1 /** 2 ****************************************************************************** 3 * @file dma_reg.h 4 * @version V1.0 5 * @date 2022-06-20 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_DMA_H__ 37 #define __HARDWARE_DMA_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define DMA_INTSTATUS_OFFSET (0x0) /* DMA_IntStatus */ 46 #define DMA_INTTCSTATUS_OFFSET (0x4) /* DMA_IntTCStatus */ 47 #define DMA_INTTCCLEAR_OFFSET (0x8) /* DMA_IntTCClear */ 48 #define DMA_INTERRORSTATUS_OFFSET (0xC) /* DMA_IntErrorStatus */ 49 #define DMA_INTERRCLR_OFFSET (0x10) /* DMA_IntErrClr */ 50 #define DMA_RAWINTTCSTATUS_OFFSET (0x14) /* DMA_RawIntTCStatus */ 51 #define DMA_RAWINTERRORSTATUS_OFFSET (0x18) /* DMA_RawIntErrorStatus */ 52 #define DMA_ENBLDCHNS_OFFSET (0x1C) /* DMA_EnbldChns */ 53 #define DMA_SOFTBREQ_OFFSET (0x20) /* DMA_SoftBReq */ 54 #define DMA_SOFTSREQ_OFFSET (0x24) /* DMA_SoftSReq */ 55 #define DMA_SOFTLBREQ_OFFSET (0x28) /* DMA_SoftLBReq */ 56 #define DMA_SOFTLSREQ_OFFSET (0x2C) /* DMA_SoftLSReq */ 57 #define DMA_TOP_CONFIG_OFFSET (0x30) /* DMA_Top_Config */ 58 #define DMA_SYNC_OFFSET (0x34) /* DMA_Sync */ 59 60 #define DMA_CxSRCADDR_OFFSET (0x00) /* DMA_CxSrcAddr */ 61 #define DMA_CxDSTADDR_OFFSET (0x04) /* DMA_CxDstAddr */ 62 #define DMA_CxLLI_OFFSET (0x08) /* DMA_CxLLI */ 63 #define DMA_CxCONTROL_OFFSET (0x0C) /* DMA_CxControl */ 64 #define DMA_CxCONFIG_OFFSET (0x10) /* DMA_CxConfig */ 65 66 /* Register Bitfield definitions *****************************************************/ 67 68 /* 0x0 : DMA_IntStatus */ 69 #define DMA_INTSTATUS_SHIFT (0U) 70 #define DMA_INTSTATUS_MASK (0xff << DMA_INTSTATUS_SHIFT) 71 72 /* 0x4 : DMA_IntTCStatus */ 73 #define DMA_INTTCSTATUS_SHIFT (0U) 74 #define DMA_INTTCSTATUS_MASK (0xff << DMA_INTTCSTATUS_SHIFT) 75 76 /* 0x8 : DMA_IntTCClear */ 77 #define DMA_INTTCCLEAR_SHIFT (0U) 78 #define DMA_INTTCCLEAR_MASK (0xff << DMA_INTTCCLEAR_SHIFT) 79 80 /* 0xC : DMA_IntErrorStatus */ 81 #define DMA_INTERRORSTATUS_SHIFT (0U) 82 #define DMA_INTERRORSTATUS_MASK (0xff << DMA_INTERRORSTATUS_SHIFT) 83 84 /* 0x10 : DMA_IntErrClr */ 85 #define DMA_INTERRCLR_SHIFT (0U) 86 #define DMA_INTERRCLR_MASK (0xff << DMA_INTERRCLR_SHIFT) 87 88 /* 0x14 : DMA_RawIntTCStatus */ 89 #define DMA_RAWINTTCSTATUS_SHIFT (0U) 90 #define DMA_RAWINTTCSTATUS_MASK (0xff << DMA_RAWINTTCSTATUS_SHIFT) 91 92 /* 0x18 : DMA_RawIntErrorStatus */ 93 #define DMA_RAWINTERRORSTATUS_SHIFT (0U) 94 #define DMA_RAWINTERRORSTATUS_MASK (0xff << DMA_RAWINTERRORSTATUS_SHIFT) 95 96 /* 0x1C : DMA_EnbldChns */ 97 #define DMA_ENABLEDCHANNELS_SHIFT (0U) 98 #define DMA_ENABLEDCHANNELS_MASK (0xff << DMA_ENABLEDCHANNELS_SHIFT) 99 100 /* 0x20 : DMA_SoftBReq */ 101 #define DMA_SOFTBREQ_SHIFT (0U) 102 #define DMA_SOFTBREQ_MASK (0xffffffff << DMA_SOFTBREQ_SHIFT) 103 104 /* 0x24 : DMA_SoftSReq */ 105 #define DMA_SOFTSREQ_SHIFT (0U) 106 #define DMA_SOFTSREQ_MASK (0xffffffff << DMA_SOFTSREQ_SHIFT) 107 108 /* 0x28 : DMA_SoftLBReq */ 109 #define DMA_SOFTLBREQ_SHIFT (0U) 110 #define DMA_SOFTLBREQ_MASK (0xffffffff << DMA_SOFTLBREQ_SHIFT) 111 112 /* 0x2C : DMA_SoftLSReq */ 113 #define DMA_SOFTLSREQ_SHIFT (0U) 114 #define DMA_SOFTLSREQ_MASK (0xffffffff << DMA_SOFTLSREQ_SHIFT) 115 116 /* 0x30 : DMA_Top_Config */ 117 #define DMA_E (1 << 0U) 118 #define DMA_M (1 << 1U) 119 120 /* 0x34 : DMA_Sync */ 121 #define DMA_SYNC_SHIFT (0U) 122 #define DMA_SYNC_MASK (0xffffffff << DMA_SYNC_SHIFT) 123 124 /* 0x100 : DMA_CxSrcAddr */ 125 #define DMA_SRCADDR_SHIFT (0U) 126 #define DMA_SRCADDR_MASK (0xffffffff << DMA_SRCADDR_SHIFT) 127 128 /* 0x104 : DMA_CxDstAddr */ 129 #define DMA_DSTADDR_SHIFT (0U) 130 #define DMA_DSTADDR_MASK (0xffffffff << DMA_DSTADDR_SHIFT) 131 132 /* 0x108 : DMA_CxLLI */ 133 #define DMA_LLI_SHIFT (0U) 134 #define DMA_LLI_MASK (0xffffffff << DMA_LLI_SHIFT) 135 136 /* 0x10C : DMA_CxControl */ 137 #define DMA_TRANSFERSIZE_SHIFT (0U) 138 #define DMA_TRANSFERSIZE_MASK (0xfff << DMA_TRANSFERSIZE_SHIFT) 139 #define DMA_SBSIZE_SHIFT (12U) 140 #if defined(BL602) 141 #define DMA_SBSIZE_MASK (0x7 << DMA_SBSIZE_SHIFT) 142 #else 143 #define DMA_SBSIZE_MASK (0x3 << DMA_SBSIZE_SHIFT) 144 #define DMA_DST_MIN_MODE (1 << 14U) 145 #endif 146 #define DMA_DBSIZE_SHIFT (15U) 147 #if defined(BL602) 148 #define DMA_DBSIZE_MASK (0x7 << DMA_DBSIZE_SHIFT) 149 #else 150 #define DMA_DBSIZE_MASK (0x3 << DMA_DBSIZE_SHIFT) 151 #define DMA_DST_ADD_MODE (1 << 17U) 152 #endif 153 #define DMA_SWIDTH_SHIFT (18U) 154 #if defined(BL602) 155 #define DMA_SWIDTH_MASK (0x7 << DMA_SWIDTH_SHIFT) 156 #else 157 #define DMA_SWIDTH_MASK (0x3 << DMA_SWIDTH_SHIFT) 158 #endif 159 #define DMA_DWIDTH_SHIFT (21U) 160 #if defined(BL602) 161 #define DMA_DWIDTH_MASK (0x7 << DMA_DWIDTH_SHIFT) 162 #define DMA_SLARGERD (1 << 24U) 163 #else 164 #define DMA_DWIDTH_MASK (0x3 << DMA_DWIDTH_SHIFT) 165 #define DMA_FIX_CNT_SHIFT (23U) 166 #define DMA_FIX_CNT_MASK (0x7 << DMA_FIX_CNT_SHIFT) 167 #endif 168 #define DMA_SI (1 << 26U) 169 #define DMA_DI (1 << 27U) 170 #define DMA_PROT_SHIFT (28U) 171 #define DMA_PROT_MASK (0x7 << DMA_PROT_SHIFT) 172 #define DMA_I (1 << 31U) 173 174 /* 0x110 : DMA_CxConfig */ 175 #define DMA_E (1 << 0U) 176 #define DMA_SRCPERIPHERAL_SHIFT (1U) 177 #define DMA_SRCPERIPHERAL_MASK (0x1f << DMA_SRCPERIPHERAL_SHIFT) 178 #define DMA_DSTPERIPHERAL_SHIFT (6U) 179 #define DMA_DSTPERIPHERAL_MASK (0x1f << DMA_DSTPERIPHERAL_SHIFT) 180 #define DMA_FLOWCNTRL_SHIFT (11U) 181 #define DMA_FLOWCNTRL_MASK (0x7 << DMA_FLOWCNTRL_SHIFT) 182 #define DMA_IE (1 << 14U) 183 #define DMA_ITC (1 << 15U) 184 #define DMA_L (1 << 16U) 185 #define DMA_A (1 << 17U) 186 #define DMA_H (1 << 18U) 187 #define DMA_LLICOUNTER_SHIFT (20U) 188 #define DMA_LLICOUNTER_MASK (0x3ff << DMA_LLICOUNTER_SHIFT) 189 190 #endif /* __HARDWARE_DMA_H__ */ 191