1 /* 2 * Copyright (c) 2006-2024, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2015-06-15 hichard first version 9 * 2024-05-25 HPMicro add strobe support 10 */ 11 12 #ifndef __DEV_MMC_H__ 13 #define __DEV_MMC_H__ 14 15 #include <rtthread.h> 16 #include <drivers/mmcsd_host.h> 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 /* 23 * EXT_CSD fields 24 */ 25 26 #define EXT_CSD_FLUSH_CACHE 32 /* W */ 27 #define EXT_CSD_CACHE_CTRL 33 /* R/W */ 28 #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ 29 #define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */ 30 #define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */ 31 #define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */ 32 #define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */ 33 #define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */ 34 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 35 #define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */ 36 #define EXT_CSD_PARTITION_SUPPORT 160 /* RO */ 37 #define EXT_CSD_HPI_MGMT 161 /* R/W */ 38 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 39 #define EXT_CSD_BKOPS_EN 163 /* R/W */ 40 #define EXT_CSD_BKOPS_START 164 /* W */ 41 #define EXT_CSD_SANITIZE_START 165 /* W */ 42 #define EXT_CSD_WR_REL_PARAM 166 /* RO */ 43 #define EXT_CSD_RPMB_MULT 168 /* RO */ 44 #define EXT_CSD_BOOT_WP 173 /* R/W */ 45 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 46 #define EXT_CSD_PART_CONFIG 179 /* R/W */ 47 #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ 48 #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 49 #define EXT_CSD_STROBE_SUPPORT 184 /* RO */ 50 #define EXT_CSD_HS_TIMING 185 /* R/W */ 51 #define EXT_CSD_POWER_CLASS 187 /* R/W */ 52 #define EXT_CSD_REV 192 /* RO */ 53 #define EXT_CSD_STRUCTURE 194 /* RO */ 54 #define EXT_CSD_CARD_TYPE 196 /* RO */ 55 #define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */ 56 #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */ 57 #define EXT_CSD_PWR_CL_52_195 200 /* RO */ 58 #define EXT_CSD_PWR_CL_26_195 201 /* RO */ 59 #define EXT_CSD_PWR_CL_52_360 202 /* RO */ 60 #define EXT_CSD_PWR_CL_26_360 203 /* RO */ 61 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 62 #define EXT_CSD_S_A_TIMEOUT 217 /* RO */ 63 #define EXT_CSD_REL_WR_SEC_C 222 /* RO */ 64 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 65 #define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ 66 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 67 #define EXT_CSD_BOOT_MULT 226 /* RO */ 68 #define EXT_CSD_SEC_TRIM_MULT 229 /* RO */ 69 #define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ 70 #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ 71 #define EXT_CSD_TRIM_MULT 232 /* RO */ 72 #define EXT_CSD_PWR_CL_200_195 236 /* RO */ 73 #define EXT_CSD_PWR_CL_200_360 237 /* RO */ 74 #define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */ 75 #define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */ 76 #define EXT_CSD_BKOPS_STATUS 246 /* RO */ 77 #define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ 78 #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ 79 #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ 80 #define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ 81 #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ 82 #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ 83 #define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */ 84 #define EXT_CSD_MAX_PACKED_READS 501 /* RO */ 85 #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ 86 #define EXT_CSD_HPI_FEATURES 503 /* RO */ 87 88 /* 89 * EXT_CSD field definitions 90 */ 91 92 #define EXT_CSD_WR_REL_PARAM_EN (1<<2) 93 94 #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40) 95 #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10) 96 #define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04) 97 #define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01) 98 99 #define EXT_CSD_PART_CONFIG_ACC_MASK (0x7) 100 #define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1) 101 #define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3) 102 #define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4) 103 104 #define EXT_CSD_PART_SUPPORT_PART_EN (0x1) 105 106 #define EXT_CSD_CMD_SET_NORMAL (1<<0) 107 #define EXT_CSD_CMD_SET_SECURE (1<<1) 108 #define EXT_CSD_CMD_SET_CPSECURE (1<<2) 109 110 #define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */ 111 #define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */ 112 #define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \ 113 EXT_CSD_CARD_TYPE_HS_52) 114 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ 115 /* DDR mode @1.8V or 3V I/O */ 116 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ 117 /* DDR mode @1.2V I/O */ 118 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ 119 | EXT_CSD_CARD_TYPE_DDR_1_2V) 120 #define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */ 121 #define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */ 122 /* SDR mode @1.2V I/O */ 123 #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ 124 EXT_CSD_CARD_TYPE_HS200_1_2V) 125 #define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */ 126 #define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */ 127 #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ 128 EXT_CSD_CARD_TYPE_HS400_1_2V) 129 130 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 131 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 132 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 133 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ 134 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ 135 #define EXT_CSD_DDR_BUS_WIDTH_8_EH_DS 0x86/* Card is in 8 bit DDR mode with Enhanced Data Strobe */ 136 137 #define EXT_CSD_TIMING_BC 0 /* Backwards compatibility */ 138 #define EXT_CSD_TIMING_HS 1 /* High speed */ 139 #define EXT_CSD_TIMING_HS200 2 /* HS200 */ 140 #define EXT_CSD_TIMING_HS400 3 /* HS400 */ 141 142 #define EXT_CSD_SEC_ER_EN BIT(0) 143 #define EXT_CSD_SEC_BD_BLK_EN BIT(2) 144 #define EXT_CSD_SEC_GB_CL_EN BIT(4) 145 #define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */ 146 147 #define EXT_CSD_RST_N_EN_MASK 0x3 148 #define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */ 149 150 #define EXT_CSD_NO_POWER_NOTIFICATION 0 151 #define EXT_CSD_POWER_ON 1 152 #define EXT_CSD_POWER_OFF_SHORT 2 153 #define EXT_CSD_POWER_OFF_LONG 3 154 155 #define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */ 156 #define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */ 157 #define EXT_CSD_PWR_CL_8BIT_SHIFT 4 158 #define EXT_CSD_PWR_CL_4BIT_SHIFT 0 159 160 #define EXT_CSD_PACKED_EVENT_EN BIT(3) 161 162 /* 163 * EXCEPTION_EVENT_STATUS field 164 */ 165 #define EXT_CSD_URGENT_BKOPS BIT(0) 166 #define EXT_CSD_DYNCAP_NEEDED BIT(1) 167 #define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2) 168 #define EXT_CSD_PACKED_FAILURE BIT(3) 169 170 #define EXT_CSD_PACKED_GENERIC_ERROR BIT(0) 171 #define EXT_CSD_PACKED_INDEXED_ERROR BIT(1) 172 173 /* 174 * BKOPS status level 175 */ 176 #define EXT_CSD_BKOPS_LEVEL_2 0x2 177 /* 178 * MMC_SWITCH access modes 179 */ 180 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 181 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */ 182 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ 183 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ 184 185 /* 186 * extern function 187 */ 188 rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, rt_uint32_t ocr, rt_uint32_t *rocr); 189 rt_int32_t init_mmc(struct rt_mmcsd_host *host, rt_uint32_t ocr); 190 191 #ifdef __cplusplus 192 } 193 #endif 194 195 #endif 196