1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2011-07-25 weety first version 9 * 2024-05-26 HPMicro add VOLTAGE_SWITCH definition 10 */ 11 12 #ifndef __CMD_H__ 13 #define __CMD_H__ 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 /* class 1 */ 20 #define GO_IDLE_STATE 0 /* bc */ 21 #define SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ 22 #define ALL_SEND_CID 2 /* bcr R2 */ 23 #define SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ 24 #define SET_DSR 4 /* bc [31:16] RCA */ 25 #define SWITCH 6 /* ac [31:0] See below R1b */ 26 #define SELECT_CARD 7 /* ac [31:16] RCA R1 */ 27 #define SEND_EXT_CSD 8 /* adtc R1 */ 28 #define SEND_CSD 9 /* ac [31:16] RCA R2 */ 29 #define SEND_CID 10 /* ac [31:16] RCA R2 */ 30 #define VOLTAGE_SWITCH 11 /* ac [31:0] R1 */ 31 #define STOP_TRANSMISSION 12 /* ac R1b */ 32 #define SEND_STATUS 13 /* ac [31:16] RCA R1 */ 33 #define GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ 34 #define SPI_READ_OCR 58 /* spi spi_R3 */ 35 #define SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ 36 37 /* class 2 */ 38 #define SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ 39 #define READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ 40 #define READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ 41 #define SEND_TUNING_BLOCK 19 /* adtc R1 */ 42 #define SEND_TUNING_BLOCK_HS200 21 /* adtc R1*/ 43 /* class 3 */ 44 #define WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ 45 46 /* class 4 */ 47 #define SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ 48 #define WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ 49 #define WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ 50 #define PROGRAM_CID 26 /* adtc R1 */ 51 #define PROGRAM_CSD 27 /* adtc R1 */ 52 53 /* class 6 */ 54 #define SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ 55 #define CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ 56 #define SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ 57 58 /* class 5 */ 59 #define ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ 60 #define ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ 61 #define ERASE 38 /* ac R1b */ 62 63 /* class 9 */ 64 #define FAST_IO 39 /* ac <Complex> R4 */ 65 #define GO_IRQ_STATE 40 /* bcr R5 */ 66 67 /* class 7 */ 68 #define LOCK_UNLOCK 42 /* adtc R1b */ 69 70 /* class 8 */ 71 #define APP_CMD 55 /* ac [31:16] RCA R1 */ 72 #define GEN_CMD 56 /* adtc [0] RD/WR R1 */ 73 74 75 /* SD commands type argument response */ 76 /* class 0 */ 77 /* This is basically the same command as for MMC with some quirks. */ 78 #define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */ 79 #define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */ 80 81 /* class 10 */ 82 #define SD_SWITCH 6 /* adtc [31:0] See below R1 */ 83 84 /* Application commands */ 85 #define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ 86 #define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */ 87 #define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ 88 #define SD_APP_SEND_SCR 51 /* adtc R1 */ 89 90 #define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */ 91 #define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */ 92 #define SCR_SPEC_VER_2 2 /* Implements system specification 2.00 */ 93 94 95 /* SDIO commands type argument response */ 96 #define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */ 97 #define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */ 98 #define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */ 99 100 101 /* CMD52 arguments */ 102 #define SDIO_ARG_CMD52_READ (0<<31) 103 #define SDIO_ARG_CMD52_WRITE (1u<<31) 104 #define SDIO_ARG_CMD52_FUNC_SHIFT 28 105 #define SDIO_ARG_CMD52_FUNC_MASK 0x7 106 #define SDIO_ARG_CMD52_RAW_FLAG (1u<<27) 107 #define SDIO_ARG_CMD52_REG_SHIFT 9 108 #define SDIO_ARG_CMD52_REG_MASK 0x1ffff 109 #define SDIO_ARG_CMD52_DATA_SHIFT 0 110 #define SDIO_ARG_CMD52_DATA_MASK 0xff 111 #define SDIO_R5_DATA(resp) ((resp)[0] & 0xff) 112 113 /* CMD53 arguments */ 114 #define SDIO_ARG_CMD53_READ (0<<31) 115 #define SDIO_ARG_CMD53_WRITE (1u<<31) 116 #define SDIO_ARG_CMD53_FUNC_SHIFT 28 117 #define SDIO_ARG_CMD53_FUNC_MASK 0x7 118 #define SDIO_ARG_CMD53_BLOCK_MODE (1u<<27) 119 #define SDIO_ARG_CMD53_INCREMENT (1u<<26) 120 #define SDIO_ARG_CMD53_REG_SHIFT 9 121 #define SDIO_ARG_CMD53_REG_MASK 0x1ffff 122 #define SDIO_ARG_CMD53_LENGTH_SHIFT 0 123 #define SDIO_ARG_CMD53_LENGTH_MASK 0x1ff 124 #define SDIO_ARG_CMD53_LENGTH_MAX 511 125 126 127 #ifdef __cplusplus 128 } 129 #endif 130 131 #endif 132