1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2018-11-19     zylx         first version
9  */
10 
11 #include "board.h"
12 
13 #ifdef BSP_USING_EXT_FMC_IO
14 
15 //#define DRV_DEBUG
16 #define LOG_TAG             "drv.ext_io"
17 #include <drv_log.h>
18 
19 #include "drv_ext_io.h"
20 #define  HC574_PORT  *(volatile rt_uint32_t *)0x64001000
21 
22 volatile rt_uint32_t HC574_state = 0;
23 
HC574_SetPin(rt_uint32_t _pin,uint8_t _value)24 void HC574_SetPin(rt_uint32_t _pin, uint8_t _value)
25 {
26     if (_value == 0)
27     {
28         HC574_state &= (~_pin);
29     }
30     else
31     {
32         HC574_state |= _pin;
33     }
34 
35     HC574_PORT = HC574_state;
36 }
37 
HC574_GetPin(rt_uint32_t _pin)38 rt_uint8_t HC574_GetPin(rt_uint32_t _pin)
39 {
40     if (HC574_state & _pin)
41     {
42         return 1;
43     }
44     else
45     {
46         return 0;
47     }
48 }
49 
HC574_Config_FMC(void)50 static void HC574_Config_FMC(void)
51 {
52     FMC_NORSRAM_TimingTypeDef timing = {0};
53     SRAM_HandleTypeDef sram2 = {0};
54 
55     /*
56         For LCD compatibility，select 3-0-6-1-0-0
57         3-0-5-1-0-0  : RD high level 75ns，low level 50ns. Read 8 channels of data into memory in 1us.
58         1-0-1-1-0-0  : RD high level 75ns，low level 12ns，trailing edge 12ns.
59     */
60     /* FMC_Bank1_NORSRAM2 configuration */
61     timing.AddressSetupTime = 3;
62     timing.AddressHoldTime = 0;
63     timing.DataSetupTime = 6;
64     timing.BusTurnAroundDuration = 1;
65     timing.CLKDivision = 0;
66     timing.DataLatency = 0;
67     timing.AccessMode = FMC_ACCESS_MODE_A;
68 
69     /*
70      LCD configured as follow:
71         - Data/Address MUX = Disable
72         - Memory Type = SRAM
73         - Data Width = 32bit
74         - Write Operation = Enable
75         - Extended Mode = Enable
76         - Asynchronous Wait = Disable
77     */
78     sram2.Instance = FMC_NORSRAM_DEVICE;
79     sram2.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
80 
81     sram2.Init.NSBank = FMC_NORSRAM_BANK2;
82     sram2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
83     sram2.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
84     sram2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32;
85     sram2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
86     sram2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
87     sram2.Init.WrapMode = FMC_WRAP_MODE_DISABLE;
88     sram2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
89     sram2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
90     sram2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
91     sram2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
92     sram2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
93     sram2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
94     sram2.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
95     sram2.Init.PageSize = FMC_PAGE_SIZE_1024;
96 
97     if (HAL_SRAM_Init(&sram2, &timing, NULL) != HAL_OK)
98     {
99         LOG_E("extend IO init failed!");
100     }
101     else
102     {
103         LOG_D("extend IO init success");
104     }
105 }
106 
stm32_ext_io_init(void)107 static int stm32_ext_io_init(void)
108 {
109     HC574_Config_FMC();
110     /* Set the chip select to high level */
111     HC574_state = (NRF24L01_CE | VS1053_XDCS | LED1 | LED2 | LED3 | LED4 );
112     /* Change IO state */
113     HC574_PORT = HC574_state;
114 
115     return RT_EOK;
116 }
117 INIT_BOARD_EXPORT(stm32_ext_io_init);
118 #endif /* BSP_USING_EXT_FMC_IO */
119