1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2022-08-15 xjy198903 the first version
9 * 2024-04-18 Jiading add a parameter passed into rt_phy_ops APIs
10 */
11 #include <rtthread.h>
12
13 #ifdef PHY_USING_RTL8211F
14
15 #include <rtdevice.h>
16 #include "drv_gpio.h"
17 #include "drv_mdio.h"
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23 /*! @note The following PHY registers are the IEEE802.3 standard definition, same register and bit field may
24 have different names in various PHYs, but the feature they represent should be same or very similar. */
25
26 /*! @brief Defines the IEEE802.3 standard PHY registers. */
27 #define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
28 #define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
29 #define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
30 #define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
31 #define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
32 #define PHY_AUTONEG_LINKPARTNER_REG 0x05U /*!< The PHY auto negotiation link partner ability register. */
33 #define PHY_AUTONEG_EXPANSION_REG 0x06U /*!< The PHY auto negotiation expansion register. */
34 #define PHY_1000BASET_CONTROL_REG 0x09U /*!< The PHY 1000BASE-T control register. */
35 #define PHY_MMD_ACCESS_CONTROL_REG 0x0DU /*!< The PHY MMD access control register. */
36 #define PHY_MMD_ACCESS_DATA_REG 0x0EU /*!< The PHY MMD access data register. */
37
38 /*! @brief Defines the mask flag in basic control register(Address 0x00). */
39 #define PHY_BCTL_SPEED1_MASK 0x0040U /*!< The PHY speed bit mask(MSB).*/
40 #define PHY_BCTL_ISOLATE_MASK 0x0400U /*!< The PHY isolate mask.*/
41 #define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
42 #define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
43 #define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
44 #define PHY_BCTL_SPEED0_MASK 0x2000U /*!< The PHY speed bit mask(LSB). */
45 #define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
46 #define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
47
48 /*! @brief Defines the mask flag in basic status register(Address 0x01). */
49 #define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
50 #define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
51 #define PHY_BSTATUS_SPEEDUPLX_MASK 0x001CU /*!< The PHY speed and duplex mask. */
52 #define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
53
54 /*! @brief Defines the mask flag in PHY auto-negotiation advertise register(Address 0x04). */
55 #define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
56 #define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
57 #define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
58 #define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
59 #define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
60 #define PHY_IEEE802_3_SELECTOR_MASK 0x001U /*!< The message type being sent by Auto-Nego.*/
61
62 /*! @brief Defines the mask flag in the 1000BASE-T control register(Address 0x09). */
63 #define PHY_1000BASET_FULLDUPLEX_MASK 0x200U /*!< The PHY has the 1000M full duplex ability.*/
64 #define PHY_1000BASET_HALFDUPLEX_MASK 0x100U /*!< The PHY has the 1000M half duplex ability.*/
65
66 /*! @brief Defines the PHY RTL8211F vendor defined registers. */
67 #define PHY_SPECIFIC_STATUS_REG 0x1AU /*!< The PHY specific status register. */
68 #define PHY_PAGE_SELECT_REG 0x1FU /*!< The PHY page select register. */
69
70 /*! @brief Defines the PHY RTL8211F ID number. */
71 #define PHY_CONTROL_ID1 0x001CU /*!< The PHY ID1 . */
72
73 /*! @brief Defines the mask flag in specific status register. */
74 #define PHY_SSTATUS_LINKSTATUS_MASK 0x04U /*!< The PHY link status mask. */
75 #define PHY_SSTATUS_LINKSPEED_MASK 0x30U /*!< The PHY link speed mask. */
76 #define PHY_SSTATUS_LINKDUPLEX_MASK 0x08U /*!< The PHY link duplex mask. */
77 #define PHY_SSTATUS_LINKSPEED_SHIFT 4U /*!< The link speed shift */
78
79 /*! @brief Defines the PHY RTL8211F extra page and the registers in specified page. */
80 #define PHY_PAGE_RGMII_TXRX_DELAY_ADDR 0xD08U /*!< The register page including RGMII TX/RX delay setting. */
81 #define PHY_RGMII_TX_DELAY_REG 0x11U /*!< The RGMII TXC delay register. */
82 #define PHY_RGMII_RX_DELAY_REG 0x15U /*!< The RGMII RXC delay register. */
83 #define PHY_RGMII_TX_DELAY_MASK 0x100U /*!< The RGMII TXC delay mask. */
84 #define PHY_RGMII_RX_DELAY_MASK 0x8U /*!< The RGMII RXC delay mask. */
85
86 /*! @brief MDIO MMD Devices .*/
87 #define PHY_MDIO_MMD_PCS 3U
88 #define PHY_MDIO_MMD_AN 7U
89
90 /*! @brief MDIO MMD Physical Coding layer device registers .*/
91 #define PHY_MDIO_PCS_EEE_CAP 0x14U /* EEE capability */
92
93 /*! @brief MDIO MMD AutoNegotiation device registers .*/
94 #define PHY_MDIO_AN_EEE_ADV 0x3CU /* EEE advertisement */
95
96 /*! @brief MDIO MMD EEE mask flags. (common for adv and cap) */
97 #define PHY_MDIO_EEE_100TX 0x2U
98 #define PHY_MDIO_EEE_1000T 0x4U
99
100 /*! @brief Defines the timeout macro. */
101 #define PHY_READID_TIMEOUT_COUNT 1000U
102
103 /* defined the Reset pin, PORT and PIN config by menuconfig */
104 #define RESET_PIN GET_PIN(PHY_RESET_RTL8211F_PORT, PHY_RESET_RTL8211F_PIN)
105
106 /*! @brief Defines the PHY MMD data access mode. */
107 typedef enum _phy_mmd_access_mode
108 {
109 kPHY_MMDAccessNoPostIncrement = (1U << 14), /*!< ENET PHY MMD access data with no address post increment. */
110 kPHY_MMDAccessRdWrPostIncrement =
111 (2U << 14), /*!< ENET PHY MMD access data with Read/Write address post increment. */
112 kPHY_MMDAccessWrPostIncrement = (3U << 14), /*!< ENET PHY MMD access data with Write address post increment. */
113 } phy_mmd_access_mode_t;
114
115 /*******************************************************************************
116 * Prototypes
117 ******************************************************************************/
118
119 /*******************************************************************************
120 * Variables
121 ******************************************************************************/
122
123 static struct rt_phy_device phy_rtl8211f;
124
125 /*******************************************************************************
126 * Code
127 ******************************************************************************/
128
read_reg(rt_mdio_t * bus,rt_uint32_t addr,rt_uint32_t reg_id,rt_uint32_t * value)129 static inline rt_bool_t read_reg(rt_mdio_t *bus, rt_uint32_t addr, rt_uint32_t reg_id, rt_uint32_t *value)
130 {
131 if (4 != bus->ops->read(bus, addr, reg_id, value, 4))
132 {
133 return RT_FALSE;
134 }
135 return RT_TRUE;
136 }
137
write_reg(rt_mdio_t * bus,rt_uint32_t addr,rt_uint32_t reg_id,rt_uint32_t value)138 static inline rt_bool_t write_reg(rt_mdio_t *bus, rt_uint32_t addr, rt_uint32_t reg_id, rt_uint32_t value)
139 {
140 if (4 != bus->ops->write(bus, addr, reg_id, &value, 4))
141 {
142 return RT_FALSE;
143 }
144 return RT_TRUE;
145 }
146
PHY_RTL8211F_MMD_WriteData(uint32_t data)147 static inline status_t PHY_RTL8211F_MMD_WriteData(uint32_t data)
148 {
149 return phy_rtl8211f.ops->write(PHY_MMD_ACCESS_DATA_REG, data);
150 }
151
PHY_RTL8211F_MMD_SetDevice(uint8_t device,uint16_t addr,phy_mmd_access_mode_t mode)152 static status_t PHY_RTL8211F_MMD_SetDevice(uint8_t device,
153 uint16_t addr,
154 phy_mmd_access_mode_t mode)
155 {
156 status_t result = PHY_STATUS_OK;
157
158 /* Set Function mode of address access(b00) and device address. */
159 result = phy_rtl8211f.ops->write(PHY_MMD_ACCESS_CONTROL_REG, device);
160 if (result != PHY_STATUS_OK)
161 {
162 return result;
163 }
164
165 /* Set register address. */
166 result = phy_rtl8211f.ops->write(PHY_MMD_ACCESS_DATA_REG, addr);
167 if (result != PHY_STATUS_OK)
168 {
169 return result;
170 }
171
172 /* Set Function mode of data access(b01~11) and device address. */
173 result = phy_rtl8211f.ops->write(PHY_MMD_ACCESS_CONTROL_REG, (uint32_t)mode | (uint32_t)device);
174 return result;
175 }
176
PHY_RTL8211F_MMD_Write(uint8_t device,uint16_t addr,uint32_t data)177 static status_t PHY_RTL8211F_MMD_Write(uint8_t device, uint16_t addr, uint32_t data)
178 {
179 status_t result = PHY_STATUS_OK;
180
181 result = PHY_RTL8211F_MMD_SetDevice(device, addr, kPHY_MMDAccessNoPostIncrement);
182 if (result == PHY_STATUS_OK)
183 {
184 result = PHY_RTL8211F_MMD_WriteData(data);
185 }
186 return result;
187 }
188
rt_phy_init(void * object,rt_uint32_t phy_addr,rt_uint32_t src_clock_hz)189 static rt_phy_status rt_phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz)
190 {
191 rt_bool_t ret;
192 rt_phy_status result;
193 rt_uint32_t counter = PHY_READID_TIMEOUT_COUNT;
194 rt_uint32_t regValue = 0U;
195
196 // reset phy device by gpio
197 rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT);
198 rt_pin_write(RESET_PIN, PIN_LOW);
199 rt_thread_mdelay(10);
200 rt_pin_write(RESET_PIN, PIN_HIGH);
201 rt_thread_mdelay(30);
202
203 rt_mdio_t *mdio_bus = rt_hw_mdio_register(object, "phy_mdio");
204 if (RT_NULL == mdio_bus)
205 {
206 return PHY_STATUS_FAIL;
207 }
208 phy_rtl8211f.bus = mdio_bus;
209 phy_rtl8211f.addr = phy_addr;
210 ret = mdio_bus->ops->init(mdio_bus, src_clock_hz);
211 if (!ret)
212 {
213 return PHY_STATUS_FAIL;
214 }
215
216 /* Check PHY ID. */
217 do
218 {
219 result = phy_rtl8211f.ops->read(NULL, PHY_ID1_REG, ®Value);
220 if (result != PHY_STATUS_OK)
221 {
222 return result;
223 }
224 counter--;
225 } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U));
226
227 if (counter == 0U)
228 {
229 return PHY_STATUS_FAIL;
230 }
231
232 /* Reset PHY. */
233 result = phy_rtl8211f.ops->write(PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
234 if (result != PHY_STATUS_OK)
235 {
236 return result;
237 }
238
239 /* The RGMII specifies output TXC/RXC and TXD/RXD without any clock skew. Need to add skew on clock line
240 to make sure the other side sample right data. This can also be done in PCB traces. */
241 result = phy_rtl8211f.ops->write(PHY_PAGE_SELECT_REG, PHY_PAGE_RGMII_TXRX_DELAY_ADDR);
242 if (PHY_STATUS_OK != result)
243 {
244 return result;
245 }
246
247 /* Set Tx Delay */
248 result = phy_rtl8211f.ops->read(NULL, PHY_RGMII_TX_DELAY_REG, ®Value);
249 if (PHY_STATUS_OK == result)
250 {
251 regValue |= PHY_RGMII_TX_DELAY_MASK;
252 result = phy_rtl8211f.ops->write(PHY_RGMII_TX_DELAY_REG, regValue);
253 if (result != PHY_STATUS_OK)
254 {
255 return result;
256 }
257 }
258 else
259 {
260 return result;
261 }
262
263 /* Set Rx Delay */
264 result = phy_rtl8211f.ops->read(NULL, PHY_RGMII_RX_DELAY_REG, ®Value);
265 if (PHY_STATUS_OK == result)
266 {
267 regValue |= PHY_RGMII_RX_DELAY_MASK;
268 result = phy_rtl8211f.ops->write(PHY_RGMII_RX_DELAY_REG, regValue);
269 if (result != PHY_STATUS_OK)
270 {
271 return result;
272 }
273 }
274 else
275 {
276 return result;
277 }
278
279 /* Restore to default page 0 */
280 result = phy_rtl8211f.ops->write(PHY_PAGE_SELECT_REG, 0x0);
281 if (result != PHY_STATUS_OK)
282 {
283 return result;
284 }
285
286 // disabled EEE
287 result = PHY_RTL8211F_MMD_Write(PHY_MDIO_MMD_AN, PHY_MDIO_AN_EEE_ADV, 0);
288 if (result != PHY_STATUS_OK)
289 {
290 return result;
291 }
292
293 /* Set the auto-negotiation. */
294 result = phy_rtl8211f.ops->write(PHY_AUTONEG_ADVERTISE_REG,
295 PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | PHY_10BASETX_FULLDUPLEX_MASK |
296 PHY_10BASETX_HALFDUPLEX_MASK | PHY_IEEE802_3_SELECTOR_MASK);
297 if (result == PHY_STATUS_OK)
298 {
299 result = phy_rtl8211f.ops->write(PHY_1000BASET_CONTROL_REG, PHY_1000BASET_FULLDUPLEX_MASK);
300 if (result == PHY_STATUS_OK)
301 {
302 result = phy_rtl8211f.ops->read(NULL, PHY_BASICCONTROL_REG, ®Value);
303 if (result == PHY_STATUS_OK)
304 {
305 result = phy_rtl8211f.ops->write(PHY_BASICCONTROL_REG, (regValue | PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
306 }
307 }
308 }
309
310 return result;
311 }
312
rt_phy_read(rt_phy_t * phy,rt_uint32_t reg,rt_uint32_t * data)313 static rt_phy_status rt_phy_read(rt_phy_t *phy, rt_uint32_t reg, rt_uint32_t *data)
314 {
315 rt_mdio_t *mdio_bus = phy_rtl8211f.bus;
316 rt_uint32_t device_id = phy_rtl8211f.addr;
317
318 if (read_reg(mdio_bus, device_id, reg, data))
319 {
320 return PHY_STATUS_OK;
321 }
322 return PHY_STATUS_FAIL;
323 }
324
rt_phy_write(rt_phy_t * phy,rt_uint32_t reg,rt_uint32_t data)325 static rt_phy_status rt_phy_write(rt_phy_t *phy, rt_uint32_t reg, rt_uint32_t data)
326 {
327 rt_mdio_t *mdio_bus = phy_rtl8211f.bus;
328 rt_uint32_t device_id = phy_rtl8211f.addr;
329
330 if (write_reg(mdio_bus, device_id, reg, data))
331 {
332 return PHY_STATUS_OK;
333 }
334 return PHY_STATUS_FAIL;
335 }
336
rt_phy_loopback(rt_phy_t * phy,rt_uint32_t mode,rt_uint32_t speed,rt_bool_t enable)337 static rt_phy_status rt_phy_loopback(rt_phy_t *phy, rt_uint32_t mode, rt_uint32_t speed, rt_bool_t enable)
338 {
339 /* This PHY only supports local loopback. */
340 // rt_assert(mode == PHY_LOCAL_LOOP);
341
342 status_t result;
343 uint32_t regValue;
344
345 /* Set the loop mode. */
346 if (enable)
347 {
348 if (speed == PHY_SPEED_1000M)
349 {
350 regValue = PHY_BCTL_SPEED1_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
351 }
352 else if (speed == PHY_SPEED_100M)
353 {
354 regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
355 }
356 else
357 {
358 regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
359 }
360 result = phy_rtl8211f.ops->write(PHY_BASICCONTROL_REG, regValue);
361 }
362 else
363 {
364 /* First read the current status in control register. */
365 result = phy_rtl8211f.ops->read(NULL, PHY_BASICCONTROL_REG, ®Value);
366 if (result == PHY_STATUS_OK)
367 {
368 regValue &= ~PHY_BCTL_LOOP_MASK;
369 result = phy_rtl8211f.ops->write(PHY_BASICCONTROL_REG, (regValue | PHY_BCTL_RESTART_AUTONEG_MASK));
370 }
371 }
372 return result;
373 }
374
get_link_status(rt_phy_t * phy,rt_bool_t * status)375 static rt_phy_status get_link_status(rt_phy_t *phy, rt_bool_t *status)
376 {
377 // assert(status);
378
379 status_t result;
380 uint32_t regValue;
381
382 /* Read the basic status register. */
383 result = phy_rtl8211f.ops->read(PHY_SPECIFIC_STATUS_REG, ®Value);
384 if (result == PHY_STATUS_OK)
385 {
386 if ((PHY_SSTATUS_LINKSTATUS_MASK & regValue) != 0U)
387 {
388 /* Link up. */
389 *status = true;
390 }
391 else
392 {
393 /* Link down. */
394 *status = false;
395 }
396 }
397 return result;
398 }
399
get_link_speed_duplex(rt_phy_t * phy,rt_uint32_t * speed,rt_uint32_t * duplex)400 static rt_phy_status get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex)
401 {
402 // assert(!((speed == NULL) && (duplex == NULL)));
403
404 status_t result;
405 uint32_t regValue;
406
407 /* Read the status register. */
408 result = phy_rtl8211f.ops->read(NULL, PHY_SPECIFIC_STATUS_REG, ®Value);
409 if (result == PHY_STATUS_OK)
410 {
411 if (speed != NULL)
412 {
413 switch ((regValue & PHY_SSTATUS_LINKSPEED_MASK) >> PHY_SSTATUS_LINKSPEED_SHIFT)
414 {
415 case (uint32_t)PHY_SPEED_10M:
416 *speed = PHY_SPEED_10M;
417 break;
418 case (uint32_t)PHY_SPEED_100M:
419 *speed = PHY_SPEED_100M;
420 break;
421 case (uint32_t)PHY_SPEED_1000M:
422 *speed = PHY_SPEED_1000M;
423 break;
424 default:
425 *speed = PHY_SPEED_10M;
426 break;
427 }
428 }
429
430 if (duplex != NULL)
431 {
432 if ((regValue & PHY_SSTATUS_LINKDUPLEX_MASK) != 0U)
433 {
434 *duplex = PHY_FULL_DUPLEX;
435 }
436 else
437 {
438 *duplex = PHY_HALF_DUPLEX;
439 }
440 }
441 }
442 return result;
443 }
444
445 static struct rt_phy_ops phy_ops =
446 {
447 .init = rt_phy_init,
448 .read = rt_phy_read,
449 .write = rt_phy_write,
450 .loopback = rt_phy_loopback,
451 .get_link_status = get_link_status,
452 .get_link_speed_duplex = get_link_speed_duplex,
453 };
454
rt_phy_rtl8211f_register(void)455 static int rt_phy_rtl8211f_register(void)
456 {
457 phy_rtl8211f.ops = &phy_ops;
458 rt_hw_phy_register(&phy_rtl8211f, "rtl8211f");
459 return 1;
460 }
461
462 INIT_DEVICE_EXPORT(rt_phy_rtl8211f_register);
463 #endif /* PHY_USING_RTL8211F */
464