1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2018-12-10 zylx first version
9 * 2020-06-16 thread-liu Porting for stm32mp1
10 * 2020-08-25 linyongkang Fix the timer clock frequency doubling problem
11 * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
12 * 2020-11-18 leizhixiong add STM32H7 series support
13 * 2023-08-21 Donocean fix the MCU crash when using timer6
14 * 2023-12-24 Meco Man add TIMx existing check
15 */
16
17 #include <rtdevice.h>
18 #include "drv_config.h"
19
20 //#define DRV_DEBUG
21 #define LOG_TAG "drv.tim"
22 #include <drv_log.h>
23
24 #if defined(BSP_USING_TIM1) && !defined(TIM1)
25 #error "timer1 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM1"
26 #endif
27 #if defined(BSP_USING_TIM2) && !defined(TIM2)
28 #error "timer2 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM2"
29 #endif
30 #if defined(BSP_USING_TIM3) && !defined(TIM3)
31 #error "timer3 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM3"
32 #endif
33 #if defined(BSP_USING_TIM4) && !defined(TIM4)
34 #error "timer4 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM4"
35 #endif
36 #if defined(BSP_USING_TIM5) && !defined(TIM5)
37 #error "timer5 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM5"
38 #endif
39 #if defined(BSP_USING_TIM6) && !defined(TIM6)
40 #error "timer6 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM6"
41 #endif
42 #if defined(BSP_USING_TIM7) && !defined(TIM7)
43 #error "timer7 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM7"
44 #endif
45 #if defined(BSP_USING_TIM8) && !defined(TIM8)
46 #error "timer8 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM8"
47 #endif
48 #if defined(BSP_USING_TIM9) && !defined(TIM9)
49 #error "timer9 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM9"
50 #endif
51 #if defined(BSP_USING_TIM10) && !defined(TIM10)
52 #error "timer10 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM10"
53 #endif
54 #if defined(BSP_USING_TIM11) && !defined(TIM11)
55 #error "timer11 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM11"
56 #endif
57 #if defined(BSP_USING_TIM12) && !defined(TIM12)
58 #error "timer12 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM12"
59 #endif
60 #if defined(BSP_USING_TIM13) && !defined(TIM13)
61 #error "timer13 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM13"
62 #endif
63 #if defined(BSP_USING_TIM14) && !defined(TIM14)
64 #error "timer14 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM14"
65 #endif
66 #if defined(BSP_USING_TIM15) && !defined(TIM15)
67 #error "timer15 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM15"
68 #endif
69 #if defined(BSP_USING_TIM16) && !defined(TIM16)
70 #error "timer16 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM16"
71 #endif
72 #if defined(BSP_USING_TIM17) && !defined(TIM17)
73 #error "timer17 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM17"
74 #endif
75 #if defined(BSP_USING_TIM18) && !defined(TIM18)
76 #error "timer18 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM18"
77 #endif
78 #if defined(BSP_USING_TIM19) && !defined(TIM19)
79 #error "timer19 doesn't exist in this STM32 series, but you enabled the BSP_USING_TIM19"
80 #endif
81
82 /* APBx timer clocks frequency doubler state related to APB1CLKDivider value */
stm32_tim_pclkx_doubler_get(rt_uint32_t * pclk1_doubler,rt_uint32_t * pclk2_doubler)83 void stm32_tim_pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
84 {
85 rt_uint32_t flatency = 0;
86 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
87
88 RT_ASSERT(pclk1_doubler != RT_NULL);
89 RT_ASSERT(pclk1_doubler != RT_NULL);
90
91 HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &flatency);
92
93 *pclk1_doubler = 1;
94 *pclk2_doubler = 1;
95
96 #if defined(SOC_SERIES_STM32MP1)
97 if (RCC_ClkInitStruct.APB1_Div != RCC_APB1_DIV1)
98 {
99 *pclk1_doubler = 2;
100 }
101 if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
102 {
103 *pclk2_doubler = 2;
104 }
105 #else
106 if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
107 {
108 *pclk1_doubler = 2;
109 }
110 #if !(defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0))
111 if (RCC_ClkInitStruct.APB2CLKDivider != RCC_HCLK_DIV1)
112 {
113 *pclk2_doubler = 2;
114 }
115 #endif /* !(defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)) */
116 #endif /* defined(SOC_SERIES_STM32MP1) */
117 }
118
stm32_tim_enable_clock(TIM_HandleTypeDef * htim_base)119 void stm32_tim_enable_clock(TIM_HandleTypeDef* htim_base)
120 {
121 RT_ASSERT(htim_base != RT_NULL);
122
123 if(RT_FALSE);
124 #ifdef TIM1
125 else if(htim_base->Instance==TIM1)
126 {
127 __HAL_RCC_TIM1_CLK_ENABLE();
128 }
129 #endif /* TIM1 */
130 #ifdef TIM2
131 else if(htim_base->Instance==TIM2)
132 {
133 __HAL_RCC_TIM2_CLK_ENABLE();
134 }
135 #endif /* TIM2 */
136 #ifdef TIM3
137 else if(htim_base->Instance==TIM3)
138 {
139 __HAL_RCC_TIM3_CLK_ENABLE();
140 }
141 #endif /* TIM3 */
142 #ifdef TIM4
143 else if(htim_base->Instance==TIM4)
144 {
145 __HAL_RCC_TIM4_CLK_ENABLE();
146 }
147 #endif /* TIM4 */
148 #ifdef TIM5
149 else if(htim_base->Instance==TIM5)
150 {
151 __HAL_RCC_TIM5_CLK_ENABLE();
152 }
153 #endif /* TIM5 */
154 #ifdef TIM6
155 else if(htim_base->Instance==TIM6)
156 {
157 __HAL_RCC_TIM6_CLK_ENABLE();
158 }
159 #endif /* TIM6 */
160 #ifdef TIM7
161 else if(htim_base->Instance==TIM7)
162 {
163 __HAL_RCC_TIM7_CLK_ENABLE();
164 }
165 #endif /* TIM7 */
166 #ifdef TIM8
167 else if(htim_base->Instance==TIM8)
168 {
169 __HAL_RCC_TIM8_CLK_ENABLE();
170 }
171 #endif /* TIM8 */
172 #ifdef TIM9
173 else if(htim_base->Instance==TIM9)
174 {
175 __HAL_RCC_TIM9_CLK_ENABLE();
176 }
177 #endif /* TIM9 */
178 #ifdef TIM10
179 else if(htim_base->Instance==TIM10)
180 {
181 __HAL_RCC_TIM10_CLK_ENABLE();
182 }
183 #endif /* TIM10 */
184 #ifdef TIM11
185 else if(htim_base->Instance==TIM11)
186 {
187 __HAL_RCC_TIM11_CLK_ENABLE();
188 }
189 #endif /* TIM11 */
190 #ifdef TIM12
191 else if(htim_base->Instance==TIM12)
192 {
193 __HAL_RCC_TIM12_CLK_ENABLE();
194 }
195 #endif /* TIM12 */
196 #ifdef TIM13
197 else if(htim_base->Instance==TIM13)
198 {
199 __HAL_RCC_TIM13_CLK_ENABLE();
200 }
201 #endif /* TIM13 */
202 #ifdef TIM14
203 else if(htim_base->Instance==TIM14)
204 {
205 __HAL_RCC_TIM14_CLK_ENABLE();
206 }
207 #endif /* TIM14 */
208 #ifdef TIM15
209 else if(htim_base->Instance==TIM15)
210 {
211 __HAL_RCC_TIM15_CLK_ENABLE();
212 }
213 #endif /* TIM15 */
214 #ifdef TIM16
215 else if(htim_base->Instance==TIM16)
216 {
217 __HAL_RCC_TIM16_CLK_ENABLE();
218 }
219 #endif /* TIM16 */
220 #ifdef TIM17
221 else if(htim_base->Instance==TIM17)
222 {
223 __HAL_RCC_TIM17_CLK_ENABLE();
224 }
225 #endif /* TIM17 */
226 #ifdef TIM18
227 else if(htim_base->Instance==TIM18)
228 {
229 __HAL_RCC_TIM18_CLK_ENABLE();
230 }
231 #endif /* TIM18 */
232 #ifdef TIM19
233 else if(htim_base->Instance==TIM19)
234 {
235 __HAL_RCC_TIM19_CLK_ENABLE();
236 }
237 #endif /* TIM19 */
238 else
239 {
240 RT_ASSERT(RT_TRUE);
241 }
242 }
243
244 #ifdef BSP_USING_TIM
245
246 enum
247 {
248 #ifdef BSP_USING_TIM1
249 TIM1_INDEX,
250 #endif
251 #ifdef BSP_USING_TIM2
252 TIM2_INDEX,
253 #endif
254 #ifdef BSP_USING_TIM3
255 TIM3_INDEX,
256 #endif
257 #ifdef BSP_USING_TIM4
258 TIM4_INDEX,
259 #endif
260 #ifdef BSP_USING_TIM5
261 TIM5_INDEX,
262 #endif
263 #ifdef BSP_USING_TIM6
264 TIM6_INDEX,
265 #endif
266 #ifdef BSP_USING_TIM7
267 TIM7_INDEX,
268 #endif
269 #ifdef BSP_USING_TIM8
270 TIM8_INDEX,
271 #endif
272 #ifdef BSP_USING_TIM9
273 TIM9_INDEX,
274 #endif
275 #ifdef BSP_USING_TIM10
276 TIM10_INDEX,
277 #endif
278 #ifdef BSP_USING_TIM11
279 TIM11_INDEX,
280 #endif
281 #ifdef BSP_USING_TIM12
282 TIM12_INDEX,
283 #endif
284 #ifdef BSP_USING_TIM13
285 TIM13_INDEX,
286 #endif
287 #ifdef BSP_USING_TIM14
288 TIM14_INDEX,
289 #endif
290 #ifdef BSP_USING_TIM15
291 TIM15_INDEX,
292 #endif
293 #ifdef BSP_USING_TIM16
294 TIM16_INDEX,
295 #endif
296 #ifdef BSP_USING_TIM17
297 TIM17_INDEX,
298 #endif
299 };
300
301 struct stm32_hwtimer
302 {
303 rt_hwtimer_t time_device;
304 TIM_HandleTypeDef tim_handle;
305 IRQn_Type tim_irqn;
306 char *name;
307 };
308
309 static struct stm32_hwtimer stm32_hwtimer_obj[] =
310 {
311 #ifdef BSP_USING_TIM1
312 TIM1_CONFIG,
313 #endif
314
315 #ifdef BSP_USING_TIM2
316 TIM2_CONFIG,
317 #endif
318
319 #ifdef BSP_USING_TIM3
320 TIM3_CONFIG,
321 #endif
322
323 #ifdef BSP_USING_TIM4
324 TIM4_CONFIG,
325 #endif
326
327 #ifdef BSP_USING_TIM5
328 TIM5_CONFIG,
329 #endif
330
331 #ifdef BSP_USING_TIM6
332 TIM6_CONFIG,
333 #endif
334
335 #ifdef BSP_USING_TIM7
336 TIM7_CONFIG,
337 #endif
338
339 #ifdef BSP_USING_TIM8
340 TIM8_CONFIG,
341 #endif
342
343 #ifdef BSP_USING_TIM9
344 TIM9_CONFIG,
345 #endif
346
347 #ifdef BSP_USING_TIM10
348 TIM10_CONFIG,
349 #endif
350
351 #ifdef BSP_USING_TIM11
352 TIM11_CONFIG,
353 #endif
354
355 #ifdef BSP_USING_TIM12
356 TIM12_CONFIG,
357 #endif
358
359 #ifdef BSP_USING_TIM13
360 TIM13_CONFIG,
361 #endif
362
363 #ifdef BSP_USING_TIM14
364 TIM14_CONFIG,
365 #endif
366
367 #ifdef BSP_USING_TIM15
368 TIM15_CONFIG,
369 #endif
370
371 #ifdef BSP_USING_TIM16
372 TIM16_CONFIG,
373 #endif
374
375 #ifdef BSP_USING_TIM17
376 TIM17_CONFIG,
377 #endif
378 };
379
timer_init(struct rt_hwtimer_device * timer,rt_uint32_t state)380 static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
381 {
382 uint32_t prescaler_value = 0;
383 uint32_t pclk1_doubler, pclk2_doubler;
384 TIM_HandleTypeDef *tim = RT_NULL;
385 struct stm32_hwtimer *tim_device = RT_NULL;
386
387 RT_ASSERT(timer != RT_NULL);
388 if (state)
389 {
390 tim = (TIM_HandleTypeDef *)timer->parent.user_data;
391 tim_device = (struct stm32_hwtimer *)timer;
392
393 stm32_tim_pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
394
395 /* time init */
396 /* Some series may only have APBPERIPH_BASE, don't have HAL_RCC_GetPCLK2Freq */
397 #if defined(APBPERIPH_BASE)
398 prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler / 10000) - 1;
399 #elif defined(APB1PERIPH_BASE) || defined(APB2PERIPH_BASE)
400 if ((rt_uint32_t)tim->Instance >= APB2PERIPH_BASE)
401 {
402 prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler / 10000) - 1;
403 }
404 else
405 {
406 prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler / 10000) - 1;
407 }
408 #endif
409 tim->Init.Period = 10000 - 1;
410 tim->Init.Prescaler = prescaler_value;
411 tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
412 if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
413 {
414 tim->Init.CounterMode = TIM_COUNTERMODE_UP;
415 }
416 else
417 {
418 tim->Init.CounterMode = TIM_COUNTERMODE_DOWN;
419 }
420 tim->Init.RepetitionCounter = 0;
421 #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
422 tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
423 #endif
424 if (HAL_TIM_Base_Init(tim) != HAL_OK)
425 {
426 LOG_E("%s init failed", tim_device->name);
427 return;
428 }
429
430 stm32_tim_enable_clock(tim);
431 HAL_NVIC_SetPriority(tim_device->tim_irqn, 3, 0); /* set the TIMx priority */
432 HAL_NVIC_EnableIRQ(tim_device->tim_irqn); /* enable the TIMx global Interrupt */
433 __HAL_TIM_CLEAR_FLAG(tim, TIM_FLAG_UPDATE); /* clear update flag */
434 __HAL_TIM_URS_ENABLE(tim); /* enable update request source */
435 LOG_D("%s init success", tim_device->name);
436 }
437 }
438
timer_start(rt_hwtimer_t * timer,rt_uint32_t t,rt_hwtimer_mode_t opmode)439 static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
440 {
441 rt_err_t result = RT_EOK;
442 TIM_HandleTypeDef *tim = RT_NULL;
443
444 RT_ASSERT(timer != RT_NULL);
445
446 tim = (TIM_HandleTypeDef *)timer->parent.user_data;
447
448 /* set tim cnt */
449 __HAL_TIM_SET_COUNTER(tim, 0);
450 /* set tim arr */
451 __HAL_TIM_SET_AUTORELOAD(tim, t - 1);
452
453 if (opmode == HWTIMER_MODE_ONESHOT)
454 {
455 /* set timer to single mode */
456 tim->Instance->CR1 |= TIM_OPMODE_SINGLE;
457 }
458 else
459 {
460 tim->Instance->CR1 &= (~TIM_OPMODE_SINGLE);
461 }
462
463 /* start timer */
464 if (HAL_TIM_Base_Start_IT(tim) != HAL_OK)
465 {
466 LOG_E("TIM start failed");
467 result = -RT_ERROR;
468 }
469
470 return result;
471 }
472
timer_stop(rt_hwtimer_t * timer)473 static void timer_stop(rt_hwtimer_t *timer)
474 {
475 TIM_HandleTypeDef *tim = RT_NULL;
476
477 RT_ASSERT(timer != RT_NULL);
478
479 tim = (TIM_HandleTypeDef *)timer->parent.user_data;
480
481 /* stop timer */
482 HAL_TIM_Base_Stop_IT(tim);
483
484 /* set tim cnt */
485 __HAL_TIM_SET_COUNTER(tim, 0);
486 }
487
timer_ctrl(rt_hwtimer_t * timer,rt_uint32_t cmd,void * arg)488 static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
489 {
490 TIM_HandleTypeDef *tim = RT_NULL;
491 rt_err_t result = -RT_ERROR;
492 uint32_t pclk1_doubler, pclk2_doubler;
493
494 RT_ASSERT(timer != RT_NULL);
495 RT_ASSERT(arg != RT_NULL);
496
497 tim = (TIM_HandleTypeDef *)timer->parent.user_data;
498
499 switch (cmd)
500 {
501 case HWTIMER_CTRL_FREQ_SET:
502 {
503 rt_uint32_t freq;
504 rt_uint16_t val=0;
505
506 /* set timer frequence */
507 freq = *((rt_uint32_t *)arg);
508
509 stm32_tim_pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
510
511 #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
512 if (0
513 #ifdef TIM1
514 || tim->Instance == TIM1
515 #endif /* TIM1 */
516 #ifdef TIM8
517 || tim->Instance == TIM8
518 #endif /* TIM8 */
519 #ifdef TIM9
520 || tim->Instance == TIM9
521 #endif /* TIM9 */
522 #ifdef TIM10
523 || tim->Instance == TIM10
524 #endif /* TIM10 */
525 #ifdef TIM11
526 || tim->Instance == TIM11
527 #endif /* TIM11 */
528 )
529 #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4)
530 if (0
531 #ifdef TIM15
532 || tim->Instance == TIM15
533 #endif /* TIM15 */
534 #ifdef TIM16
535 || tim->Instance == TIM16
536 #endif /* TIM16 */
537 #ifdef TIM17
538 || tim->Instance == TIM17
539 #endif /* TIM17 */
540 )
541 #elif defined(SOC_SERIES_STM32WB)
542 if (0
543 #ifdef TIM16
544 || tim->Instance == TIM16
545 #endif /* TIM16 */
546 #ifdef TIM17
547 || tim->Instance == TIM17
548 #endif /* TIM17 */
549 )
550 #elif defined(SOC_SERIES_STM32MP1)
551 if(0
552 #ifdef TIM14
553 || tim->Instance == TIM14
554 #endif /* TIM14 */
555 #ifdef TIM16
556 || tim->Instance == TIM16
557 #endif /* TIM16 */
558 #ifdef TIM17
559 || tim->Instance == TIM17
560 #endif /* TIM17 */
561 )
562 #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7)
563 if (0)
564 #else
565 #error "This driver has not supported this series yet!"
566 #endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
567 {
568 #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
569 val = HAL_RCC_GetPCLK2Freq() * pclk2_doubler / freq;
570 #endif /* !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0) */
571 }
572 else
573 {
574 val = HAL_RCC_GetPCLK1Freq() * pclk1_doubler / freq;
575 }
576 __HAL_TIM_SET_PRESCALER(tim, val - 1);
577
578 /* Update frequency value */
579 tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE;
580
581 result = RT_EOK;
582 }
583 break;
584 default:
585 {
586 result = -RT_EINVAL;
587 }
588 break;
589 }
590
591 return result;
592 }
593
timer_counter_get(rt_hwtimer_t * timer)594 static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
595 {
596 TIM_HandleTypeDef *tim = RT_NULL;
597
598 RT_ASSERT(timer != RT_NULL);
599
600 tim = (TIM_HandleTypeDef *)timer->parent.user_data;
601
602 return tim->Instance->CNT;
603 }
604
605 static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
606
607 static const struct rt_hwtimer_ops _ops =
608 {
609 .init = timer_init,
610 .start = timer_start,
611 .stop = timer_stop,
612 .count_get = timer_counter_get,
613 .control = timer_ctrl,
614 };
615
616 #ifdef BSP_USING_TIM2
TIM2_IRQHandler(void)617 void TIM2_IRQHandler(void)
618 {
619 /* enter interrupt */
620 rt_interrupt_enter();
621 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM2_INDEX].tim_handle);
622 /* leave interrupt */
623 rt_interrupt_leave();
624 }
625 #endif
626 #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx)
627 #if defined(BSP_USING_TIM3) || defined(BSP_USING_TIM4)
TIM3_TIM4_IRQHandler(void)628 void TIM3_TIM4_IRQHandler(void)
629 {
630 /* enter interrupt */
631 rt_interrupt_enter();
632 #ifdef BSP_USING_TIM3
633 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle);
634 #endif
635 #ifdef BSP_USING_TIM4
636 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle);
637 #endif
638 /* leave interrupt */
639 rt_interrupt_leave();
640 }
641 #endif
642 #else
643 #ifdef BSP_USING_TIM3
TIM3_IRQHandler(void)644 void TIM3_IRQHandler(void)
645 {
646 /* enter interrupt */
647 rt_interrupt_enter();
648 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle);
649 /* leave interrupt */
650 rt_interrupt_leave();
651 }
652 #endif
653 #ifdef BSP_USING_TIM4
TIM4_IRQHandler(void)654 void TIM4_IRQHandler(void)
655 {
656 /* enter interrupt */
657 rt_interrupt_enter();
658 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle);
659 /* leave interrupt */
660 rt_interrupt_leave();
661 }
662 #endif
663 #endif
664 #ifdef BSP_USING_TIM5
TIM5_IRQHandler(void)665 void TIM5_IRQHandler(void)
666 {
667 /* enter interrupt */
668 rt_interrupt_enter();
669 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM5_INDEX].tim_handle);
670 /* leave interrupt */
671 rt_interrupt_leave();
672 }
673 #endif
674 #ifdef BSP_USING_TIM6
TIM6_DAC_IRQHandler(void)675 void TIM6_DAC_IRQHandler(void)
676 {
677 /* enter interrupt */
678 rt_interrupt_enter();
679 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM6_INDEX].tim_handle);
680 /* leave interrupt */
681 rt_interrupt_leave();
682 }
683 #endif
684 #ifdef BSP_USING_TIM7
TIM7_IRQHandler(void)685 void TIM7_IRQHandler(void)
686 {
687 /* enter interrupt */
688 rt_interrupt_enter();
689 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM7_INDEX].tim_handle);
690 /* leave interrupt */
691 rt_interrupt_leave();
692 }
693 #endif
694 #ifdef BSP_USING_TIM8
TIM8_UP_IRQHandler(void)695 void TIM8_UP_IRQHandler(void)
696 {
697 /* enter interrupt */
698 rt_interrupt_enter();
699 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM8_INDEX].tim_handle);
700 /* leave interrupt */
701 rt_interrupt_leave();
702 }
703 #endif
704 #ifdef BSP_USING_TIM11
TIM1_TRG_COM_TIM11_IRQHandler(void)705 void TIM1_TRG_COM_TIM11_IRQHandler(void)
706 {
707 /* enter interrupt */
708 rt_interrupt_enter();
709 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM11_INDEX].tim_handle);
710 /* leave interrupt */
711 rt_interrupt_leave();
712 }
713 #endif
714 #ifdef BSP_USING_TIM13
TIM8_UP_TIM13_IRQHandler(void)715 void TIM8_UP_TIM13_IRQHandler(void)
716 {
717 /* enter interrupt */
718 rt_interrupt_enter();
719 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM13_INDEX].tim_handle);
720 /* leave interrupt */
721 rt_interrupt_leave();
722 }
723 #endif
724 #ifdef BSP_USING_TIM14
725 #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
TIM8_TRG_COM_TIM14_IRQHandler(void)726 void TIM8_TRG_COM_TIM14_IRQHandler(void)
727 #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
728 void TIM14_IRQHandler(void)
729 #endif
730 {
731 /* enter interrupt */
732 rt_interrupt_enter();
733 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM14_INDEX].tim_handle);
734 /* leave interrupt */
735 rt_interrupt_leave();
736 }
737 #endif
738 #ifdef BSP_USING_TIM15
TIM1_BRK_TIM15_IRQHandler(void)739 void TIM1_BRK_TIM15_IRQHandler(void)
740 {
741 /* enter interrupt */
742 rt_interrupt_enter();
743 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM15_INDEX].tim_handle);
744 /* leave interrupt */
745 rt_interrupt_leave();
746 }
747 #endif
748 #ifdef BSP_USING_TIM16
749 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32G4)
TIM1_UP_TIM16_IRQHandler(void)750 void TIM1_UP_TIM16_IRQHandler(void)
751 #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
752 void TIM16_IRQHandler(void)
753 #endif
754 {
755 /* enter interrupt */
756 rt_interrupt_enter();
757 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM16_INDEX].tim_handle);
758 /* leave interrupt */
759 rt_interrupt_leave();
760 }
761 #endif
762 #ifdef BSP_USING_TIM17
763 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32G4)
TIM1_TRG_COM_TIM17_IRQHandler(void)764 void TIM1_TRG_COM_TIM17_IRQHandler(void)
765 #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
766 void TIM17_IRQHandler(void)
767 #endif
768 {
769 /* enter interrupt */
770 rt_interrupt_enter();
771 HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM17_INDEX].tim_handle);
772 /* leave interrupt */
773 rt_interrupt_leave();
774 }
775 #endif
776
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)777 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
778 {
779 #ifdef BSP_USING_TIM2
780 if (htim->Instance == TIM2)
781 {
782 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM2_INDEX].time_device);
783 }
784 #endif
785 #ifdef BSP_USING_TIM3
786 if (htim->Instance == TIM3)
787 {
788 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM3_INDEX].time_device);
789 }
790 #endif
791 #ifdef BSP_USING_TIM4
792 if (htim->Instance == TIM4)
793 {
794 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM4_INDEX].time_device);
795 }
796 #endif
797 #ifdef BSP_USING_TIM5
798 if (htim->Instance == TIM5)
799 {
800 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM5_INDEX].time_device);
801 }
802 #endif
803 #ifdef BSP_USING_TIM6
804 if (htim->Instance == TIM6)
805 {
806 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM6_INDEX].time_device);
807 }
808 #endif
809 #ifdef BSP_USING_TIM7
810 if (htim->Instance == TIM7)
811 {
812 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM7_INDEX].time_device);
813 }
814 #endif
815 #ifdef BSP_USING_TIM8
816 if (htim->Instance == TIM8)
817 {
818 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM8_INDEX].time_device);
819 }
820 #endif
821 #ifdef BSP_USING_TIM11
822 if (htim->Instance == TIM11)
823 {
824 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM11_INDEX].time_device);
825 }
826 #endif
827 #ifdef BSP_USING_TIM13
828 if (htim->Instance == TIM13)
829 {
830 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM13_INDEX].time_device);
831 }
832 #endif
833 #ifdef BSP_USING_TIM14
834 if (htim->Instance == TIM14)
835 {
836 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM14_INDEX].time_device);
837 }
838 #endif
839 #ifdef BSP_USING_TIM15
840 if (htim->Instance == TIM15)
841 {
842 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM15_INDEX].time_device);
843 }
844 #endif
845 #ifdef BSP_USING_TIM16
846 if (htim->Instance == TIM16)
847 {
848 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM16_INDEX].time_device);
849 }
850 #endif
851 #ifdef BSP_USING_TIM17
852 if (htim->Instance == TIM17)
853 {
854 rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM17_INDEX].time_device);
855 }
856 #endif
857 }
858
stm32_hwtimer_init(void)859 static int stm32_hwtimer_init(void)
860 {
861 rt_uint32_t i = 0;
862 int result = RT_EOK;
863
864 for (i = 0; i < sizeof(stm32_hwtimer_obj) / sizeof(stm32_hwtimer_obj[0]); i++)
865 {
866 stm32_hwtimer_obj[i].time_device.info = &_info;
867 stm32_hwtimer_obj[i].time_device.ops = &_ops;
868 if (rt_device_hwtimer_register(&stm32_hwtimer_obj[i].time_device,
869 stm32_hwtimer_obj[i].name, &stm32_hwtimer_obj[i].tim_handle) == RT_EOK)
870 {
871 LOG_D("%s register success", stm32_hwtimer_obj[i].name);
872 }
873 else
874 {
875 LOG_E("%s register failed", stm32_hwtimer_obj[i].name);
876 result = -RT_ERROR;
877 }
878 }
879
880 return result;
881 }
882 INIT_BOARD_EXPORT(stm32_hwtimer_init);
883
884 #endif /* BSP_USING_TIM */
885