1 /*
2 * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 #ifndef _DW_GMAC_182x_H_
17 #define _DW_GMAC_182x_H_
18
19 #include "cvi_eth_phy.h"
20
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24
25 #ifndef __aligned
26 #define __aligned(x) __attribute__((aligned(x)))
27 #endif
28
29 typedef void *eth_mac_handle_t;
30
31 #define CSI_ETH_MAC_CONFIGURE (0x01) ///< Configure MAC; arg = configuration
32 #define CSI_ETH_MAC_CONTROL_TX (0x02) ///< Transmitter; arg: 0=disabled (default), 1=enabled
33 #define CSI_ETH_MAC_CONTROL_RX (0x03) ///< Receiver; arg: 0=disabled (default), 1=enabled
34 #define CSI_ETH_MAC_FLUSH (0x04) ///< Flush buffer; arg = CSI_ETH_MAC_FLUSH_...
35 #define CSI_ETH_MAC_SLEEP (0x05) ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit
36 #define CSI_ETH_MAC_VLAN_FILTER (0x06) ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional CSI_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default)
37 #define DRV_ETH_MAC_ADJUST_LINK (0x07) ///< Adjust MAC link state according to phy state; arg: phy handle
38 #define DRV_ETH_MAC_CONTROL_IRQ (0x08) ///< Interrupt request; arg: 0=disable, 1=enable
39
40 #define DW_GMAC_DMA_ALIGN 128
41
42 #ifndef _DW_ETH_H
43 #define _DW_ETH_H
44
45 #define CVI_CONFIG_SYS_HZ 1000
46 #define CVI_CONFIG_TX_DESCR_NUM 16
47 #define CVI_CONFIG_RX_DESCR_NUM 16
48 #define CVI_CONFIG_ETH_BUFSIZE 2048
49 #define CVI_TX_TOTAL_BUFSIZE (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_TX_DESCR_NUM)
50 #define CVI_RX_TOTAL_BUFSIZE (CVI_CONFIG_ETH_BUFSIZE * CVI_CONFIG_RX_DESCR_NUM)
51
52 #define CVI_CONFIG_MACRESET_TIMEOUT (3 * CVI_CONFIG_SYS_HZ)
53 #define CVI_CONFIG_MDIO_TIMEOUT (3 * CVI_CONFIG_SYS_HZ)
54
55 struct dw_gmac_mac_regs {
56 volatile uint32_t conf; /* 0x00 */
57 volatile uint32_t framefilt; /* 0x04 */
58 volatile uint32_t hashtablehigh; /* 0x08 */
59 volatile uint32_t hashtablelow; /* 0x0c */
60 volatile uint32_t miiaddr; /* 0x10 */
61 volatile uint32_t miidata; /* 0x14 */
62 volatile uint32_t flowcontrol; /* 0x18 */
63 volatile uint32_t vlantag; /* 0x1c */
64 volatile uint32_t version; /* 0x20 */
65 volatile uint32_t reserved_1[5];
66 volatile uint32_t intreg; /* 0x38 */
67 volatile uint32_t intmask; /* 0x3c */
68 volatile uint32_t macaddr0hi; /* 0x40 */
69 volatile uint32_t macaddr0lo; /* 0x44 */
70 };
71
72 /* MAC configuration register definitions */
73 #define CVI_FRAMEBURSTENABLE (1 << 21)
74 #define CVI_MII_PORTSELECT (1 << 15)
75 #define CVI_FES_100 (1 << 14)
76 #define CVI_DISABLERXOWN (1 << 13)
77 #define CVI_FULLDPLXMODE (1 << 11)
78 #define CVI_RXENABLE (1 << 2)
79 #define CVI_TXENABLE (1 << 3)
80
81 /* MII address register definitions */
82 #define CVI_MII_BUSY (1 << 0)
83 #define CVI_MII_WRITE (1 << 1)
84 #define CVI_MII_CLKRANGE_60_100M (0)
85 #define CVI_MII_CLKRANGE_100_150M (0x4)
86 #define CVI_MII_CLKRANGE_20_35M (0x8)
87 #define CVI_MII_CLKRANGE_35_60M (0xC)
88 #define CVI_MII_CLKRANGE_150_250M (0x10)
89 #define CVI_MII_CLKRANGE_250_300M (0x14)
90
91 #define CVI_MIIADDRSHIFT (11)
92 #define CVI_MIIREGSHIFT (6)
93 #define CVI_MII_REGMSK (0x1F << 6)
94 #define CVI_MII_ADDRMSK (0x1F << 11)
95
96 typedef uint32_t reg_type;
97 struct dw_gmac_dma_regs
98 {
99 volatile reg_type busmode; /* 0x00 */
100 volatile reg_type txpolldemand; /* 0x04 */
101 volatile reg_type rxpolldemand; /* 0x08 */
102 volatile reg_type rxdesclistaddr; /* 0x0c */
103 volatile reg_type txdesclistaddr; /* 0x10 */
104 volatile reg_type status; /* 0x14 */
105 volatile reg_type opmode; /* 0x18 */
106 volatile reg_type intenable; /* 0x1c */
107 volatile reg_type discardedcount; /* 0x20 */
108 volatile reg_type wdtforri; /* 0x24 */
109 //volatile reg_type reserved1[2];
110 volatile reg_type axibus; /* 0x28 */
111 volatile reg_type reserved2[7];
112 volatile reg_type currhosttxdesc; /* 0x48 */
113 volatile reg_type currhostrxdesc; /* 0x4c */
114 volatile reg_type currhosttxbuffaddr; /* 0x50 */
115 volatile reg_type currhostrxbuffaddr; /* 0x54 */
116 };
117
118 /* Operation mode definitions */
119 #define CVI_RXSTART (1 << 1)
120 #define CVI_TXSECONDFRAME (1 << 2)
121 #define CVI_TXSTART (1 << 13)
122 #define CVI_FLUSHTXFIFO (1 << 20)
123 #define CVI_STOREFORWARD (1 << 21)
124 #define CVI_DW_DMA_BASE_OFFSET (0x1000)
125
126 /* Default DMA Burst length */
127 #ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
128 #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
129 #endif
130 /* Status definitions */
131 #define CVI_DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
132 #define CVI_DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
133 #define CVI_DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
134
135 /* Bus mode register definitions */
136
137 #define CVI_DMAMAC_SRST (1 << 0)
138 #define CVI_RXHIGHPRIO (1 << 1)
139 #define CVI_FIXEDBURST (1 << 16)
140 #define CVI_PRIORXTX_11 (0 << 14)
141 #define CVI_PRIORXTX_21 (1 << 14)
142 #define CVI_PRIORXTX_31 (2 << 14)
143 #define CVI_PRIORXTX_41 (3 << 14)
144 #define CVI_DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
145
146 /* Poll demand definitions */
147 #define CVI_POLL_DATA (0xFFFFFFFF)
148
149
150 /* Descriptior related definitions */
151 #define CVI_MAC_MAX_FRAME_SZ (1600)
152
153 struct dmamacdescr
154 {
155 unsigned int txrx_status;
156 unsigned int dmamac_cntl;
157 unsigned int dmamac_addr;
158 unsigned int dmamac_next;
159 } __attribute__((aligned(DW_GMAC_DMA_ALIGN)));
160
161 /*
162 * txrx_status definitions
163 */
164
165 /* tx status bits definitions */
166 #if defined(CONFIG_DW_ALTDESCRIPTOR)
167
168 #define CVI_DESC_TXSTS_OWNBYDMA (1 << 31)
169 #define CVI_DESC_TXSTS_TXINT (1 << 30)
170 #define CVI_DESC_TXSTS_TXLAST (1 << 29)
171 #define CVI_DESC_TXSTS_TXFIRST (1 << 28)
172 #define CVI_DESC_TXSTS_TXCRCDIS (1 << 27)
173
174 #define CVI_DESC_TXSTS_TXPADDIS (1 << 26)
175 #define CVI_DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
176 #define CVI_DESC_TXSTS_TXRINGEND (1 << 21)
177 #define CVI_DESC_TXSTS_TXCHAIN (1 << 20)
178 #define CVI_DESC_TXSTS_MSK (0x1FFFF << 0)
179
180 #else
181
182 #define CVI_DESC_TXSTS_OWNBYDMA (1 << 31)
183 #define CVI_DESC_TXSTS_MSK (0x1FFFF << 0)
184
185 #endif
186
187 /* rx status bits definitions */
188 #define CVI_DESC_RXSTS_OWNBYDMA (1 << 31)
189 #define CVI_DESC_RXSTS_DAFILTERFAIL (1 << 30)
190 #define CVI_DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
191 #define CVI_DESC_RXSTS_FRMLENSHFT (16)
192
193 #define CVI_DESC_RXSTS_ERROR (1 << 15)
194 #define CVI_DESC_RXSTS_RXTRUNCATED (1 << 14)
195 #define CVI_DESC_RXSTS_SAFILTERFAIL (1 << 13)
196 #define CVI_DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
197 #define CVI_DESC_RXSTS_RXDAMAGED (1 << 11)
198 #define CVI_DESC_RXSTS_RXVLANTAG (1 << 10)
199 #define CVI_DESC_RXSTS_RXFIRST (1 << 9)
200 #define CVI_DESC_RXSTS_RXLAST (1 << 8)
201 #define CVI_DESC_RXSTS_RXIPC_GIANT (1 << 7)
202 #define CVI_DESC_RXSTS_RXCOLLISION (1 << 6)
203 #define CVI_DESC_RXSTS_RXFRAMEETHER (1 << 5)
204 #define CVI_DESC_RXSTS_RXWATCHDOG (1 << 4)
205 #define CVI_DESC_RXSTS_RXMIIERROR (1 << 3)
206 #define CVI_DESC_RXSTS_RXDRIBBLING (1 << 2)
207 #define CVI_DESC_RXSTS_RXCRC (1 << 1)
208
209 /*
210 * dmamac_cntl definitions
211 */
212
213 /* tx control bits definitions */
214 #if defined(CONFIG_DW_ALTDESCRIPTOR)
215
216 #define CVI_DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
217 #define CVI_DESC_TXCTRL_SIZE1SHFT (0)
218 #define CVI_DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
219 #define CVI_DESC_TXCTRL_SIZE2SHFT (16)
220
221 #else
222
223 #define CVI_DESC_TXCTRL_TXINT (1 << 31)
224 #define CVI_DESC_TXCTRL_TXLAST (1 << 30)
225 #define CVI_DESC_TXCTRL_TXFIRST (1 << 29)
226 #define CVI_DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
227 #define CVI_DESC_TXCTRL_TXCRCDIS (1 << 26)
228 #define CVI_DESC_TXCTRL_TXRINGEND (1 << 25)
229 #define CVI_DESC_TXCTRL_TXCHAIN (1 << 24)
230
231 #define CVI_DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
232 #define CVI_DESC_TXCTRL_SIZE1SHFT (0)
233 #define CVI_DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
234 #define CVI_DESC_TXCTRL_SIZE2SHFT (11)
235
236 #endif
237
238 /* rx control bits definitions */
239 #if defined(CONFIG_DW_ALTDESCRIPTOR)
240
241 #define CVI_DESC_RXCTRL_RXINTDIS (1 << 31)
242 #define CVI_DESC_RXCTRL_RXRINGEND (1 << 15)
243 #define CVI_DESC_RXCTRL_RXCHAIN (1 << 14)
244
245 #define CVI_DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
246 #define CVI_DESC_RXCTRL_SIZE1SHFT (0)
247 #define CVI_DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
248 #define CVI_DESC_RXCTRL_SIZE2SHFT (16)
249
250 #else
251
252 #define CVI_DESC_RXCTRL_RXINTDIS (1 << 31)
253 #define CVI_DESC_RXCTRL_RXRINGEND (1 << 25)
254 #define CVI_DESC_RXCTRL_RXCHAIN (1 << 24)
255
256 #define CVI_DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
257 #define CVI_DESC_RXCTRL_SIZE1SHFT (0)
258 #define CVI_DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
259 #define CVI_DESC_RXCTRL_SIZE2SHFT (11)
260
261 #endif
262
263 struct dw_gmac_priv
264 {
265 struct dmamacdescr tx_mac_descrtable[CVI_CONFIG_TX_DESCR_NUM] __aligned(DW_GMAC_DMA_ALIGN);
266 struct dmamacdescr rx_mac_descrtable[CVI_CONFIG_RX_DESCR_NUM] __aligned(DW_GMAC_DMA_ALIGN);
267 char txbuffs[CVI_TX_TOTAL_BUFSIZE] __aligned(DW_GMAC_DMA_ALIGN);
268 char rxbuffs[CVI_RX_TOTAL_BUFSIZE] __aligned(DW_GMAC_DMA_ALIGN);
269
270 uint32_t interface;
271 uint32_t max_speed;
272 uint32_t tx_currdescnum;
273 uint32_t rx_currdescnum;
274
275 struct dw_gmac_mac_regs *mac_regs_p;
276 struct dw_gmac_dma_regs *dma_regs_p;
277 };
278
279 #ifdef CONFIG_DM_ETH
280 int designware_eth_ofdata_to_platdata(struct udevice *dev);
281 int designware_eth_probe(struct udevice *dev);
282 extern const struct eth_ops designware_eth_ops;
283
284 struct dw_eth_pdata
285 {
286 struct eth_pdata eth_pdata;
287 u32 reset_delays[3];
288 };
289
290 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
291 int designware_eth_enable(struct dw_eth_dev *priv);
292 int designware_eth_send(struct udevice *dev, void *packet, int length);
293 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp);
294 int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
295 int length);
296 void designware_eth_stop(struct udevice *dev);
297 int designware_eth_write_hwaddr(struct udevice *dev);
298 #endif
299
300 #endif
301
302 typedef struct
303 {
304 eth_phy_dev_t *phy_dev;
305 rt_ubase_t base;
306 uint8_t irq;
307 uint8_t mac_addr[6];
308 struct dw_gmac_priv *priv_unalign;
309 struct dw_gmac_priv *priv;
310 } gmac_dev_t;
311
312 /**
313 \brief Ethernet MAC Address
314 */
315 typedef struct eth_mac_addr
316 {
317 uint8_t b[6]; ///< MAC Address (6 bytes), MSB first
318 } eth_mac_addr_t;
319
memalign(uint32_t align,uint32_t size,void ** mem_unalign)320 static inline void *memalign(uint32_t align, uint32_t size, void **mem_unalign)
321 {
322 void *mem;
323 uint32_t offset;
324
325 *mem_unalign = (void *)rt_malloc(size + align);
326
327 if (!*mem_unalign) {
328 return NULL;
329 }
330
331 offset = *(uint32_t *)mem_unalign % align;
332
333 if (offset == 0) {
334 mem = (struct eqos_priv *)*mem_unalign;
335 } else {
336 mem = (struct eqos_priv *)(*mem_unalign + (align - offset));
337 }
338 return mem;
339 }
340 /**
341 \brief Write Ethernet PHY Register through Management Interface.
342 \param[in] handle ethernet handle
343 \param[in] phy_addr 5-bit device address
344 \param[in] reg_addr 5-bit register address
345 \param[in] data 16-bit data to write
346 \return error code
347 */
348 int32_t dw_eth_mac_phy_write(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t data);
349
350 /**
351 \brief Control Ethernet Interface.
352 \param[in] handle ethernet handle
353 \param[in] control Operation
354 \param[in] arg Argument of operation (optional)
355 \return error code
356 */
357 int32_t cvi_eth_mac_control(eth_mac_handle_t handle, uint32_t control, uint32_t arg);
358 /**
359 \brief Get Ethernet MAC Address.
360 \param[in] handle ethernet handle
361 \param[in] mac Pointer to address
362 \return error code
363 */
364 int32_t cvi_eth_mac_get_macaddr(eth_mac_handle_t handle, eth_mac_addr_t *mac);
365
366 /**
367 \brief Set Ethernet MAC Address.
368 \param[in] handle ethernet handle
369 \param[in] mac Pointer to address
370 \return error code
371 */
372 int32_t cvi_eth_mac_set_macaddr(eth_mac_handle_t handle, const eth_mac_addr_t *mac);
373
374 /**
375 \brief Connect phy device to mac device.
376 \param[in] handle_mac mac handle
377 \param[in] handle_phy phy handle
378 */
379 void dw_eth_mac_connect_phy(eth_mac_handle_t handle_mac, eth_phy_handle_t handle_phy);
380
381 /**
382 \brief Read Ethernet PHY Register through Management Interface.
383 \param[in] handle ethernet handle
384 \param[in] phy_addr 5-bit device address
385 \param[in] reg_addr 5-bit register address
386 \param[out] data Pointer where the result is written to
387 \return error code
388 */
389 int32_t dw_eth_mac_phy_read(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);
390
391 /**
392 \brief Send Ethernet frame.
393 \param[in] handle ethernet handle
394 \param[in] frame Pointer to frame buffer with data to send
395 \param[in] len Frame buffer length in bytes
396 \return error code
397 */
398 int32_t cvi_eth_mac_send_frame(eth_mac_handle_t handle, const uint8_t *frame, uint32_t len);
399
400 /**
401 \brief Read data of received Ethernet frame.
402 \param[in] handle ethernet handle
403 \param[in] frame Pointer to frame buffer for data to read into
404 \param[in] len Frame buffer length in bytes
405 \return number of data bytes read or execution status
406 - value >= 0: number of data bytes read
407 - value < 0: error occurred, value is execution status as defined with execution_status
408 */
409 int32_t cvi_eth_mac_read_frame(eth_mac_handle_t handle, uint8_t *frame, uint32_t len);
410
411 /**
412 \brief This function is used to initialize Ethernet device and register an event callback.
413 \param[in] idx device id
414 \param[in] cb callback to handle ethernet event
415 \return return ethernet handle if success
416 */
417 eth_mac_handle_t cvi_eth_mac_init(rt_ubase_t base);
418
419 #ifdef __cplusplus
420 }
421 #endif
422
423 #endif /* _DW_GMAC_182x_H_ */
424