1 /*
2 * Copyright (C) 2017-2024 Alibaba Group Holding Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /******************************************************************************
20 * @file dw_uart_ll.h
21 * @brief header file for uart ll driver
22 * @version V1.0
23 * @date 18. December 2024
24 ******************************************************************************/
25
26 #ifndef _DW_UART_LL_H_
27 #define _DW_UART_LL_H_
28
29 #include <stdio.h>
30 #include <csi_config.h>
31 #include <soc.h>
32 #include <csi_core.h>
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 #if CONFIG_XIP
39 #define ATTRIBUTE_DATA __attribute__((section(".ram.code")))
40 #else
41 #define ATTRIBUTE_DATA
42 #endif
43
44 /*! IER, offset: 0x4 */
45 #define DW_UART_IER_ERBFI_Pos (0U)
46 #define DW_UART_IER_ERBFI_Msk (0x1U << DW_UART_IER_ERBFI_Pos)
47 #define DW_UART_IER_ERBFI_EN DW_UART_IER_ERBFI_Msk
48
49 #define DW_UART_IER_ETBEI_Pos (1U)
50 #define DW_UART_IER_ETBEI_Msk (0x1U << DW_UART_IER_ETBEI_Pos)
51 #define DW_UART_IER_ETBEI_EN DW_UART_IER_ETBEI_Msk
52
53 #define DW_UART_IER_ELSI_Pos (2U)
54 #define DW_UART_IER_ELSI_Msk (0x1U << DW_UART_IER_ELSI_Pos)
55 #define DW_UART_IER_ELSI_EN DW_UART_IER_ELSI_Msk
56
57 #define DW_UART_IER_EDSSI_Pos (3U)
58 #define DW_UART_IER_EDSSI_Msk (0x1U << DW_UART_IER_EDSSI_Pos)
59 #define DW_UART_IER_EDSSI_EN DW_UART_IER_EDSSI_Msk
60
61 /*! IIR, offset: 0x8 */
62 #define DW_UART_IIR_IID_Pos (0U)
63 #define DW_UART_IIR_IID_Msk (0xFU << DW_UART_IIR_IID_Pos)
64 #define DW_UART_IIR_IID_MODEM_STATUS (0x0U)
65 #define DW_UART_IIR_IID_NO_INTERRUPT (0x1U)
66 #define DW_UART_IIR_IID_THR_EMPTY (0x2U)
67 #define DW_UART_IIR_IID_RECV_DATA_AVAIL (0x4U)
68 #define DW_UART_IIR_IID_RECV_LINE_STATUS (0x6U)
69 #define DW_UART_IIR_IID_BUSY_DETECT (0x7U)
70 #define DW_UART_IIR_IID_CHARACTER_TIMEOUT (0xCU)
71
72 #define DW_UART_IIR_FIFOSE_Pos (6U)
73 #define DW_UART_IIR_FIFOSE_Msk (0x3U << DW_UART_IIR_FIFOSE_Pos)
74 #define DW_UART_IIR_FIFOSE_EN DW_UART_IIR_FIFOSE_Msk
75
76 /*! FCR, offset: 0x8 */
77 #define DW_UART_FCR_FIFOE_Pos (0U)
78 #define DW_UART_FCR_FIFOE_Msk (0x1U << DW_UART_FCR_FIFOE_Pos)
79 #define DW_UART_FCR_FIFOE_EN DW_UART_FCR_FIFOE_Msk
80
81 #define DW_UART_FCR_RFIFOR_Pos (1U)
82 #define DW_UART_FCR_RFIFOR_Msk (0x1U << DW_UART_FCR_RFIFOR_Pos)
83 #define DW_UART_FCR_RFIFOR_RESET DW_UART_FCR_RFIFOR_Msk
84
85 #define DW_UART_FCR_XFIFOR_Pos (2U)
86 #define DW_UART_FCR_XFIFOR_Msk (0x1U << DW_UART_FCR_XFIFOR_Pos)
87 #define DW_UART_FCR_XFIFOR_RESET DW_UART_FCR_XFIFOR_Msk
88
89 #define DW_UART_FCR_TET_Pos (4U)
90 #define DW_UART_FCR_TET_Msk (0x3U << DW_UART_FCR_TET_Pos)
91 #define DW_UART_FCR_TET_FIFO_EMTPY (0x0U)
92 #define DW_UART_FCR_TET_FIFO_2_CHAR (0x1U << DW_UART_FCR_TET_Pos)
93 #define DW_UART_FCR_TET_FIFO_1_4_FULL (0x2U << DW_UART_FCR_TET_Pos)
94 #define DW_UART_FCR_TET_FIFO_1_2_FULL (0x3U << DW_UART_FCR_TET_Pos)
95
96 #define DW_UART_FCR_RT_Pos (6U)
97 #define DW_UART_FCR_RT_Msk (0x3U << DW_UART_FCR_RT_Pos)
98 #define DW_UART_FCR_RT_FIFO_1_CHAR (0x0U)
99 #define DW_UART_FCR_RT_FIFO_1_4_FULL (0x1U << DW_UART_FCR_RT_Pos)
100 #define DW_UART_FCR_RT_FIFO_1_2_FULL (0x2U << DW_UART_FCR_RT_Pos)
101 #define DW_UART_FCR_RT_FIFO_2_LESS_FULL (0x3U << DW_UART_FCR_RT_Pos)
102
103 /*! LCR, offset: 0xC */
104 #define DW_UART_LCR_DLS_Pos (0U)
105 #define DW_UART_LCR_DLS_Msk (0x3U << DW_UART_LCR_DLS_Pos)
106 #define DW_UART_LCR_DLS_5_BITS (0x0U)
107 #define DW_UART_LCR_DLS_6_BITS (0x1U << DW_UART_LCR_DLS_Pos)
108 #define DW_UART_LCR_DLS_7_BITS (0x2U << DW_UART_LCR_DLS_Pos)
109 #define DW_UART_LCR_DLS_8_BITS (0x3U << DW_UART_LCR_DLS_Pos)
110
111 #define DW_UART_LCR_STOP_Pos (2U)
112 #define DW_UART_LCR_STOP_Msk (0x1U << DW_UART_LCR_STOP_Pos)
113 #define DW_UART_LCR_STOP_1_BIT (0x0U)
114 #define DW_UART_LCR_STOP_2_BIT (0x1U << DW_UART_LCR_STOP_Pos)
115
116 #define DW_UART_LCR_PEN_Pos (3U)
117 #define DW_UART_LCR_PEN_Msk (0x1U << DW_UART_LCR_PEN_Pos)
118 #define DW_UART_LCR_PEN_EN DW_UART_LCR_PEN_Msk
119
120 #define DW_UART_LCR_EPS_Pos (4U)
121 #define DW_UART_LCR_EPS_Msk (0x1U << DW_UART_LCR_EPS_Pos)
122 #define DW_UART_LCR_EPS_EN DW_UART_LCR_EPS_Msk
123
124 #define DW_UART_LCR_BC_Pos (6U)
125 #define DW_UART_LCR_BC_Msk (0x1U << DW_UART_LCR_BC_Pos)
126 #define DW_UART_LCR_BC_EN DW_UART_LCR_BC_Msk
127
128 #define DW_UART_LCR_DLAB_Pos (7U)
129 #define DW_UART_LCR_DLAB_Msk (0x1U << DW_UART_LCR_DLAB_Pos)
130 #define DW_UART_LCR_DLAB_EN DW_UART_LCR_DLAB_Msk
131
132 /*! MCR, offset: 0x10 */
133 #define DW_UART_MCR_RTS_Pos (1U)
134 #define DW_UART_MCR_RTS_Msk (0x1U << DW_UART_MCR_RTS_Pos)
135 #define DW_UART_MCR_RTS_EN DW_UART_MCR_RTS_Msk
136
137 #define DW_UART_MCR_LB_Pos (4U)
138 #define DW_UART_MCR_LB_Msk (0x1U << DW_UART_MCR_LB_Pos)
139 #define DW_UART_MCR_LB_EN DW_UART_MCR_LB_Msk
140
141 #define DW_UART_MCR_AFCE_Pos (5U)
142 #define DW_UART_MCR_AFCE_Msk (0x1U << DW_UART_MCR_AFCE_Pos)
143 #define DW_UART_MCR_AFCE_EN DW_UART_MCR_AFCE_Msk
144
145 /*! LSR, offset: 0x14 */
146 #define DW_UART_LSR_DR_Pos (0U)
147 #define DW_UART_LSR_DR_Msk (0x1U << DW_UART_LSR_DR_Pos)
148 #define DW_UART_LSR_DR_READY DW_UART_LSR_DR_Msk
149
150 #define DW_UART_LSR_OE_Pos (1U)
151 #define DW_UART_LSR_OE_Msk (0x1U << DW_UART_LSR_OE_Pos)
152 #define DW_UART_LSR_OE_ERROR DW_UART_LSR_OE_Msk
153
154 #define DW_UART_LSR_PE_Pos (2U)
155 #define DW_UART_LSR_PE_Msk (0x1U << DW_UART_LSR_PE_Pos)
156 #define DW_UART_LSR_PE_ERROR DW_UART_LSR_PE_Msk
157
158 #define DW_UART_LSR_FE_Pos (3U)
159 #define DW_UART_LSR_FE_Msk (0x1U << DW_UART_LSR_FE_Pos)
160 #define DW_UART_LSR_FE_ERROR DW_UART_LSR_FE_Msk
161
162 #define DW_UART_LSR_BI_Pos (4U)
163 #define DW_UART_LSR_BI_Msk (0x1U << DW_UART_LSR_BI_Pos)
164 #define DW_UART_LSR_BI_SET DW_UART_LSR_BI_Msk
165
166 #define DW_UART_LSR_THRE_Pos (5U)
167 #define DW_UART_LSR_THRE_Msk (0x1U << DW_UART_LSR_THRE_Pos)
168 #define DW_UART_LSR_THRE_SET DW_UART_LSR_THRE_Msk
169
170 #define DW_UART_LSR_TEMT_Pos (6U)
171 #define DW_UART_LSR_TEMT_Msk (0x1U << DW_UART_LSR_TEMT_Pos)
172 #define DW_UART_LSR_TEMT_SET DW_UART_LSR_TEMT_Msk
173
174 #define DW_UART_LSR_RFE_Pos (7U)
175 #define DW_UART_LSR_RFE_Msk (0x1U << DW_UART_LSR_RFE_Pos)
176 #define DW_UART_LSR_RFE_ERROR DW_UART_LSR_RFE_Msk
177
178 /*! MSR, offset: 0x18 */
179 #define DW_UART_MSR_DCTS_Pos (0U)
180 #define DW_UART_MSR_DCTS_Msk (0x1U << DW_UART_MSR_DCTS_Pos)
181 #define DW_UART_MSR_DCTS_CHANGE DW_UART_MSR_DCTS_Msk
182
183 #define DW_UART_MSR_DDSR_Pos (1U)
184 #define DW_UART_MSR_DDSR_Msk (0x1U << DW_UART_MSR_DDSR_Pos)
185 #define DW_UART_MSR_DDSR_CHANGE DW_UART_MSR_DDSR_Msk
186
187 #define DW_UART_MSR_TERI_Pos (2U)
188 #define DW_UART_MSR_TERI_Msk (0x1U << DW_UART_MSR_TERI_Pos)
189 #define DW_UART_MSR_TERI_CHANGE DW_UART_MSR_TERI_Msk
190
191 #define DW_UART_MSR_DDCD_Pos (3U)
192 #define DW_UART_MSR_DDCD_Msk (0x1U << DW_UART_MSR_DDCD_Pos)
193 #define DW_UART_MSR_DDCD_CHANGE DW_UART_MSR_DDCD_Msk
194
195 #define DW_UART_MSR_CTS_Pos (4U)
196 #define DW_UART_MSR_CTS_Msk (0x1U << DW_UART_MSR_CTS_Pos)
197 #define DW_UART_MSR_CTS_ASSERTED DW_UART_MSR_CTS_Msk
198
199 #define DW_UART_MSR_DSR_Pos (5U)
200 #define DW_UART_MSR_DSR_Msk (0x1U << DW_UART_MSR_DSR_Pos)
201 #define DW_UART_MSR_DSR_ASSERTED DW_UART_MSR_DSR_Msk
202
203 #define DW_UART_MSR_RI_Pos (6U)
204 #define DW_UART_MSR_RI_Msk (0x1U << DW_UART_MSR_RI_Pos)
205 #define DW_UART_MSR_RI_ASSERTED DW_UART_MSR_RI_Msk
206
207 #define DW_UART_MSR_DCD_Pos (7U)
208 #define DW_UART_MSR_DCD_Msk (0x1U << DW_UART_MSR_DCD_Pos)
209 #define DW_UART_MSR_DCD_ASSERTED DW_UART_MSR_DCD_Msk
210
211 /*! SCR, offset: 0x1C */
212 #define DW_UART_SCR_SCRATCHPAD_Pos (0U)
213 #define DW_UART_SCR_SCRATCHPAD_Msk (0xFFU << DW_UART_SCR_SCRATCHPAD_Pos)
214
215 /*! USR, offset: 0x7C */
216 #define DW_UART_USR_BUSY_Pos (0U)
217 #define DW_UART_USR_BUSY_Msk (0x1U << DW_UART_USR_BUSY_Pos)
218 #define DW_UART_USR_BUSY_SET DW_UART_USR_BUSY_Msk
219
220 #define DW_UART_USR_TFNF_Pos (1U)
221 #define DW_UART_USR_TFNF_Msk (0x1U << DW_UART_USR_TFNF_Pos)
222 #define DW_UART_USR_TFNF_SET DW_UART_USR_TFNF_Msk
223
224 #define DW_UART_USR_TFE_Pos (2U)
225 #define DW_UART_USR_TFE_Msk (0x1U << DW_UART_USR_TFE_Pos)
226 #define DW_UART_USR_TFE_SET DW_UART_USR_TFE_Msk
227
228 #define DW_UART_USR_RFNE_Pos (3U)
229 #define DW_UART_USR_RFNE_Msk (0x1U << DW_UART_USR_RFNE_Pos)
230 #define DW_UART_USR_RFNE_SET DW_UART_USR_RFNE_Msk
231
232 #define DW_UART_USR_RFF_Pos (4U)
233 #define DW_UART_USR_RFF_Msk (0x1U << DW_UART_USR_RFF_Pos)
234 #define DW_UART_USR_RFF_SET DW_UART_USR_RFF_Msk
235
236 /*! TFL, offset: 0x80 */
237 #define DW_UART_TFL_TFIFOL_Pos (0U)
238 #define DW_UART_TFL_TFIFOL_Msk (0x1FU << DW_UART_TFL_TFIFOL_Pos)
239 #define DW_UART_TFL_TFIFOL(n) (nU << DW_UART_TFL_TFIFOL_Pos)
240
241 /*! RFL, offset: 0x84 */
242 #define DW_UART_RFL_RFIFOL_Pos (0U)
243 #define DW_UART_RFL_RFIFOL_Msk (0x1FU << DW_UART_RFL_RFIFOL_Pos)
244 #define DW_UART_RFL_RFIFOL(n) (nU << DW_UART_TFL_TFIFOL_Pos)
245
246 /*! HTX, offset: 0xA4 */
247 #define DW_UART_HTX_HALTTX_Pos (0U)
248 #define DW_UART_HTX_HALTTX_Msk (0x1U << DW_UART_HTX_HALTTX_Pos)
249 #define DW_UART_HTX_HALTTX_EN DW_UART_HTX_HALTTX_Msk
250
251 #define DW_UART_HTX_RX_ETB_FUNC_Pos (6U)
252 #define DW_UART_HTX_RX_ETB_FUNC_Msk (0x1U << DW_UART_HTX_RX_ETB_FUNC_Pos)
253 #define DW_UART_HTX_RX_ETB_FUNC_EN DW_UART_HTX_RX_ETB_FUNC_Msk
254
255 #define DW_UART_HTX_TX_ETB_FUNC_Pos (7U)
256 #define DW_UART_HTX_TX_ETB_FUNC_Msk (0x1U << DW_UART_HTX_TX_ETB_FUNC_Pos)
257 #define DW_UART_HTX_TX_ETB_FUNC_EN DW_UART_HTX_TX_ETB_FUNC_Msk
258
259 /*! DMASA, offset: 0xA8 */
260 #define DW_UART_DMASA_DMASACK_Pos (0U)
261 #define DW_UART_DMASA_DMASACK_Msk (0x1U << DW_UART_DMASA_DMASACK_Pos)
262 #define DW_UART_DMASA_DMASACK_SET DW_UART_DMASA_DMASACK_Msk
263
264 /* FIFO CONFIG */
265 #define UART_FIFO_INIT_CONFIG (DW_UART_FCR_FIFOE_EN | DW_UART_FCR_RT_FIFO_1_2_FULL|DW_UART_FCR_RFIFOR_RESET|DW_UART_FCR_XFIFOR_RESET)
266
267 /*! UART_RATE, offset: 0x3FC */
268 #define DW_UART_SUPPORT_RATE 0x10102U
269
270 #define UART_BUSY_TIMEOUT 0x70000000U
271
272 typedef struct {
273 union {
274 __IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */
275 __OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */
276 __IOM uint32_t DLL; /* Offset: 0x000 (R/W) Clock frequency division low section register */
277 };
278 union {
279 __IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section register */
280 __IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */
281 };
282 union {
283 __IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt identification register */
284 __OM uint32_t FCR; /* Offset: 0x008 ( /W) FIFO control register */
285 };
286 __IOM uint32_t LCR; /* Offset: 0x00C (R/W) Line control register */
287 __IOM uint32_t MCR; /* Offset: 0x010 (R/W) Modem control register */
288 __IM uint32_t LSR; /* Offset: 0x014 (R/ ) Line state register */
289 __IM uint32_t MSR; /* Offset: 0x018 (R/ ) Modem state register */
290 uint32_t RESERVED1[21];
291 __IM uint32_t USR; /* Offset: 0x07c (R/ ) UART state register */
292 } dw_uart_regs_t;
293
dw_uart_enable_recv_irq(dw_uart_regs_t * uart_base)294 static inline void dw_uart_enable_recv_irq(dw_uart_regs_t *uart_base)
295 {
296 uart_base->IER |= (DW_UART_IER_ERBFI_EN | DW_UART_IER_ELSI_EN);
297 }
298
dw_uart_disable_recv_irq(dw_uart_regs_t * uart_base)299 static inline void dw_uart_disable_recv_irq(dw_uart_regs_t *uart_base)
300 {
301 uart_base->IER &= ~(DW_UART_IER_ERBFI_EN | DW_UART_IER_ELSI_EN);
302 }
303
dw_uart_enable_trans_irq(dw_uart_regs_t * uart_base)304 static inline void dw_uart_enable_trans_irq(dw_uart_regs_t *uart_base)
305 {
306 uart_base->IER |= DW_UART_IER_ETBEI_EN;
307 }
308
dw_uart_disable_trans_irq(dw_uart_regs_t * uart_base)309 static inline void dw_uart_disable_trans_irq(dw_uart_regs_t *uart_base)
310 {
311 uart_base->IER &= ~(DW_UART_IER_ETBEI_EN);
312 }
313
dw_uart_fifo_init(dw_uart_regs_t * uart_base)314 static inline void dw_uart_fifo_init(dw_uart_regs_t *uart_base)
315 {
316 /* FIFO enable */
317 uart_base->FCR = UART_FIFO_INIT_CONFIG;
318 }
319
dw_uart_fifo_enable(dw_uart_regs_t * uart_base)320 static inline void dw_uart_fifo_enable(dw_uart_regs_t *uart_base)
321 {
322 uart_base->FCR |= DW_UART_FCR_FIFOE_EN;
323 }
324
dw_uart_fifo_disable(dw_uart_regs_t * uart_base)325 static inline void dw_uart_fifo_disable(dw_uart_regs_t *uart_base)
326 {
327 uart_base->FCR &= ~(DW_UART_FCR_FIFOE_EN);
328 }
329
dw_uart_putready(dw_uart_regs_t * uart_base)330 static inline uint32_t dw_uart_putready(dw_uart_regs_t *uart_base)
331 {
332 uint32_t status = 0U, ret = 0U;
333
334 status = uart_base->LSR & DW_UART_LSR_THRE_SET;
335
336 if (status != 0U) {
337 ret = 1U;
338 }
339
340 return ret;
341 }
342
dw_uart_getready(dw_uart_regs_t * uart_base)343 static inline uint32_t dw_uart_getready(dw_uart_regs_t *uart_base)
344 {
345 uint32_t status = 0U, ret = 0U;
346
347 status = uart_base->LSR & DW_UART_LSR_DR_READY;
348
349 if (status != 0U) {
350 ret = 1U;
351 }
352
353 return ret;
354 }
355
dw_uart_get_line_status(dw_uart_regs_t * uart_base)356 static inline uint32_t dw_uart_get_line_status(dw_uart_regs_t *uart_base)
357 {
358 return uart_base->LSR;
359 }
360
dw_uart_config_stop_bits_1(dw_uart_regs_t * uart_base)361 static inline void dw_uart_config_stop_bits_1(dw_uart_regs_t *uart_base)
362 {
363 uart_base->LCR &= ~(DW_UART_LCR_STOP_Msk);
364 }
365
dw_uart_config_stop_bits_2(dw_uart_regs_t * uart_base)366 static inline void dw_uart_config_stop_bits_2(dw_uart_regs_t *uart_base)
367 {
368 uart_base->LCR |= DW_UART_LCR_STOP_2_BIT;
369 }
370
dw_uart_putchar(dw_uart_regs_t * uart_base,uint8_t ch)371 static inline void dw_uart_putchar(dw_uart_regs_t *uart_base, uint8_t ch)
372 {
373 uart_base->THR = ch;
374 }
375
dw_uart_getchar(dw_uart_regs_t * uart_base)376 static inline uint8_t dw_uart_getchar(dw_uart_regs_t *uart_base)
377 {
378 return (uint8_t)(uart_base->RBR);
379 }
380
dw_uart_get_intr_en_status(dw_uart_regs_t * uart_base)381 static inline uint32_t dw_uart_get_intr_en_status(dw_uart_regs_t *uart_base)
382 {
383 return uart_base->IER;
384 }
385
dw_uart_set_intr_en_status(dw_uart_regs_t * uart_base,uint32_t status)386 static inline void dw_uart_set_intr_en_status(dw_uart_regs_t *uart_base, uint32_t status)
387 {
388 uart_base->IER = status;
389 }
390
dw_uart_set_fcr_reg(dw_uart_regs_t * uart_base,uint32_t value)391 static inline void dw_uart_set_fcr_reg(dw_uart_regs_t *uart_base, uint32_t value)
392 {
393 uart_base->FCR = value;
394 }
395
dw_uart_enable_auto_flow_control(dw_uart_regs_t * uart_base)396 static inline void dw_uart_enable_auto_flow_control(dw_uart_regs_t *uart_base)
397 {
398 uart_base->MCR |= DW_UART_MCR_AFCE_EN;
399 uart_base->MCR |= DW_UART_MCR_RTS_EN;
400 }
401
dw_uart_disable_auto_flow_control(dw_uart_regs_t * uart_base)402 static inline void dw_uart_disable_auto_flow_control(dw_uart_regs_t *uart_base)
403 {
404 uart_base->MCR &= ~DW_UART_MCR_AFCE_EN;
405 uart_base->MCR &= ~DW_UART_MCR_RTS_EN;
406 }
407
408 int32_t dw_uart_wait_timeout(dw_uart_regs_t *uart_base);
409
410 int32_t dw_uart_wait_idle(dw_uart_regs_t *uart_base);
411
412 int32_t dw_uart_config_baudrate(dw_uart_regs_t *uart_base, uint32_t baud, uint32_t uart_freq);
413
414 int32_t dw_uart_config_stop_bits(dw_uart_regs_t *uart_base, uint32_t stop_bits);
415
416 int32_t dw_uart_config_parity_none(dw_uart_regs_t *uart_base);
417
418 int32_t dw_uart_config_parity_odd(dw_uart_regs_t *uart_base);
419
420 int32_t dw_uart_config_parity_even(dw_uart_regs_t *uart_base);
421
422 int32_t dw_uart_config_data_bits(dw_uart_regs_t *uart_base, uint32_t data_bits);
423
424 #ifdef __cplusplus
425 }
426 #endif
427
428 #endif /* _DW_UART_LL_H_ */
429
430