1 /*
2 * Copyright (c) 2006-2020, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2020-08-19 lizhirui porting to ls2k
9 */
10
11 #include <rtthread.h>
12 #include <rtdef.h>
13 #include <mips_addrspace.h>
14 #include <ata_interface.h>
15 #include <ahci.h>
16 #include <dwc_ahsata.h>
17 #include <fis.h>
18 #include <libata.h>
19 #include <ata_debug.h>
20 #include <blk_device.h>
21 #include "dwc_ahsata_priv.h"
22
23 struct sata_port_regs
24 {
25 u32 clb;
26 u32 clbu;
27 u32 fb;
28 u32 fbu;
29 u32 is;
30 u32 ie;
31 u32 cmd;
32 u32 res1[1];
33 u32 tfd;
34 u32 sig;
35 u32 ssts;
36 u32 sctl;
37 u32 serr;
38 u32 sact;
39 u32 ci;
40 u32 sntf;
41 u32 res2[1];
42 u32 dmacr;
43 u32 res3[1];
44 u32 phycr;
45 u32 physr;
46 };
47
48 struct sata_host_regs
49 {
50 u32 cap;
51 u32 ghc;
52 u32 is;
53 u32 pi;
54 u32 vs;
55 u32 ccc_ctl;
56 u32 ccc_ports;
57 u32 res1[2];
58 u32 cap2;
59 u32 res2[30];
60 u32 bistafr;
61 u32 bistcr;
62 u32 bistfctr;
63 u32 bistsr;
64 u32 bistdecr;
65 u32 res3[2];
66 u32 oobr;
67 u32 res4[8];
68 u32 timer1ms;
69 u32 res5[1];
70 u32 gparam1r;
71 u32 gparam2r;
72 u32 pparamr;
73 u32 testr;
74 u32 versionr;
75 u32 idr;
76 };
77
78 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
79 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
80
81 #define writel_with_flush(a, b) \
82 do \
83 { \
84 writel(a, b); \
85 readl(b); \
86 } while (0)
87
ahci_port_base(void __iomem * base,u32 port)88 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
89 {
90 return base + 0x100 + (port * 0x80);
91 }
92
waiting_for_cmd_completed(u8 * offset,int timeout_msec,u32 sign)93 static int waiting_for_cmd_completed(u8 *offset, int timeout_msec, u32 sign)
94 {
95 int i;
96 u32 status;
97
98 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
99 {
100 mdelay(1);
101 }
102
103 return (i < timeout_msec) ? 0 : -1;
104 }
105
ahci_setup_oobr(struct ahci_uc_priv * uc_priv,int clk)106 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
107 {
108 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
109
110 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
111 writel(0x02060b14, &host_mmio->oobr);
112
113 return 0;
114 }
115
ahci_host_init(struct ahci_uc_priv * uc_priv)116 int ahci_host_init(struct ahci_uc_priv *uc_priv)
117 {
118 u32 tmp, cap_save, num_ports;
119 int i, j, timeout = 1000;
120 struct sata_port_regs *port_mmio = NULL;
121 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
122
123 //prepare to enable staggered spin-up
124 cap_save = readl(&host_mmio->cap);
125 cap_save |= SATA_HOST_CAP_SSS;
126
127 /* global controller reset */
128 tmp = readl(&host_mmio->ghc);
129
130 //ahsata controller reset
131 if ((tmp & SATA_HOST_GHC_HR) == 0)
132 {
133 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
134 }
135
136 //wait for reset finishing
137 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
138 ;
139
140 //reset timeout
141 if (timeout <= 0)
142 {
143 debug("controller reset failed (0x%x)\n", tmp);
144 return -1;
145 }
146
147 /* Set timer 1ms @ 100MHz*/
148 writel(100000000 / 1000, &host_mmio->timer1ms);
149
150 ahci_setup_oobr(uc_priv, 0);
151
152 //enable ahci
153 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
154
155 //enable staggered spin-up
156 writel(cap_save, &host_mmio->cap);
157
158 //get sata port number
159 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
160
161 //initialize pi register to set correct port number
162 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
163
164 /*
165 * Determine which Ports are implemented by the DWC_ahsata,
166 * by reading the PI register. This bit map value aids the
167 * software to determine how many Ports are available and
168 * which Port registers need to be initialized.
169 */
170 uc_priv->cap = readl(&host_mmio->cap);
171 uc_priv->port_map = readl(&host_mmio->pi);
172
173 /* Determine how many command slots the HBA supports */
174 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
175
176 debug("cap 0x%x port_map 0x%x n_ports %d\n",
177 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
178
179 for (i = 0; i < uc_priv->n_ports; i++)
180 {
181 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
182 port_mmio = uc_priv->port[i].port_mmio;
183
184 /* Ensure that the DWC_ahsata is in idle state */
185 tmp = readl(&port_mmio->cmd);
186
187 /*
188 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
189 * are all cleared, the Port is in an idle state.
190 */
191 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
192 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST))
193 {
194
195 /*
196 * System software places a Port into the idle state by
197 * clearing P#CMD.ST and waiting for P#CMD.CR to return
198 * 0 when read.
199 */
200 tmp &= ~SATA_PORT_CMD_ST;
201 writel_with_flush(tmp, &port_mmio->cmd);
202
203 /*
204 * spec says 500 msecs for each bit, so
205 * this is slightly incorrect.
206 */
207 mdelay(500);
208
209 timeout = 1000;
210 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR) && --timeout)
211 ;
212
213 if (timeout <= 0)
214 {
215 debug("port reset failed (0x%x)\n", tmp);
216 return -1;
217 }
218 }
219
220 /* Spin-up device */
221 tmp = readl(&port_mmio->cmd);
222 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
223
224 /* Wait for spin-up to finish */
225 timeout = 1000;
226 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD) && --timeout)
227 ;
228
229 if (timeout <= 0)
230 {
231 debug("Spin-Up can't finish!\n");
232 return -1;
233 }
234
235 for (j = 0; j < 100; ++j)
236 {
237 mdelay(10);
238 tmp = readl(&port_mmio->ssts);
239 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
240 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
241 {
242 break;
243 }
244 }
245
246 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
247 timeout = 1000;
248 while (!(readl(&port_mmio->serr) & SATA_PORT_SERR_DIAG_X) && --timeout)
249 ;
250
251 if (timeout <= 0)
252 {
253 debug("Can't find DIAG_X set!\n");
254 return -1;
255 }
256
257 /*
258 * For each implemented Port, clear the P#SERR
259 * register, by writing ones to each implemented\
260 * bit location.
261 */
262 tmp = readl(&port_mmio->serr);
263 debug("P#SERR 0x%x\n",
264 tmp);
265 writel(tmp, &port_mmio->serr);
266
267 /* Ack any pending irq events for this port */
268 tmp = readl(&host_mmio->is);
269 debug("IS 0x%x\n", tmp);
270 if (tmp)
271 {
272 writel(tmp, &host_mmio->is);
273 }
274
275 writel(1 << i, &host_mmio->is);
276
277 /* set irq mask (enables interrupts) */
278 writel(DEF_PORT_IRQ, &port_mmio->ie);
279
280 /* register linkup ports */
281 tmp = readl(&port_mmio->ssts);
282 debug("Port %d status: 0x%x\n", i, tmp);
283 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
284 {
285 uc_priv->link_port_map |= (0x01 << i);
286 }
287 }
288
289 tmp = readl(&host_mmio->ghc);
290 debug("GHC 0x%x\n", tmp);
291 //Interrupt Enable
292 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
293 tmp = readl(&host_mmio->ghc);
294 debug("GHC 0x%x\n", tmp);
295
296 return 0;
297 }
298
rt_hw_ahci_host_init()299 int rt_hw_ahci_host_init()
300 {
301 struct ahci_uc_priv *ahci_device;
302 ahci_device = (struct ahci_uc_priv *)rt_device_create(RT_Device_Class_Miscellaneous, sizeof(struct ahci_uc_priv) - sizeof(struct rt_device));
303
304 ahci_device->mmio_base = (void *)DWCAHSATA_BASE;
305 ahci_device->parent.init = NULL;
306 ahci_device->parent.open = NULL;
307 ahci_device->parent.close = NULL;
308 ahci_device->parent.read = NULL;
309 ahci_device->parent.write = NULL;
310 ahci_device->parent.control = NULL;
311
312 if (rt_device_register((rt_device_t)ahci_device, "dwc_ahsata_ahci", 0) != RT_EOK)
313 {
314 rt_kprintf("dwc_ahsata_ahci device register failed!\n");
315 return -RT_ERROR;
316 }
317
318 if (dwc_ahsata_probe((rt_device_t)ahci_device) != 0)
319 {
320 rt_kprintf("ahci probe failed!\n");
321 return -RT_ERROR;
322 }
323
324 if (dwc_ahsata_scan((rt_device_t)ahci_device) != 0)
325 {
326 rt_kprintf("ahci host sata device scan failed!\n");
327 return -RT_ERROR;
328 }
329
330 return RT_EOK;
331 }
332 INIT_COMPONENT_EXPORT(rt_hw_ahci_host_init);
333
ahci_print_info(struct ahci_uc_priv * uc_priv)334 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
335 {
336 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
337 u32 vers, cap, impl, speed;
338 const char *speed_s;
339 const char *scc_s;
340
341 vers = readl(&host_mmio->vs);
342 cap = uc_priv->cap;
343 impl = uc_priv->port_map;
344
345 speed = (cap & SATA_HOST_CAP_ISS_MASK) >> SATA_HOST_CAP_ISS_OFFSET;
346
347 if (speed == 1)
348 {
349 speed_s = "1.5";
350 }
351 else if (speed == 2)
352 {
353 speed_s = "3";
354 }
355 else
356 {
357 speed_s = "?";
358 }
359
360 scc_s = "SATA";
361
362 rt_kprintf("AHCI %02x%02x.%02x%02x "
363 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
364 (vers >> 24) & 0xff,
365 (vers >> 16) & 0xff,
366 (vers >> 8) & 0xff,
367 vers & 0xff,
368 ((cap >> 8) & 0x1f) + 1,
369 (cap & 0x1f) + 1,
370 speed_s,
371 impl,
372 scc_s);
373
374 rt_kprintf("flags: "
375 "%s%s%s%s%s%s"
376 "%s%s%s%s%s%s%s\n",
377 cap & (1 << 31) ? "64bit " : "",
378 cap & (1 << 30) ? "ncq " : "",
379 cap & (1 << 28) ? "ilck " : "",
380 cap & (1 << 27) ? "stag " : "",
381 cap & (1 << 26) ? "pm " : "",
382 cap & (1 << 25) ? "led " : "",
383 cap & (1 << 24) ? "clo " : "",
384 cap & (1 << 19) ? "nz " : "",
385 cap & (1 << 18) ? "only " : "",
386 cap & (1 << 17) ? "pmp " : "",
387 cap & (1 << 15) ? "pio " : "",
388 cap & (1 << 14) ? "slum " : "",
389 cap & (1 << 13) ? "part " : "");
390
391 rt_kprintf("version = %08x\n", ((struct sata_host_regs *)(uc_priv->mmio_base))->versionr);
392 }
393
ahci_fill_sg(struct ahci_uc_priv * uc_priv,u8 port,unsigned char * buf,int buf_len)394 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
395 unsigned char *buf, int buf_len)
396 {
397 struct ahci_ioports *pp = &uc_priv->port[port];
398 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
399 u32 sg_count, max_bytes;
400 int i;
401
402 max_bytes = MAX_DATA_BYTES_PER_SG;
403 sg_count = ((buf_len - 1) / max_bytes) + 1;
404
405 if (sg_count > AHCI_MAX_SG)
406 {
407 rt_kprintf("Error:Too much sg!\n");
408 return -1;
409 }
410
411 for (i = 0; i < sg_count; i++)
412 {
413 ahci_sg->addr = VADDR_TO_PHY(buf + i * max_bytes);
414 //ahci_sg->addr_hi = 0;
415 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
416 (buf_len < max_bytes
417 ? (buf_len - 1)
418 : (max_bytes - 1)));
419 ahci_sg++;
420 buf_len -= max_bytes;
421 }
422
423 return sg_count;
424 }
425
ahci_fill_cmd_slot(struct ahci_ioports * pp,u32 cmd_slot,u32 opts)426 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
427 {
428 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
429 AHCI_CMD_SLOT_SZ * cmd_slot);
430
431 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
432 cmd_hdr->opts = cpu_to_le32(opts);
433 cmd_hdr->status = 0;
434 pp->cmd_slot->tbl_addr = VADDR_TO_PHY(pp->cmd_tbl);
435 /*#ifdef CONFIG_PHYS_64BIT
436 pp->cmd_slot->tbl_addr_hi =
437 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
438 #endif*/
439 }
440
441 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
442
ahci_exec_ata_cmd(struct ahci_uc_priv * uc_priv,u8 port,struct sata_fis_h2d * cfis,u8 * buf,u32 buf_len,s32 is_write)443 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
444 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
445 s32 is_write)
446 {
447 struct ahci_ioports *pp = &uc_priv->port[port];
448 struct sata_port_regs *port_mmio = pp->port_mmio;
449 u32 opts;
450 int sg_count = 0, cmd_slot = 0;
451
452 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
453
454 if (32 == cmd_slot)
455 {
456 rt_kprintf("Can't find empty command slot!\n");
457 return 0;
458 }
459
460 /* Check xfer length */
461 if (buf_len > MAX_BYTES_PER_TRANS)
462 {
463 rt_kprintf("Max transfer length is %dB\n\r",
464 MAX_BYTES_PER_TRANS);
465 return 0;
466 }
467
468 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
469
470 if (buf && buf_len)
471 {
472 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
473 }
474
475 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
476
477 if (is_write)
478 {
479 opts |= 0x40;
480 flush_cache((ulong)buf, buf_len);
481 }
482
483 ahci_fill_cmd_slot(pp, cmd_slot, opts);
484
485 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
486 writel_with_flush(1 << cmd_slot, &port_mmio->ci);
487
488 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
489 0x1 << cmd_slot))
490 {
491 rt_kprintf("timeout exit!\n");
492 return -1;
493 }
494
495 invalidate_dcache_range((int)(pp->cmd_slot),
496 (int)(pp->cmd_slot) + AHCI_PORT_PRIV_DMA_SZ);
497
498 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
499 pp->cmd_slot->status);
500
501 if (!is_write)
502 {
503 invalidate_dcache_range((ulong)buf, (ulong)buf + buf_len);
504 }
505
506 return buf_len;
507 }
508
ahci_set_feature(struct ahci_uc_priv * uc_priv,u8 port)509 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
510 {
511 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
512 struct sata_fis_h2d *cfis = &h2d;
513
514 memset(cfis, 0, sizeof(struct sata_fis_h2d));
515 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
516 cfis->pm_port_c = 1 << 7;
517 cfis->command = ATA_CMD_SET_FEATURES;
518 cfis->features = SETFEATURES_XFER;
519 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
520
521 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
522 }
523
ahci_port_start(struct ahci_uc_priv * uc_priv,u8 port)524 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
525 {
526 struct ahci_ioports *pp = &uc_priv->port[port];
527 struct sata_port_regs *port_mmio = pp->port_mmio;
528 u32 port_status;
529 u64 mem;
530 int timeout = 10000000;
531
532 debug("Enter start port: %d\n", port);
533 port_status = readl(&port_mmio->ssts);
534 debug("Port %d status: %x\n", port, port_status);
535
536 if ((port_status & 0xf) != 0x03)
537 {
538 rt_kprintf("No Link on this port!\n");
539 return -1;
540 }
541
542 mem = (u64)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
543
544 if (!mem)
545 {
546 rt_kprintf("No mem for table!\n");
547 return -ENOMEM;
548 }
549
550 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
551 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
552
553 /*
554 * First item in chunk of DMA memory: 32-slot command table,
555 * 32 bytes each in size
556 */
557 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
558 debug("cmd_slot = 0x%p\n", pp->cmd_slot);
559 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
560
561 /*
562 * Second item: Received-FIS area, 256-Byte aligned
563 */
564 pp->rx_fis = mem;
565 mem += AHCI_RX_FIS_SZ;
566
567 /*
568 * Third item: data area for storing a single command
569 * and its scatter-gather table
570 */
571 pp->cmd_tbl = mem;
572 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
573
574 mem += AHCI_CMD_TBL_HDR;
575
576 writel_with_flush(0x00004444, &port_mmio->dmacr);
577 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
578 writel_with_flush(LOW_PHY(pp->cmd_slot), &port_mmio->clb);
579 writel_with_flush(HIGH_PHY(pp->cmd_slot), &port_mmio->clbu);
580 writel_with_flush(LOW_PHY(pp->rx_fis), &port_mmio->fb);
581 writel_with_flush(HIGH_PHY(pp->rx_fis), &port_mmio->fbu);
582
583 /* Enable FRE */
584 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
585 &port_mmio->cmd);
586
587 /* Wait device ready */
588 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
589 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) &&
590 --timeout)
591 ;
592 if (timeout <= 0)
593 {
594 debug("Device not ready for BSY, DRQ and"
595 "ERR in TFD!\n");
596 return -1;
597 }
598
599 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
600 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
601 PORT_CMD_START,
602 &port_mmio->cmd);
603
604 debug("Exit start port %d\n", port);
605
606 return 0;
607 }
608
dwc_ahsata_print_info(struct blk_device * pdev)609 static void dwc_ahsata_print_info(struct blk_device *pdev)
610 {
611 rt_kprintf("SATA Device Info:\n\r");
612 rt_kprintf("S/N: %s\n\rProduct model number: %s\n\r"
613 "Firmware version: %s\n\rCapacity: %lu sectors\n\r",
614 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
615 }
616
dwc_ahsata_identify(struct ahci_uc_priv * uc_priv,u16 * id)617 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
618 {
619 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
620 struct sata_fis_h2d *cfis = &h2d;
621 u8 port = uc_priv->hard_port_no;
622
623 memset(cfis, 0, sizeof(struct sata_fis_h2d));
624
625 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
626 cfis->pm_port_c = 0x80; /* is command */
627 cfis->command = ATA_CMD_ID_ATA;
628
629 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
630 READ_CMD);
631 ata_swap_buf_le16(id, ATA_ID_WORDS);
632 }
633
dwc_ahsata_xfer_mode(struct ahci_uc_priv * uc_priv,u16 * id)634 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
635 {
636 uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
637 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
638 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
639 }
640
dwc_ahsata_rw_cmd(struct ahci_uc_priv * uc_priv,u32 start,u32 blkcnt,u8 * buffer,int is_write)641 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
642 u32 blkcnt, u8 *buffer, int is_write)
643 {
644 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
645 struct sata_fis_h2d *cfis = &h2d;
646 u8 port = uc_priv->hard_port_no;
647 u32 block;
648
649 block = start;
650
651 memset(cfis, 0, sizeof(struct sata_fis_h2d));
652
653 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
654 cfis->pm_port_c = 0x80; /* is command */
655 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
656 cfis->device = ATA_LBA;
657
658 cfis->device |= (block >> 24) & 0xf;
659 cfis->lba_high = (block >> 16) & 0xff;
660 cfis->lba_mid = (block >> 8) & 0xff;
661 cfis->lba_low = block & 0xff;
662 cfis->sector_count = (u8)(blkcnt & 0xff);
663
664 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
665 ATA_SECT_SIZE * blkcnt, is_write) > 0)
666 return blkcnt;
667 else
668 return 0;
669 }
670
dwc_ahsata_flush_cache(struct ahci_uc_priv * uc_priv)671 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
672 {
673 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
674 struct sata_fis_h2d *cfis = &h2d;
675 u8 port = uc_priv->hard_port_no;
676
677 memset(cfis, 0, sizeof(struct sata_fis_h2d));
678
679 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
680 cfis->pm_port_c = 0x80; /* is command */
681 cfis->command = ATA_CMD_FLUSH;
682
683 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
684 }
685
dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv * uc_priv,u32 start,lbaint_t blkcnt,u8 * buffer,int is_write)686 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
687 lbaint_t blkcnt, u8 *buffer, int is_write)
688 {
689 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
690 struct sata_fis_h2d *cfis = &h2d;
691 u8 port = uc_priv->hard_port_no;
692 u64 block;
693
694 block = (u64)start;
695
696 memset(cfis, 0, sizeof(struct sata_fis_h2d));
697
698 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
699 cfis->pm_port_c = 0x80; /* is command */
700
701 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
702 : ATA_CMD_READ_EXT;
703
704 cfis->lba_high_exp = (block >> 40) & 0xff;
705 cfis->lba_mid_exp = (block >> 32) & 0xff;
706 cfis->lba_low_exp = (block >> 24) & 0xff;
707 cfis->lba_high = (block >> 16) & 0xff;
708 cfis->lba_mid = (block >> 8) & 0xff;
709 cfis->lba_low = block & 0xff;
710 cfis->device = ATA_LBA;
711 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
712 cfis->sector_count = blkcnt & 0xff;
713
714 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
715 ATA_SECT_SIZE * blkcnt, is_write) > 0)
716 return blkcnt;
717 else
718 return 0;
719 }
720
dwc_ahsata_flush_cache_ext(struct ahci_uc_priv * uc_priv)721 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
722 {
723 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
724 struct sata_fis_h2d *cfis = &h2d;
725 u8 port = uc_priv->hard_port_no;
726
727 memset(cfis, 0, sizeof(struct sata_fis_h2d));
728
729 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
730 cfis->pm_port_c = 0x80; /* is command */
731 cfis->command = ATA_CMD_FLUSH_EXT;
732
733 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
734 }
735
dwc_ahsata_init_wcache(struct ahci_uc_priv * uc_priv,u16 * id)736 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
737 {
738 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
739 uc_priv->flags |= SATA_FLAG_WCACHE;
740 if (ata_id_has_flush(id))
741 uc_priv->flags |= SATA_FLAG_FLUSH;
742 if (ata_id_has_flush_ext(id))
743 uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
744 }
745
ata_low_level_rw_lba48(struct ahci_uc_priv * uc_priv,u32 blknr,lbaint_t blkcnt,const void * buffer,int is_write)746 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
747 lbaint_t blkcnt, const void *buffer,
748 int is_write)
749 {
750 u32 start, blks;
751 u8 *addr;
752 int max_blks;
753
754 start = blknr;
755 blks = blkcnt;
756 addr = (u8 *)buffer;
757
758 max_blks = ATA_MAX_SECTORS_LBA48;
759
760 do
761 {
762 if (blks > max_blks)
763 {
764 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
765 max_blks, addr,
766 is_write))
767 return 0;
768 start += max_blks;
769 blks -= max_blks;
770 addr += ATA_SECT_SIZE * max_blks;
771 }
772 else
773 {
774 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
775 addr, is_write))
776 return 0;
777 start += blks;
778 blks = 0;
779 addr += ATA_SECT_SIZE * blks;
780 }
781 } while (blks != 0);
782
783 return blkcnt;
784 }
785
ata_low_level_rw_lba28(struct ahci_uc_priv * uc_priv,u32 blknr,lbaint_t blkcnt,const void * buffer,int is_write)786 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
787 lbaint_t blkcnt, const void *buffer,
788 int is_write)
789 {
790 u32 start, blks;
791 u8 *addr;
792 int max_blks;
793
794 start = blknr;
795 blks = blkcnt;
796 addr = (u8 *)buffer;
797
798 max_blks = ATA_MAX_SECTORS;
799 do
800 {
801 if (blks > max_blks)
802 {
803 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
804 max_blks, addr,
805 is_write))
806 return 0;
807 start += max_blks;
808 blks -= max_blks;
809 addr += ATA_SECT_SIZE * max_blks;
810 }
811 else
812 {
813 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
814 addr, is_write))
815 return 0;
816 start += blks;
817 blks = 0;
818 addr += ATA_SECT_SIZE * blks;
819 }
820 } while (blks != 0);
821
822 return blkcnt;
823 }
824
dwc_ahci_start_ports(struct ahci_uc_priv * uc_priv)825 static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
826 {
827 u32 linkmap;
828 int i;
829
830 linkmap = uc_priv->link_port_map;
831
832 if (0 == linkmap)
833 {
834 rt_kprintf("No port device detected!\n");
835 return -ENXIO;
836 }
837
838 for (i = 0; i < uc_priv->n_ports; i++)
839 {
840 if ((linkmap >> i) && ((linkmap >> i) & 0x01))
841 {
842 if (ahci_port_start(uc_priv, (u8)i))
843 {
844 rt_kprintf("Can not start port %d\n", i);
845 return 1;
846 }
847
848 uc_priv->hard_port_no = i;
849 break;
850 }
851 }
852
853 return 0;
854 }
855
856 unsigned char sector_data[512];
857
dump_pbuf(void * p,int len)858 void dump_pbuf(void *p, int len)
859 {
860 rt_kprintf("----dump_pbuf----\n");
861 rt_kprintf("pbuf = 0x%p,len = %d\n", p, len);
862 u32 i;
863 u8 *q = p;
864 rt_kprintf("%p", q);
865
866 for (i = 0; i < 16; i++)
867 {
868 rt_kprintf(" %02x", i);
869 }
870
871 rt_kprintf("\n");
872
873 for (i = 0; i < len; i++)
874 {
875 if (!(i & 0xF))
876 {
877 rt_kprintf("%p", &q[i]);
878 }
879
880 rt_kprintf(" %02x", q[i]);
881
882 if ((i & 0xF) == 0xF)
883 {
884 rt_kprintf("\n");
885 }
886 }
887
888 rt_kprintf("\n-----------------\n");
889 }
890
dwc_ahsata_scan_common(struct ahci_uc_priv * uc_priv,struct blk_device * pdev)891 static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
892 struct blk_device *pdev)
893 {
894 u8 serial[ATA_ID_SERNO_LEN + 1] = {0};
895 u8 firmware[ATA_ID_FW_REV_LEN + 1] = {0};
896 u8 product[ATA_ID_PROD_LEN + 1] = {0};
897 u8 port = uc_priv->hard_port_no;
898 ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
899
900 /* Identify device to get information */
901 dwc_ahsata_identify(uc_priv, id);
902
903 /* Serial number */
904 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
905 memcpy(pdev->product, serial, sizeof(serial));
906
907 /* Firmware version */
908 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
909 memcpy(pdev->revision, firmware, sizeof(firmware));
910
911 /* Product model */
912 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
913 memcpy(pdev->vendor, product, sizeof(product));
914
915 /* Total sectors */
916 pdev->lba = ata_id_n_sectors(id);
917
918 pdev->type = DEV_TYPE_HARDDISK;
919 pdev->blksz = ATA_SECT_SIZE;
920 pdev->lun = 0;
921
922 /* Check if support LBA48 */
923 if (ata_id_has_lba48(id))
924 {
925 pdev->lba48 = 1;
926 debug("Device support LBA48\n\r");
927 }
928
929 /* Get the NCQ queue depth from device */
930 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
931 uc_priv->flags |= ata_id_queue_depth(id);
932
933 /* Get the xfer mode from device */
934 dwc_ahsata_xfer_mode(uc_priv, id);
935
936 /* Get the write cache status from device */
937 dwc_ahsata_init_wcache(uc_priv, id);
938
939 /* Set the xfer mode to highest speed */
940 ahci_set_feature(uc_priv, port);
941 dwc_ahsata_read((rt_device_t)pdev, 0, sector_data, 1);
942 //dump_pbuf(sector_data, 512);
943 dwc_ahsata_print_info(pdev);
944
945 return 0;
946 }
947
948 /*
949 * SATA interface between low level driver and command layer
950 */
sata_read_common(struct ahci_uc_priv * uc_priv,struct blk_device * desc,ulong blknr,lbaint_t blkcnt,void * buffer)951 static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
952 struct blk_device *desc, ulong blknr,
953 lbaint_t blkcnt, void *buffer)
954 {
955 u32 rc;
956
957 if (desc->lba48)
958 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
959 READ_CMD);
960 else
961 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
962 READ_CMD);
963
964 return rc;
965 }
966
sata_write_common(struct ahci_uc_priv * uc_priv,struct blk_device * desc,ulong blknr,lbaint_t blkcnt,const void * buffer)967 static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
968 struct blk_device *desc, ulong blknr,
969 lbaint_t blkcnt, const void *buffer)
970 {
971 u32 rc;
972 u32 flags = uc_priv->flags;
973
974 if (desc->lba48)
975 {
976 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
977 WRITE_CMD);
978 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
979 dwc_ahsata_flush_cache_ext(uc_priv);
980 }
981 else
982 {
983 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
984 WRITE_CMD);
985 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
986 dwc_ahsata_flush_cache(uc_priv);
987 }
988
989 return rc;
990 }
991
992 #if !CONFIG_IS_ENABLED(AHCI)
ahci_init_one(int pdev)993 static int ahci_init_one(int pdev)
994 {
995 int rc;
996 struct ahci_uc_priv *uc_priv = NULL;
997
998 uc_priv = (struct ahci_uc_priv *)malloc(sizeof(struct ahci_uc_priv));
999 if (!uc_priv)
1000 return -ENOMEM;
1001
1002 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
1003 uc_priv->dev = pdev;
1004
1005 uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
1006
1007 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
1008
1009 /* initialize adapter */
1010 rc = ahci_host_init(uc_priv);
1011 if (rc)
1012 goto err_out;
1013
1014 ahci_print_info(uc_priv);
1015
1016 /* Save the uc_private struct to block device struct */
1017 sata_dev_desc[pdev].priv = uc_priv;
1018
1019 return 0;
1020
1021 err_out:
1022 if (uc_priv)
1023 free(uc_priv);
1024 return rc;
1025 }
1026
init_sata(int dev)1027 int init_sata(int dev)
1028 {
1029 struct ahci_uc_priv *uc_priv = NULL;
1030
1031 #if defined(CONFIG_MX6)
1032 if (!is_mx6dq() && !is_mx6dqp())
1033 return 1;
1034 #endif
1035 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
1036 {
1037 rt_kprintf("The sata index %d is out of ranges\n\r", dev);
1038 return -1;
1039 }
1040
1041 ahci_init_one(dev);
1042
1043 uc_priv = sata_dev_desc[dev].priv;
1044
1045 return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
1046 }
1047
reset_sata(int dev)1048 int reset_sata(int dev)
1049 {
1050 struct ahci_uc_priv *uc_priv;
1051 struct sata_host_regs *host_mmio;
1052
1053 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
1054 {
1055 rt_kprintf("The sata index %d is out of ranges\n\r", dev);
1056 return -1;
1057 }
1058
1059 uc_priv = sata_dev_desc[dev].priv;
1060 if (NULL == uc_priv)
1061 /* not initialized, so nothing to reset */
1062 return 0;
1063
1064 host_mmio = uc_priv->mmio_base;
1065 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
1066 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
1067 udelay(100);
1068
1069 free(uc_priv);
1070 memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc));
1071
1072 return 0;
1073 }
1074
sata_port_status(int dev,int port)1075 int sata_port_status(int dev, int port)
1076 {
1077 struct sata_port_regs *port_mmio;
1078 struct ahci_uc_priv *uc_priv = NULL;
1079
1080 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
1081 return -EINVAL;
1082
1083 if (sata_dev_desc[dev].priv == NULL)
1084 return -ENODEV;
1085
1086 uc_priv = sata_dev_desc[dev].priv;
1087 port_mmio = uc_priv->port[port].port_mmio;
1088
1089 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
1090 }
1091
1092 /*
1093 * SATA interface between low level driver and command layer
1094 */
sata_read(int dev,ulong blknr,lbaint_t blkcnt,void * buffer)1095 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
1096 {
1097 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
1098
1099 return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
1100 buffer);
1101 }
1102
sata_write(int dev,ulong blknr,lbaint_t blkcnt,const void * buffer)1103 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
1104 {
1105 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
1106
1107 return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
1108 buffer);
1109 }
1110
scan_sata(int dev)1111 int scan_sata(int dev)
1112 {
1113 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
1114 struct blk_desc *pdev = &sata_dev_desc[dev];
1115
1116 return dwc_ahsata_scan_common(uc_priv, pdev);
1117 }
1118 #endif /* CONFIG_IS_ENABLED(AHCI) */
1119
1120 #if CONFIG_IS_ENABLED(AHCI)
1121
dwc_ahsata_port_status(struct rt_device * dev,int port)1122 int dwc_ahsata_port_status(struct rt_device *dev, int port)
1123 {
1124 struct ahci_uc_priv *uc_priv = (struct ahci_uc_priv *)dev;
1125 struct sata_port_regs *port_mmio;
1126
1127 port_mmio = uc_priv->port[port].port_mmio;
1128 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
1129 }
1130
dwc_ahsata_bus_reset(struct rt_device * dev)1131 int dwc_ahsata_bus_reset(struct rt_device *dev)
1132 {
1133 struct ahci_uc_priv *uc_priv = (struct ahci_uc_priv *)dev;
1134 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
1135
1136 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
1137
1138 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
1139 {
1140 udelay(100);
1141 }
1142
1143 return 0;
1144 }
1145
dwc_ahsata_scan(struct rt_device * dev)1146 int dwc_ahsata_scan(struct rt_device *dev)
1147 {
1148 struct ahci_uc_priv *uc_priv = (struct ahci_uc_priv *)dev;
1149 struct blk_device *blk;
1150 rt_err_t ret;
1151
1152 blk = (struct blk_device *)rt_device_create(RT_Device_Class_Block, sizeof(struct blk_device) - sizeof(struct rt_device));
1153 blk->parent.init = NULL;
1154 blk->parent.open = NULL;
1155 blk->parent.close = NULL;
1156 blk->parent.control = dwc_ahsata_control;
1157 blk->parent.read = dwc_ahsata_read;
1158 blk->parent.write = dwc_ahsata_write;
1159 blk->ahci_device = uc_priv;
1160 blk->blksz = 512;
1161 blk->log2blksz = 9;
1162 blk->lba = 0;
1163 ret = rt_device_register((rt_device_t)blk, "dwc_ahsata_blk", RT_DEVICE_FLAG_RDWR);
1164
1165 if (ret != RT_EOK)
1166 {
1167 debug("Can't create device\n");
1168 return ret;
1169 }
1170
1171 ret = dwc_ahsata_scan_common(uc_priv, blk);
1172
1173 if (ret)
1174 {
1175 debug("%s: Failed to scan bus\n", __func__);
1176 return ret;
1177 }
1178
1179 return 0;
1180 }
1181
dwc_ahsata_probe(struct rt_device * dev)1182 int dwc_ahsata_probe(struct rt_device *dev)
1183 {
1184 struct ahci_uc_priv *uc_priv = (struct ahci_uc_priv *)dev;
1185 int ret;
1186
1187 uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
1188 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
1189
1190 /* initialize adapter */
1191 ret = ahci_host_init(uc_priv);
1192 if (ret)
1193 return ret;
1194
1195 ahci_print_info(uc_priv);
1196
1197 return dwc_ahci_start_ports(uc_priv);
1198 }
1199
dwc_ahsata_read(rt_device_t dev,rt_off_t pos,void * buffer,rt_size_t size)1200 rt_ssize_t dwc_ahsata_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
1201 {
1202 struct blk_device *blk = (struct blk_device *)dev;
1203 return sata_read_common(blk->ahci_device, blk, pos, size, buffer);
1204 }
1205
dwc_ahsata_write(rt_device_t dev,rt_off_t pos,const void * buffer,rt_size_t size)1206 rt_ssize_t dwc_ahsata_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
1207 {
1208 struct blk_device *blk = (struct blk_device *)dev;
1209 return sata_write_common(blk->ahci_device, blk, pos, size, buffer);
1210 }
1211
dwc_ahsata_control(rt_device_t dev,int cmd,void * args)1212 rt_err_t dwc_ahsata_control(rt_device_t dev, int cmd, void *args)
1213 {
1214 struct blk_device *blk = (struct blk_device *)dev;
1215
1216 switch (cmd)
1217 {
1218 case RT_DEVICE_CTRL_BLK_GETGEOME:
1219
1220 if (args != NULL)
1221 {
1222 struct rt_device_blk_geometry *info = (struct rt_device_blk_geometry *)args;
1223 info->sector_count = blk->lba;
1224 info->bytes_per_sector = blk->blksz;
1225 info->block_size = 0;
1226 }
1227
1228 break;
1229 }
1230
1231 return RT_EOK;
1232 }
1233
1234 #endif
1235