1 /* 2 * Copyright (c) 2006-2020, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2020-08-19 lizhirui porting to ls2k 9 */ 10 11 #ifndef __DWC_AHSATA_PRIV_H__ 12 #define __DWC_AHSATA_PRIV_H__ 13 14 #define DWC_AHSATA_MAX_CMD_SLOTS 32 15 16 /* Max host controller numbers */ 17 #define SATA_HC_MAX_NUM 4 18 /* Max command queue depth per host controller */ 19 #define DWC_AHSATA_HC_MAX_CMD 32 20 /* Max port number per host controller */ 21 #define SATA_HC_MAX_PORT 16 22 23 /* Generic Host Register */ 24 25 /* HBA Capabilities Register */ 26 #define SATA_HOST_CAP_S64A 0x80000000 27 #define SATA_HOST_CAP_SNCQ 0x40000000 28 #define SATA_HOST_CAP_SSNTF 0x20000000 29 #define SATA_HOST_CAP_SMPS 0x10000000 30 #define SATA_HOST_CAP_SSS 0x08000000 31 #define SATA_HOST_CAP_SALP 0x04000000 32 #define SATA_HOST_CAP_SAL 0x02000000 33 #define SATA_HOST_CAP_SCLO 0x01000000 34 #define SATA_HOST_CAP_ISS_MASK 0x00f00000 35 #define SATA_HOST_CAP_ISS_OFFSET 20 36 #define SATA_HOST_CAP_SNZO 0x00080000 37 #define SATA_HOST_CAP_SAM 0x00040000 38 #define SATA_HOST_CAP_SPM 0x00020000 39 #define SATA_HOST_CAP_PMD 0x00008000 40 #define SATA_HOST_CAP_SSC 0x00004000 41 #define SATA_HOST_CAP_PSC 0x00002000 42 #define SATA_HOST_CAP_NCS 0x00001f00 43 #define SATA_HOST_CAP_CCCS 0x00000080 44 #define SATA_HOST_CAP_EMS 0x00000040 45 #define SATA_HOST_CAP_SXS 0x00000020 46 #define SATA_HOST_CAP_NP_MASK 0x0000001f 47 48 /* Global HBA Control Register */ 49 #define SATA_HOST_GHC_AE 0x80000000 50 #define SATA_HOST_GHC_IE 0x00000002 51 #define SATA_HOST_GHC_HR 0x00000001 52 53 /* Interrupt Status Register */ 54 55 /* Ports Implemented Register */ 56 57 /* AHCI Version Register */ 58 #define SATA_HOST_VS_MJR_MASK 0xffff0000 59 #define SATA_HOST_VS_MJR_OFFSET 16 60 #define SATA_HOST_VS_MJR_MNR 0x0000ffff 61 62 /* Command Completion Coalescing Control */ 63 #define SATA_HOST_CCC_CTL_TV_MASK 0xffff0000 64 #define SATA_HOST_CCC_CTL_TV_OFFSET 16 65 #define SATA_HOST_CCC_CTL_CC_MASK 0x0000ff00 66 #define SATA_HOST_CCC_CTL_CC_OFFSET 8 67 #define SATA_HOST_CCC_CTL_INT_MASK 0x000000f8 68 #define SATA_HOST_CCC_CTL_INT_OFFSET 3 69 #define SATA_HOST_CCC_CTL_EN 0x00000001 70 71 /* Command Completion Coalescing Ports */ 72 73 /* HBA Capabilities Extended Register */ 74 #define SATA_HOST_CAP2_APST 0x00000004 75 76 /* BIST Activate FIS Register */ 77 #define SATA_HOST_BISTAFR_NCP_MASK 0x0000ff00 78 #define SATA_HOST_BISTAFR_NCP_OFFSET 8 79 #define SATA_HOST_BISTAFR_PD_MASK 0x000000ff 80 #define SATA_HOST_BISTAFR_PD_OFFSET 0 81 82 /* BIST Control Register */ 83 #define SATA_HOST_BISTCR_FERLB 0x00100000 84 #define SATA_HOST_BISTCR_TXO 0x00040000 85 #define SATA_HOST_BISTCR_CNTCLR 0x00020000 86 #define SATA_HOST_BISTCR_NEALB 0x00010000 87 #define SATA_HOST_BISTCR_LLC_MASK 0x00000700 88 #define SATA_HOST_BISTCR_LLC_OFFSET 8 89 #define SATA_HOST_BISTCR_ERREN 0x00000040 90 #define SATA_HOST_BISTCR_FLIP 0x00000020 91 #define SATA_HOST_BISTCR_PV 0x00000010 92 #define SATA_HOST_BISTCR_PATTERN_MASK 0x0000000f 93 #define SATA_HOST_BISTCR_PATTERN_OFFSET 0 94 95 /* BIST FIS Count Register */ 96 97 /* BIST Status Register */ 98 #define SATA_HOST_BISTSR_FRAMERR_MASK 0x0000ffff 99 #define SATA_HOST_BISTSR_FRAMERR_OFFSET 0 100 #define SATA_HOST_BISTSR_BRSTERR_MASK 0x00ff0000 101 #define SATA_HOST_BISTSR_BRSTERR_OFFSET 16 102 103 /* BIST DWORD Error Count Register */ 104 105 /* OOB Register*/ 106 #define SATA_HOST_OOBR_WE 0x80000000 107 #define SATA_HOST_OOBR_cwMin_MASK 0x7f000000 108 #define SATA_HOST_OOBR_cwMAX_MASK 0x00ff0000 109 #define SATA_HOST_OOBR_ciMin_MASK 0x0000ff00 110 #define SATA_HOST_OOBR_ciMax_MASK 0x000000ff 111 112 /* Timer 1-ms Register */ 113 114 /* Global Parameter 1 Register */ 115 #define SATA_HOST_GPARAM1R_ALIGN_M 0x80000000 116 #define SATA_HOST_GPARAM1R_RX_BUFFER 0x40000000 117 #define SATA_HOST_GPARAM1R_PHY_DATA_MASK 0x30000000 118 #define SATA_HOST_GPARAM1R_PHY_RST 0x08000000 119 #define SATA_HOST_GPARAM1R_PHY_CTRL_MASK 0x07e00000 120 #define SATA_HOST_GPARAM1R_PHY_STAT_MASK 0x001f8000 121 #define SATA_HOST_GPARAM1R_LATCH_M 0x00004000 122 #define SATA_HOST_GPARAM1R_BIST_M 0x00002000 123 #define SATA_HOST_GPARAM1R_PHY_TYPE 0x00001000 124 #define SATA_HOST_GPARAM1R_RETURN_ERR 0x00000400 125 #define SATA_HOST_GPARAM1R_AHB_ENDIAN_MASK 0x00000300 126 #define SATA_HOST_GPARAM1R_S_HADDR 0X00000080 127 #define SATA_HOST_GPARAM1R_M_HADDR 0X00000040 128 129 /* Global Parameter 2 Register */ 130 #define SATA_HOST_GPARAM2R_DEV_CP 0x00004000 131 #define SATA_HOST_GPARAM2R_DEV_MP 0x00002000 132 #define SATA_HOST_GPARAM2R_DEV_ENCODE_M 0x00001000 133 #define SATA_HOST_GPARAM2R_RXOOB_CLK_M 0x00000800 134 #define SATA_HOST_GPARAM2R_RXOOB_M 0x00000400 135 #define SATA_HOST_GPARAM2R_TX_OOB_M 0x00000200 136 #define SATA_HOST_GPARAM2R_RXOOB_CLK_MASK 0x000001ff 137 138 /* Port Parameter Register */ 139 #define SATA_HOST_PPARAMR_TX_MEM_M 0x00000200 140 #define SATA_HOST_PPARAMR_TX_MEM_S 0x00000100 141 #define SATA_HOST_PPARAMR_RX_MEM_M 0x00000080 142 #define SATA_HOST_PPARAMR_RX_MEM_S 0x00000040 143 #define SATA_HOST_PPARAMR_TXFIFO_DEPTH_MASK 0x00000038 144 #define SATA_HOST_PPARAMR_RXFIFO_DEPTH_MASK 0x00000007 145 146 /* Test Register */ 147 #define SATA_HOST_TESTR_PSEL_MASK 0x00070000 148 #define SATA_HOST_TESTR_TEST_IF 0x00000001 149 150 /* Port Register Descriptions */ 151 /* Port# Command List Base Address Register */ 152 #define SATA_PORT_CLB_CLB_MASK 0xfffffc00 153 154 /* Port# Command List Base Address Upper 32-Bits Register */ 155 156 /* Port# FIS Base Address Register */ 157 #define SATA_PORT_FB_FB_MASK 0xfffffff0 158 159 /* Port# FIS Base Address Upper 32-Bits Register */ 160 161 /* Port# Interrupt Status Register */ 162 #define SATA_PORT_IS_CPDS 0x80000000 163 #define SATA_PORT_IS_TFES 0x40000000 164 #define SATA_PORT_IS_HBFS 0x20000000 165 #define SATA_PORT_IS_HBDS 0x10000000 166 #define SATA_PORT_IS_IFS 0x08000000 167 #define SATA_PORT_IS_INFS 0x04000000 168 #define SATA_PORT_IS_OFS 0x01000000 169 #define SATA_PORT_IS_IPMS 0x00800000 170 #define SATA_PORT_IS_PRCS 0x00400000 171 #define SATA_PORT_IS_DMPS 0x00000080 172 #define SATA_PORT_IS_PCS 0x00000040 173 #define SATA_PORT_IS_DPS 0x00000020 174 #define SATA_PORT_IS_UFS 0x00000010 175 #define SATA_PORT_IS_SDBS 0x00000008 176 #define SATA_PORT_IS_DSS 0x00000004 177 #define SATA_PORT_IS_PSS 0x00000002 178 #define SATA_PORT_IS_DHRS 0x00000001 179 180 /* Port# Interrupt Enable Register */ 181 #define SATA_PORT_IE_CPDE 0x80000000 182 #define SATA_PORT_IE_TFEE 0x40000000 183 #define SATA_PORT_IE_HBFE 0x20000000 184 #define SATA_PORT_IE_HBDE 0x10000000 185 #define SATA_PORT_IE_IFE 0x08000000 186 #define SATA_PORT_IE_INFE 0x04000000 187 #define SATA_PORT_IE_OFE 0x01000000 188 #define SATA_PORT_IE_IPME 0x00800000 189 #define SATA_PORT_IE_PRCE 0x00400000 190 #define SATA_PORT_IE_DMPE 0x00000080 191 #define SATA_PORT_IE_PCE 0x00000040 192 #define SATA_PORT_IE_DPE 0x00000020 193 #define SATA_PORT_IE_UFE 0x00000010 194 #define SATA_PORT_IE_SDBE 0x00000008 195 #define SATA_PORT_IE_DSE 0x00000004 196 #define SATA_PORT_IE_PSE 0x00000002 197 #define SATA_PORT_IE_DHRE 0x00000001 198 199 /* Port# Command Register */ 200 #define SATA_PORT_CMD_ICC_MASK 0xf0000000 201 #define SATA_PORT_CMD_ASP 0x08000000 202 #define SATA_PORT_CMD_ALPE 0x04000000 203 #define SATA_PORT_CMD_DLAE 0x02000000 204 #define SATA_PORT_CMD_ATAPI 0x01000000 205 #define SATA_PORT_CMD_APSTE 0x00800000 206 #define SATA_PORT_CMD_ESP 0x00200000 207 #define SATA_PORT_CMD_CPD 0x00100000 208 #define SATA_PORT_CMD_MPSP 0x00080000 209 #define SATA_PORT_CMD_HPCP 0x00040000 210 #define SATA_PORT_CMD_PMA 0x00020000 211 #define SATA_PORT_CMD_CPS 0x00010000 212 #define SATA_PORT_CMD_CR 0x00008000 213 #define SATA_PORT_CMD_FR 0x00004000 214 #define SATA_PORT_CMD_MPSS 0x00002000 215 #define SATA_PORT_CMD_CCS_MASK 0x00001f00 216 #define SATA_PORT_CMD_FRE 0x00000010 217 #define SATA_PORT_CMD_CLO 0x00000008 218 #define SATA_PORT_CMD_POD 0x00000004 219 #define SATA_PORT_CMD_SUD 0x00000002 220 #define SATA_PORT_CMD_ST 0x00000001 221 222 /* Port# Task File Data Register */ 223 #define SATA_PORT_TFD_ERR_MASK 0x0000ff00 224 #define SATA_PORT_TFD_STS_MASK 0x000000ff 225 #define SATA_PORT_TFD_STS_ERR 0x00000001 226 #define SATA_PORT_TFD_STS_DRQ 0x00000008 227 #define SATA_PORT_TFD_STS_BSY 0x00000080 228 229 /* Port# Signature Register */ 230 231 /* Port# Serial ATA Status {SStatus} Register */ 232 #define SATA_PORT_SSTS_IPM_MASK 0x00000f00 233 #define SATA_PORT_SSTS_SPD_MASK 0x000000f0 234 #define SATA_PORT_SSTS_DET_MASK 0x0000000f 235 236 /* Port# Serial ATA Control {SControl} Register */ 237 #define SATA_PORT_SCTL_IPM_MASK 0x00000f00 238 #define SATA_PORT_SCTL_SPD_MASK 0x000000f0 239 #define SATA_PORT_SCTL_DET_MASK 0x0000000f 240 241 /* Port# Serial ATA Error {SError} Register */ 242 #define SATA_PORT_SERR_DIAG_X 0x04000000 243 #define SATA_PORT_SERR_DIAG_F 0x02000000 244 #define SATA_PORT_SERR_DIAG_T 0x01000000 245 #define SATA_PORT_SERR_DIAG_S 0x00800000 246 #define SATA_PORT_SERR_DIAG_H 0x00400000 247 #define SATA_PORT_SERR_DIAG_C 0x00200000 248 #define SATA_PORT_SERR_DIAG_D 0x00100000 249 #define SATA_PORT_SERR_DIAG_B 0x00080000 250 #define SATA_PORT_SERR_DIAG_W 0x00040000 251 #define SATA_PORT_SERR_DIAG_I 0x00020000 252 #define SATA_PORT_SERR_DIAG_N 0x00010000 253 #define SATA_PORT_SERR_ERR_E 0x00000800 254 #define SATA_PORT_SERR_ERR_P 0x00000400 255 #define SATA_PORT_SERR_ERR_C 0x00000200 256 #define SATA_PORT_SERR_ERR_T 0x00000100 257 #define SATA_PORT_SERR_ERR_M 0x00000002 258 #define SATA_PORT_SERR_ERR_I 0x00000001 259 260 /* Port# Serial ATA Active {SActive} Register */ 261 262 /* Port# Command Issue Register */ 263 264 /* Port# Serial ATA Notification Register */ 265 266 /* Port# DMA Control Register */ 267 #define SATA_PORT_DMACR_RXABL_MASK 0x0000f000 268 #define SATA_PORT_DMACR_TXABL_MASK 0x00000f00 269 #define SATA_PORT_DMACR_RXTS_MASK 0x000000f0 270 #define SATA_PORT_DMACR_TXTS_MASK 0x0000000f 271 272 /* Port# PHY Control Register */ 273 274 /* Port# PHY Status Register */ 275 276 #define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry) 277 278 /* DW0 279 */ 280 #define CMD_HDR_DI_CFL_MASK 0x0000001f 281 #define CMD_HDR_DI_CFL_OFFSET 0 282 #define CMD_HDR_DI_A 0x00000020 283 #define CMD_HDR_DI_W 0x00000040 284 #define CMD_HDR_DI_P 0x00000080 285 #define CMD_HDR_DI_R 0x00000100 286 #define CMD_HDR_DI_B 0x00000200 287 #define CMD_HDR_DI_C 0x00000400 288 #define CMD_HDR_DI_PMP_MASK 0x0000f000 289 #define CMD_HDR_DI_PMP_OFFSET 12 290 #define CMD_HDR_DI_PRDTL 0xffff0000 291 #define CMD_HDR_DI_PRDTL_OFFSET 16 292 293 /* prde_fis_len 294 */ 295 #define CMD_HDR_PRD_ENTRY_SHIFT 16 296 #define CMD_HDR_PRD_ENTRY_MASK 0x003f0000 297 #define CMD_HDR_FIS_LEN_SHIFT 2 298 299 /* attribute 300 */ 301 #define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */ 302 #define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */ 303 /* Snoop enable for all descriptor */ 304 #define CMD_HDR_ATTR_SNOOP 0x00000200 305 #define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */ 306 #define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */ 307 /* BIST - require the host to enter BIST mode */ 308 #define CMD_HDR_ATTR_BIST 0x00000040 309 #define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */ 310 #define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */ 311 312 #define FLAGS_DMA 0x00000000 313 #define FLAGS_FPDMA 0x00000001 314 315 #define SATA_FLAG_Q_DEP_MASK 0x0000000f 316 #define SATA_FLAG_WCACHE 0x00000100 317 #define SATA_FLAG_FLUSH 0x00000200 318 #define SATA_FLAG_FLUSH_EXT 0x00000400 319 320 #define READ_CMD 0 321 #define WRITE_CMD 1 322 323 #endif /* __DWC_AHSATA_H__ */ 324