1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2010-11-13 weety first version 9 */ 10 11 /* 12 * This EDMA3 programming framework exposes two basic kinds of resource: 13 * 14 * Channel Triggers transfers, usually from a hardware event but 15 * also manually or by "chaining" from DMA completions. 16 * Each channel is coupled to a Parameter RAM (PaRAM) slot. 17 * 18 * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM 19 * "set"), source and destination addresses, a link to a 20 * next PaRAM slot (if any), options for the transfer, and 21 * instructions for updating those addresses. There are 22 * more than twice as many slots as event channels. 23 * 24 * Each PaRAM set describes a sequence of transfers, either for one large 25 * buffer or for several discontiguous smaller buffers. An EDMA transfer 26 * is driven only from a channel, which performs the transfers specified 27 * in its PaRAM slot until there are no more transfers. When that last 28 * transfer completes, the "link" field may be used to reload the channel's 29 * PaRAM slot with a new transfer descriptor. 30 * 31 * The EDMA Channel Controller (CC) maps requests from channels into physical 32 * Transfer Controller (TC) requests when the channel triggers (by hardware 33 * or software events, or by chaining). The two physical DMA channels provided 34 * by the TCs are thus shared by many logical channels. 35 * 36 * DaVinci hardware also has a "QDMA" mechanism which is not currently 37 * supported through this interface. (DSP firmware uses it though.) 38 */ 39 40 #ifndef EDMA_H_ 41 #define EDMA_H_ 42 43 #include <rtthread.h> 44 #include <dm36x.h> 45 46 #ifdef RT_EDMA_DEBUG 47 #define edma_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__) 48 #else 49 #define edma_dbg(fmt, ...) 50 #endif 51 52 53 /* PaRAM slots are laid out like this */ 54 struct edmacc_param { 55 unsigned int opt; 56 unsigned int src; 57 unsigned int a_b_cnt; 58 unsigned int dst; 59 unsigned int src_dst_bidx; 60 unsigned int link_bcntrld; 61 unsigned int src_dst_cidx; 62 unsigned int ccnt; 63 }; 64 65 #define CCINT0_INTERRUPT 16 66 #define CCERRINT_INTERRUPT 17 67 #define TCERRINT0_INTERRUPT 18 68 #define TCERRINT1_INTERRUPT 19 69 70 /* fields in edmacc_param.opt */ 71 #define SAM BIT(0) 72 #define DAM BIT(1) 73 #define SYNCDIM BIT(2) 74 #define STATIC BIT(3) 75 #define EDMA_FWID (0x07 << 8) 76 #define TCCMODE BIT(11) 77 #define EDMA_TCC(t) ((t) << 12) 78 #define TCINTEN BIT(20) 79 #define ITCINTEN BIT(21) 80 #define TCCHEN BIT(22) 81 #define ITCCHEN BIT(23) 82 83 #define TRWORD (0x7<<2) 84 #define PAENTRY (0x1ff<<5) 85 86 /* DM365 specific EDMA3 Events Information */ 87 enum dm365_edma_ch { 88 DM365_DMA_TIMER3_TINT6, 89 DM365_DMA_TIMER3_TINT7, 90 DM365_DMA_MCBSP_TX = 2, 91 DM365_DMA_VCIF_TX = 2, 92 DM365_DMA_MCBSP_RX = 3, 93 DM365_DMA_VCIF_RX = 3, 94 DM365_DMA_VPSS_EVT1, 95 DM365_DMA_VPSS_EVT2, 96 DM365_DMA_VPSS_EVT3, 97 DM365_DMA_VPSS_EVT4, 98 DM365_DMA_TIMER2_TINT4, 99 DM365_DMA_TIMER2_TINT5, 100 DM365_DMA_SPI2XEVT, 101 DM365_DMA_SPI2REVT, 102 DM365_DMA_IMCOP_IMX0INT = 12, 103 DM365_DMA_KALEIDO_ARMINT = 12, 104 DM365_DMA_IMCOP_SEQINT, 105 DM365_DMA_SPI1XEVT, 106 DM365_DMA_SPI1REVT, 107 DM365_DMA_SPI0XEVT, 108 DM365_DMA_SPI0REVT, 109 DM365_DMA_URXEVT0 = 18, 110 DM365_DMA_SPI3XEVT = 18, 111 DM365_DMA_UTXEVT0 = 19, 112 DM365_DMA_SPI3REVT = 19, 113 DM365_DMA_URXEVT1, 114 DM365_DMA_UTXEVT1, 115 DM365_DMA_TIMER4_TINT8, 116 DM365_DMA_TIMER4_TINT9, 117 DM365_DMA_RTOINT, 118 DM365_DMA_GPIONT9, 119 DM365_DMA_MMC0RXEVT = 26, 120 DM365_DMA_MEMSTK_MSEVT = 26, 121 DM365_DMA_MMC0TXEVT, 122 DM365_DMA_I2C_ICREVT, 123 DM365_DMA_I2C_ICXEVT, 124 DM365_DMA_MMC1RXEVT, 125 DM365_DMA_MMC1TXEVT, 126 DM365_DMA_GPIOINT0, 127 DM365_DMA_GPIOINT1, 128 DM365_DMA_GPIOINT2, 129 DM365_DMA_GPIOINT3, 130 DM365_DMA_GPIOINT4, 131 DM365_DMA_GPIOINT5, 132 DM365_DMA_GPIOINT6, 133 DM365_DMA_GPIOINT7, 134 DM365_DMA_GPIOINT10 = 40, 135 DM365_DMA_EMAC_RXTHREESH = 40, 136 DM365_DMA_GPIOINT11 = 41, 137 DM365_DMA_EMAC_RXPULSE = 41, 138 DM365_DMA_GPIOINT12 = 42, 139 DM365_DMA_EMAC_TXPULSE = 42, 140 DM365_DMA_GPIOINT13 = 43, 141 DM365_DMA_EMAC_MISCPULSE = 43, 142 DM365_DMA_GPIOINT14 = 44, 143 DM365_DMA_SPI4XEVT = 44, 144 DM365_DMA_GPIOINT15 = 45, 145 DM365_DMA_SPI4REVT = 45, 146 DM365_DMA_ADC_ADINT, 147 DM365_DMA_GPIOINT8, 148 DM365_DMA_TIMER0_TINT0, 149 DM365_DMA_TIMER0_TINT1, 150 DM365_DMA_TIMER1_TINT2, 151 DM365_DMA_TIMER1_TINT3, 152 DM365_DMA_PWM0, 153 DM365_DMA_PWM1 = 53, 154 DM365_DMA_IMCOP_IMX1INT = 53, 155 DM365_DMA_PWM2 = 54, 156 DM365_DMA_IMCOP_NSFINT = 54, 157 DM365_DMA_PWM3 = 55, 158 DM365_DMA_KALEIDO6_CP_UNDEF = 55, 159 DM365_DMA_IMCOP_VLCDINT = 56, 160 DM365_DMA_KALEIDO5_CP_ECDCMP = 56, 161 DM365_DMA_IMCOP_BIMINT = 57, 162 DM365_DMA_KALEIDO8_CP_ME = 57, 163 DM365_DMA_IMCOP_DCTINT = 58, 164 DM365_DMA_KALEIDO1_CP_CALC = 58, 165 DM365_DMA_IMCOP_QIQINT = 59, 166 DM365_DMA_KALEIDO7_CP_IPE = 59, 167 DM365_DMA_IMCOP_BPSINT = 60, 168 DM365_DMA_KALEIDO2_CP_BS = 60, 169 DM365_DMA_IMCOP_VLCDERRINT = 61, 170 DM365_DMA_KALEIDO0_CP_LPF = 61, 171 DM365_DMA_IMCOP_RCNTINT = 62, 172 DM365_DMA_KALEIDO3_CP_MC = 62, 173 DM365_DMA_IMCOP_COPCINT = 63, 174 DM365_DMA_KALEIDO4_CP_ECDEND = 63, 175 }; 176 /* end DM365 specific info */ 177 178 179 /*ch_status paramater of callback function possible values*/ 180 #define DMA_COMPLETE 1 181 #define DMA_CC_ERROR 2 182 #define DMA_TC1_ERROR 3 183 #define DMA_TC2_ERROR 4 184 185 enum address_mode { 186 INCR = 0, 187 FIFO = 1 188 }; 189 190 enum fifo_width { 191 W8BIT = 0, 192 W16BIT = 1, 193 W32BIT = 2, 194 W64BIT = 3, 195 W128BIT = 4, 196 W256BIT = 5 197 }; 198 199 enum dma_event_q { 200 EVENTQ_0 = 0, 201 EVENTQ_1 = 1, 202 EVENTQ_2 = 2, 203 EVENTQ_3 = 3, 204 EVENTQ_DEFAULT = -1 205 }; 206 207 enum sync_dimension { 208 ASYNC = 0, 209 ABSYNC = 1 210 }; 211 212 #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) 213 #define EDMA_CTLR(i) ((i) >> 16) 214 #define EDMA_CHAN_SLOT(i) ((i) & 0xffff) 215 216 #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ 217 #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ 218 #define EDMA_CONT_PARAMS_ANY 1001 219 #define EDMA_CONT_PARAMS_FIXED_EXACT 1002 220 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 221 222 #define EDMA_MAX_CC 2 223 224 /* alloc/free DMA channels and their dedicated parameter RAM slots */ 225 int edma_alloc_channel(int channel, 226 void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), 227 void *data, enum dma_event_q); 228 void edma_free_channel(unsigned channel); 229 230 /* alloc/free parameter RAM slots */ 231 int edma_alloc_slot(unsigned ctlr, int slot); 232 void edma_free_slot(unsigned slot); 233 234 /* alloc/free a set of contiguous parameter RAM slots */ 235 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count); 236 int edma_free_cont_slots(unsigned slot, int count); 237 238 /* calls that operate on part of a parameter RAM slot */ 239 void edma_set_src(unsigned slot, rt_uint32_t src_port, 240 enum address_mode mode, enum fifo_width); 241 void edma_set_dest(unsigned slot, rt_uint32_t dest_port, 242 enum address_mode mode, enum fifo_width); 243 void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst); 244 void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx); 245 void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_cidx); 246 void edma_set_transfer_params(unsigned slot, rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt, 247 rt_uint16_t bcnt_rld, enum sync_dimension sync_mode); 248 void edma_link(unsigned from, unsigned to); 249 void edma_unlink(unsigned from); 250 251 /* calls that operate on an entire parameter RAM slot */ 252 void edma_write_slot(unsigned slot, const struct edmacc_param *params); 253 void edma_read_slot(unsigned slot, struct edmacc_param *params); 254 255 /* channel control operations */ 256 int edma_start(unsigned channel); 257 void edma_stop(unsigned channel); 258 void edma_clean_channel(unsigned channel); 259 void edma_clear_event(unsigned channel); 260 void edma_pause(unsigned channel); 261 void edma_resume(unsigned channel); 262 263 264 struct edma_rsv_info { 265 266 const rt_int16_t (*rsv_chans)[2]; 267 const rt_int16_t (*rsv_slots)[2]; 268 }; 269 270 /* platform_data for EDMA driver */ 271 struct edma_soc_info { 272 273 /* how many dma resources of each type */ 274 unsigned n_channel; 275 unsigned n_region; 276 unsigned n_slot; 277 unsigned n_tc; 278 unsigned n_cc; 279 enum dma_event_q default_queue; 280 281 /* Resource reservation for other cores */ 282 struct edma_rsv_info *rsv; 283 284 const rt_int8_t (*queue_tc_mapping)[2]; 285 const rt_int8_t (*queue_priority_mapping)[2]; 286 }; 287 288 int edma_init(struct edma_soc_info **info); 289 290 291 #endif 292