1 /**************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File 4 * for EFM EFM32GG980F512 5 * @author Energy Micro AS 6 * @version 3.0.0 7 ****************************************************************************** 8 * @section License 9 * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b> 10 ****************************************************************************** 11 * 12 * Permission is granted to anyone to use this software for any purpose, 13 * including commercial applications, and to alter it and redistribute it 14 * freely, subject to the following restrictions: 15 * 16 * 1. The origin of this software must not be misrepresented; you must not 17 * claim that you wrote the original software. 18 * 2. Altered source versions must be plainly marked as such, and must not be 19 * misrepresented as being the original software. 20 * 3. This notice may not be removed or altered from any source distribution. 21 * 22 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no 23 * obligation to support this Software. Energy Micro AS is providing the 24 * Software "AS IS", with no express or implied warranties of any kind, 25 * including, but not limited to, any implied warranties of merchantability 26 * or fitness for any particular purpose or warranties against infringement 27 * of any proprietary rights of a third party. 28 * 29 * Energy Micro AS will not be liable for any consequential, incidental, or 30 * special damages, or any other relief, or for any claim by any third party, 31 * arising from your use of this Software. 32 * 33 *****************************************************************************/ 34 35 #ifndef __EFM32GG980F512_H 36 #define __EFM32GG980F512_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /**************************************************************************//** 43 * @addtogroup Parts 44 * @{ 45 *****************************************************************************/ 46 47 /**************************************************************************//** 48 * @defgroup EFM32GG980F512 EFM32GG980F512 49 * @{ 50 *****************************************************************************/ 51 52 /** Interrupt Number Definition */ 53 typedef enum IRQn 54 { 55 /****** Cortex-M3 Processor Exceptions Numbers *******************************************/ 56 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 57 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ 58 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 59 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 60 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 61 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 62 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 63 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 64 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 65 66 /****** EFM32G Peripheral Interrupt Numbers **********************************************/ 67 DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */ 68 GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */ 69 TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */ 70 USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */ 71 USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */ 72 USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */ 73 ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */ 74 ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */ 75 DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */ 76 I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */ 77 I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */ 78 GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */ 79 TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */ 80 TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */ 81 TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */ 82 USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */ 83 USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */ 84 LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */ 85 USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */ 86 USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */ 87 UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */ 88 UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */ 89 UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */ 90 UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */ 91 LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */ 92 LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */ 93 LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */ 94 PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */ 95 PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */ 96 PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */ 97 RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */ 98 BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */ 99 CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ 100 VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */ 101 LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */ 102 MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */ 103 AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */ 104 EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */ 105 EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */ 106 } IRQn_Type; 107 108 /**************************************************************************//** 109 * @defgroup EFM32GG980F512_Core EFM32GG980F512 Core 110 * @{ 111 * @brief Processor and Core Peripheral Section 112 *****************************************************************************/ 113 #define __MPU_PRESENT 1 /**< Presence of MPU */ 114 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ 115 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ 116 117 /** @} End of group EFM32GG980F512_Core */ 118 119 /**************************************************************************//** 120 * @defgroup EFM32GG980F512_Part EFM32GG980F512 Part 121 * @{ 122 ******************************************************************************/ 123 124 /** Part family */ 125 #define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ 126 127 /* If part number is not defined as compiler option, define it */ 128 #if !defined(EFM32GG980F512) 129 #define EFM32GG980F512 1 /**< Giant/Leopard Gecko Part */ 130 #endif 131 132 /** Configure part number */ 133 #define PART_NUMBER "EFM32GG980F512" /**< Part Number */ 134 135 /** Memory Base addresses and limits */ 136 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */ 137 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */ 138 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */ 139 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */ 140 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */ 141 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */ 142 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */ 143 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */ 144 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */ 145 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */ 146 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */ 147 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */ 148 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ 149 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */ 150 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */ 151 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ 152 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ 153 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */ 154 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */ 155 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */ 156 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */ 157 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */ 158 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */ 159 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */ 160 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ 161 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */ 162 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */ 163 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */ 164 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */ 165 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ 166 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */ 167 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ 168 169 /** Bit banding area */ 170 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ 171 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ 172 173 /** Flash and SRAM limits for EFM32GG980F512 */ 174 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 175 #define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ 176 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 177 #define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ 178 #define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */ 179 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ 180 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */ 181 182 /* Part number capabilities */ 183 184 #define TIMER_PRESENT /**< TIMER is available in this part */ 185 #define TIMER_COUNT 4 /**< 4 TIMERs available */ 186 #define USART_PRESENT /**< USART is available in this part */ 187 #define USART_COUNT 3 /**< 3 USARTs available */ 188 #define UART_PRESENT /**< UART is available in this part */ 189 #define UART_COUNT 2 /**< 2 UARTs available */ 190 #define LEUART_PRESENT /**< LEUART is available in this part */ 191 #define LEUART_COUNT 2 /**< 2 LEUARTs available */ 192 #define LETIMER_PRESENT /**< LETIMER is available in this part */ 193 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */ 194 #define PCNT_PRESENT /**< PCNT is available in this part */ 195 #define PCNT_COUNT 3 /**< 3 PCNTs available */ 196 #define I2C_PRESENT /**< I2C is available in this part */ 197 #define I2C_COUNT 2 /**< 2 I2Cs available */ 198 #define ADC_PRESENT /**< ADC is available in this part */ 199 #define ADC_COUNT 1 /**< 1 ADCs available */ 200 #define DAC_PRESENT /**< DAC is available in this part */ 201 #define DAC_COUNT 1 /**< 1 DACs available */ 202 #define ACMP_PRESENT /**< ACMP is available in this part */ 203 #define ACMP_COUNT 2 /**< 2 ACMPs available */ 204 #define LE_PRESENT 205 #define LE_COUNT 1 206 #define MSC_PRESENT 207 #define MSC_COUNT 1 208 #define EMU_PRESENT 209 #define EMU_COUNT 1 210 #define RMU_PRESENT 211 #define RMU_COUNT 1 212 #define CMU_PRESENT 213 #define CMU_COUNT 1 214 #define AES_PRESENT 215 #define AES_COUNT 1 216 #define LESENSE_PRESENT 217 #define LESENSE_COUNT 1 218 #define EBI_PRESENT 219 #define EBI_COUNT 1 220 #define GPIO_PRESENT 221 #define GPIO_COUNT 1 222 #define PRS_PRESENT 223 #define PRS_COUNT 1 224 #define DMA_PRESENT 225 #define DMA_COUNT 1 226 #define OPAMP_PRESENT 227 #define OPAMP_COUNT 1 228 #define USB_PRESENT 229 #define USB_COUNT 1 230 #define USBC_PRESENT 231 #define USBC_COUNT 1 232 #define BU_PRESENT 233 #define BU_COUNT 1 234 #define VCMP_PRESENT 235 #define VCMP_COUNT 1 236 #define LCD_PRESENT 237 #define LCD_COUNT 1 238 #define RTC_PRESENT 239 #define RTC_COUNT 1 240 #define BURTC_PRESENT 241 #define BURTC_COUNT 1 242 #define HFXTAL_PRESENT 243 #define HFXTAL_COUNT 1 244 #define LFXTAL_PRESENT 245 #define LFXTAL_COUNT 1 246 #define WDOG_PRESENT 247 #define WDOG_COUNT 1 248 #define DBG_PRESENT 249 #define DBG_COUNT 1 250 #define ETM_PRESENT 251 #define ETM_COUNT 1 252 #define BOOTLOADER_PRESENT 253 #define BOOTLOADER_COUNT 1 254 255 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ 256 #include "system_efm32gg.h" /* System Header */ 257 258 /** @} End of group EFM32GG980F512_Part */ 259 260 /**************************************************************************//** 261 * @defgroup EFM32GG980F512_Peripheral_TypeDefs EFM32GG980F512 Peripheral TypeDefs 262 * @{ 263 * @brief Device Specific Peripheral Register Structures 264 *****************************************************************************/ 265 266 #include "efm32gg_msc.h" 267 #include "efm32gg_emu.h" 268 #include "efm32gg_rmu.h" 269 #include "efm32gg_cmu.h" 270 #include "efm32gg_aes.h" 271 #include "efm32gg_lesense_st.h" 272 #include "efm32gg_lesense_buf.h" 273 #include "efm32gg_lesense_ch.h" 274 #include "efm32gg_lesense.h" 275 #include "efm32gg_ebi.h" 276 #include "efm32gg_gpio_p.h" 277 #include "efm32gg_gpio.h" 278 #include "efm32gg_prs_ch.h" 279 #include "efm32gg_prs.h" 280 #include "efm32gg_dma_ch.h" 281 #include "efm32gg_dma.h" 282 #include "efm32gg_timer_cc.h" 283 #include "efm32gg_timer.h" 284 #include "efm32gg_usart.h" 285 #include "efm32gg_leuart.h" 286 #include "efm32gg_letimer.h" 287 #include "efm32gg_pcnt.h" 288 #include "efm32gg_i2c.h" 289 #include "efm32gg_adc.h" 290 #include "efm32gg_dac.h" 291 #include "efm32gg_acmp.h" 292 #include "efm32gg_usb_hc.h" 293 #include "efm32gg_usb_diep.h" 294 #include "efm32gg_usb_doep.h" 295 #include "efm32gg_usb.h" 296 #include "efm32gg_vcmp.h" 297 #include "efm32gg_lcd.h" 298 #include "efm32gg_rtc.h" 299 #include "efm32gg_burtc_ret.h" 300 #include "efm32gg_burtc.h" 301 #include "efm32gg_wdog.h" 302 #include "efm32gg_etm.h" 303 #include "efm32gg_dma_descriptor.h" 304 #include "efm32gg_devinfo.h" 305 #include "efm32gg_romtable.h" 306 #include "efm32gg_calibrate.h" 307 308 /** @} End of group EFM32GG980F512_Peripheral_TypeDefs */ 309 310 /**************************************************************************//** 311 * @defgroup EFM32GG980F512_Peripheral_Base EFM32GG980F512 Peripheral Memory Map 312 * @{ 313 *****************************************************************************/ 314 315 #define MSC_BASE (0x400C0000UL) /**< MSC base address */ 316 #define EMU_BASE (0x400C6000UL) /**< EMU base address */ 317 #define RMU_BASE (0x400CA000UL) /**< RMU base address */ 318 #define CMU_BASE (0x400C8000UL) /**< CMU base address */ 319 #define AES_BASE (0x400E0000UL) /**< AES base address */ 320 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */ 321 #define EBI_BASE (0x40008000UL) /**< EBI base address */ 322 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ 323 #define PRS_BASE (0x400CC000UL) /**< PRS base address */ 324 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ 325 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */ 326 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */ 327 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */ 328 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */ 329 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */ 330 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */ 331 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */ 332 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */ 333 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */ 334 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */ 335 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */ 336 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */ 337 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */ 338 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */ 339 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */ 340 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */ 341 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */ 342 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ 343 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */ 344 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */ 345 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */ 346 #define USB_BASE (0x400C4000UL) /**< USB base address */ 347 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */ 348 #define LCD_BASE (0x4008A000UL) /**< LCD base address */ 349 #define RTC_BASE (0x40080000UL) /**< RTC base address */ 350 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */ 351 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */ 352 #define ETM_BASE (0xE0041000UL) /**< ETM base address */ 353 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */ 354 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ 355 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ 356 357 /** @} End of group EFM32GG980F512_Peripheral_Base */ 358 359 /**************************************************************************//** 360 * @defgroup EFM32GG980F512_Peripheral_Declaration EFM32GG980F512 Peripheral Declarations 361 * @{ 362 *****************************************************************************/ 363 364 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 365 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 366 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ 367 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 368 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */ 369 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ 370 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ 371 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 372 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 373 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */ 374 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 375 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 376 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 377 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ 378 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 379 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 380 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ 381 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ 382 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ 383 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ 384 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ 385 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 386 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 387 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ 388 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ 389 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 390 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ 391 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ 392 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */ 393 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 394 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ 395 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ 396 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */ 397 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ 398 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ 399 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ 400 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */ 401 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ 402 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */ 403 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 404 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ 405 406 /** @} End of group EFM32GG980F512_Peripheral_Declaration */ 407 408 /**************************************************************************//** 409 * @defgroup EFM32GG980F512_BitFields EFM32GG980F512 Bit Fields 410 * @{ 411 *****************************************************************************/ 412 413 #include "efm32gg_prs_signals.h" 414 #include "efm32gg_dmareq.h" 415 #include "efm32gg_dmactrl.h" 416 #include "efm32gg_uart.h" 417 418 /**************************************************************************//** 419 * @defgroup EFM32GG980F512_UNLOCK Unlock Codes 420 * @{ 421 *****************************************************************************/ 422 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ 423 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ 424 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ 425 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ 426 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ 427 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */ 428 429 /** @} End of group EFM32GG980F512_UNLOCK */ 430 431 /** @} End of group EFM32GG980F512_BitFields */ 432 433 /**************************************************************************//** 434 * @defgroup EFM32GG980F512_Alternate_Function EFM32GG980F512 Alternate Function 435 * @{ 436 *****************************************************************************/ 437 438 #include "efm32gg_af_channels.h" 439 #include "efm32gg_af_ports.h" 440 #include "efm32gg_af_pins.h" 441 442 /** @} End of group EFM32GG980F512_Alternate_Function */ 443 444 /**************************************************************************//** 445 * @brief Set the value of a bit field within a register. 446 * 447 * @param REG 448 * The register to update 449 * @param MASK 450 * The mask for the bit field to update 451 * @param VALUE 452 * The value to write to the bit field 453 * @param OFFSET 454 * The number of bits that the field is offset within the register. 455 * 0 (zero) means LSB. 456 *****************************************************************************/ 457 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ 458 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); 459 460 /** @} End of group EFM32GG980F512 */ 461 462 /** @} End of group Parts */ 463 464 #ifdef __cplusplus 465 } 466 #endif 467 468 #endif /* __EFM32GG980F512_H */ 469