1 /**************************************************************************//** 2 * @file 3 * @brief efm32gg_dmactrl Register and Bit Field definitions 4 * @author Energy Micro AS 5 * @version 3.0.0 6 ****************************************************************************** 7 * @section License 8 * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b> 9 ****************************************************************************** 10 * 11 * Permission is granted to anyone to use this software for any purpose, 12 * including commercial applications, and to alter it and redistribute it 13 * freely, subject to the following restrictions: 14 * 15 * 1. The origin of this software must not be misrepresented; you must not 16 * claim that you wrote the original software. 17 * 2. Altered source versions must be plainly marked as such, and must not be 18 * misrepresented as being the original software. 19 * 3. This notice may not be removed or altered from any source distribution. 20 * 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no 22 * obligation to support this Software. Energy Micro AS is providing the 23 * Software "AS IS", with no express or implied warranties of any kind, 24 * including, but not limited to, any implied warranties of merchantability 25 * or fitness for any particular purpose or warranties against infringement 26 * of any proprietary rights of a third party. 27 * 28 * Energy Micro AS will not be liable for any consequential, incidental, or 29 * special damages, or any other relief, or for any claim by any third party, 30 * arising from your use of this Software. 31 * 32 *****************************************************************************/ 33 34 /**************************************************************************//** 35 * @defgroup EFM32GG_DMACTRL_BitFields 36 * @{ 37 *****************************************************************************/ 38 #define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */ 39 #define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */ 40 #define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */ 41 #define _DMA_CTRL_DST_INC_HALFWORD 0x01 /**< Half word/16-bit increment */ 42 #define _DMA_CTRL_DST_INC_WORD 0x02 /**< Word/32-bit increment */ 43 #define _DMA_CTRL_DST_INC_NONE 0x03 /**< No increment */ 44 #define DMA_CTRL_DST_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */ 45 #define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL /**< Half word/16-bit increment */ 46 #define DMA_CTRL_DST_INC_WORD 0x80000000UL /**< Word/32-bit increment */ 47 #define DMA_CTRL_DST_INC_NONE 0xC0000000UL /**< No increment */ 48 #define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL /**< Data size for destination - MUST be the same as source, bit mask */ 49 #define _DMA_CTRL_DST_SIZE_SHIFT 28 /**< Data size for destination - MUST be the same as source, shift value */ 50 #define _DMA_CTRL_DST_SIZE_BYTE 0x00 /**< Byte/8-bit data size */ 51 #define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */ 52 #define _DMA_CTRL_DST_SIZE_WORD 0x02 /**< Word/32-bit data size */ 53 #define _DMA_CTRL_DST_SIZE_RSVD 0x03 /**< Reserved */ 54 #define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */ 55 #define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL /**< Half word/16-bit data size */ 56 #define DMA_CTRL_DST_SIZE_WORD 0x20000000UL /**< Word/32-bit data size */ 57 #define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL /**< Reserved - do not use */ 58 #define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL /**< Data increment for source, bit mask */ 59 #define _DMA_CTRL_SRC_INC_SHIFT 26 /**< Data increment for source, shift value */ 60 #define _DMA_CTRL_SRC_INC_BYTE 0x00 /**< Byte/8-bit increment */ 61 #define _DMA_CTRL_SRC_INC_HALFWORD 0x01 /**< Half word/16-bit increment */ 62 #define _DMA_CTRL_SRC_INC_WORD 0x02 /**< Word/32-bit increment */ 63 #define _DMA_CTRL_SRC_INC_NONE 0x03 /**< No increment */ 64 #define DMA_CTRL_SRC_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */ 65 #define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL /**< Half word/16-bit increment */ 66 #define DMA_CTRL_SRC_INC_WORD 0x08000000UL /**< Word/32-bit increment */ 67 #define DMA_CTRL_SRC_INC_NONE 0x0C000000UL /**< No increment */ 68 #define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL /**< Data size for source - MUST be the same as destination, bit mask */ 69 #define _DMA_CTRL_SRC_SIZE_SHIFT 24 /**< Data size for source - MUST be the same as destination, shift value */ 70 #define _DMA_CTRL_SRC_SIZE_BYTE 0x00 /**< Byte/8-bit data size */ 71 #define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */ 72 #define _DMA_CTRL_SRC_SIZE_WORD 0x02 /**< Word/32-bit data size */ 73 #define _DMA_CTRL_SRC_SIZE_RSVD 0x03 /**< Reserved */ 74 #define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */ 75 #define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL /**< Half word/16-bit data size */ 76 #define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL /**< Word/32-bit data size */ 77 #define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL /**< Reserved - do not use */ 78 #define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL /**< Protection flag for destination, bit mask */ 79 #define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 /**< Protection flag for destination, shift value */ 80 #define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL /**< Privileged mode for destination */ 81 #define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */ 82 #define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL /**< Protection flag for source, bit mask */ 83 #define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 /**< Protection flag for source, shift value */ 84 #define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL /**< Privileged mode for destination */ 85 #define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */ 86 #define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 /**< Protection bits to indicate non-privileged access */ 87 #define _DMA_CTRL_PROT_PRIVILEGED 0x01 /**< Protection bits to indicate privileged access */ 88 #define _DMA_CTRL_R_POWER_MASK 0x0003C000UL /**< DMA arbitration mask */ 89 #define _DMA_CTRL_R_POWER_SHIFT 14 /**< Number of DMA cycles before controller does new arbitration in 2^R */ 90 #define _DMA_CTRL_R_POWER_1 0x00 /**< Arbitrate after each transfer */ 91 #define _DMA_CTRL_R_POWER_2 0x01 /**< Arbitrate after every 2 transfers */ 92 #define _DMA_CTRL_R_POWER_4 0x02 /**< Arbitrate after every 4 transfers */ 93 #define _DMA_CTRL_R_POWER_8 0x03 /**< Arbitrate after every 8 transfers */ 94 #define _DMA_CTRL_R_POWER_16 0x04 /**< Arbitrate after every 16 transfers */ 95 #define _DMA_CTRL_R_POWER_32 0x05 /**< Arbitrate after every 32 transfers */ 96 #define _DMA_CTRL_R_POWER_64 0x06 /**< Arbitrate after every 64 transfers */ 97 #define _DMA_CTRL_R_POWER_128 0x07 /**< Arbitrate after every 128 transfers */ 98 #define _DMA_CTRL_R_POWER_256 0x08 /**< Arbitrate after every 256 transfers */ 99 #define _DMA_CTRL_R_POWER_512 0x09 /**< Arbitrate after every 512 transfers */ 100 #define _DMA_CTRL_R_POWER_1024 0x0a /**< Arbitrate after every 1024 transfers */ 101 #define DMA_CTRL_R_POWER_1 0x00000000UL /**< Arbitrate after each transfer */ 102 #define DMA_CTRL_R_POWER_2 0x00004000UL /**< Arbitrate after every 2 transfers */ 103 #define DMA_CTRL_R_POWER_4 0x00008000UL /**< Arbitrate after every 4 transfers */ 104 #define DMA_CTRL_R_POWER_8 0x0000c000UL /**< Arbitrate after every 8 transfers */ 105 #define DMA_CTRL_R_POWER_16 0x00010000UL /**< Arbitrate after every 16 transfers */ 106 #define DMA_CTRL_R_POWER_32 0x00014000UL /**< Arbitrate after every 32 transfers */ 107 #define DMA_CTRL_R_POWER_64 0x00018000UL /**< Arbitrate after every 64 transfers */ 108 #define DMA_CTRL_R_POWER_128 0x0001c000UL /**< Arbitrate after every 128 transfers */ 109 #define DMA_CTRL_R_POWER_256 0x00020000UL /**< Arbitrate after every 256 transfers */ 110 #define DMA_CTRL_R_POWER_512 0x00024000UL /**< Arbitrate after every 512 transfers */ 111 #define DMA_CTRL_R_POWER_1024 0x00028000UL /**< Arbitrate after every 1024 transfers */ 112 #define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */ 113 #define _DMA_CTRL_N_MINUS_1_SHIFT 4 /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */ 114 #define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */ 115 #define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 /**< DMA useburst shift */ 116 #define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */ 117 #define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 /**< DMA Cycle control bit shift */ 118 #define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 /**< Invalid cycle type */ 119 #define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 /**< Basic cycle type */ 120 #define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 /**< Auto cycle type */ 121 #define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 /**< PingPong cycle type */ 122 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 /**< Memory scatter gather cycle type */ 123 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 /**< Memory scatter gather using alternate structure */ 124 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 /**< Peripheral scatter gather cycle type */ 125 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 /**< Peripheral scatter gather cycle type using alternate structure */ 126 #define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL /**< Invalid cycle type */ 127 #define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL /**< Basic cycle type */ 128 #define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL /**< Auto cycle type */ 129 #define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL /**< PingPong cycle type */ 130 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL /**< Memory scatter gather cycle type */ 131 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL /**< Memory scatter gather using alternate structure */ 132 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /**< Peripheral scatter gather cycle type */ 133 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */ 134 135 /** @} End of group EFM32GG_DMA */ 136 137 138