1 /**************************************************************************//** 2 * @file 3 * @brief efm32gg_msc Register and Bit Field definitions 4 * @author Energy Micro AS 5 * @version 3.0.0 6 ****************************************************************************** 7 * @section License 8 * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b> 9 ****************************************************************************** 10 * 11 * Permission is granted to anyone to use this software for any purpose, 12 * including commercial applications, and to alter it and redistribute it 13 * freely, subject to the following restrictions: 14 * 15 * 1. The origin of this software must not be misrepresented; you must not 16 * claim that you wrote the original software. 17 * 2. Altered source versions must be plainly marked as such, and must not be 18 * misrepresented as being the original software. 19 * 3. This notice may not be removed or altered from any source distribution. 20 * 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no 22 * obligation to support this Software. Energy Micro AS is providing the 23 * Software "AS IS", with no express or implied warranties of any kind, 24 * including, but not limited to, any implied warranties of merchantability 25 * or fitness for any particular purpose or warranties against infringement 26 * of any proprietary rights of a third party. 27 * 28 * Energy Micro AS will not be liable for any consequential, incidental, or 29 * special damages, or any other relief, or for any claim by any third party, 30 * arising from your use of this Software. 31 * 32 *****************************************************************************/ 33 /**************************************************************************//** 34 * @defgroup EFM32GG_MSC 35 * @{ 36 * @brief EFM32GG_MSC Register Declaration 37 *****************************************************************************/ 38 typedef struct 39 { 40 __IO uint32_t CTRL; /**< Memory System Control Register */ 41 __IO uint32_t READCTRL; /**< Read Control Register */ 42 __IO uint32_t WRITECTRL; /**< Write Control Register */ 43 __IO uint32_t WRITECMD; /**< Write Command Register */ 44 __IO uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ 45 46 uint32_t RESERVED0[1]; /**< Reserved for future use **/ 47 __IO uint32_t WDATA; /**< Write Data Register */ 48 __I uint32_t STATUS; /**< Status Register */ 49 50 uint32_t RESERVED1[3]; /**< Reserved for future use **/ 51 __I uint32_t IF; /**< Interrupt Flag Register */ 52 __IO uint32_t IFS; /**< Interrupt Flag Set Register */ 53 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ 54 __IO uint32_t IEN; /**< Interrupt Enable Register */ 55 __IO uint32_t LOCK; /**< Configuration Lock Register */ 56 __IO uint32_t CMD; /**< Command Register */ 57 __I uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ 58 __I uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ 59 uint32_t RESERVED2[1]; /**< Reserved for future use **/ 60 __IO uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */ 61 __IO uint32_t MASSLOCK; /**< Mass Erase Lock Register */ 62 } MSC_TypeDef; /** @} */ 63 64 /**************************************************************************//** 65 * @defgroup EFM32GG_MSC_BitFields 66 * @{ 67 *****************************************************************************/ 68 69 /* Bit fields for MSC CTRL */ 70 #define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */ 71 #define _MSC_CTRL_MASK 0x00000001UL /**< Mask for MSC_CTRL */ 72 #define MSC_CTRL_BUSFAULT (0x1UL << 0) /**< Bus Fault Response Enable */ 73 #define _MSC_CTRL_BUSFAULT_SHIFT 0 /**< Shift value for MSC_BUSFAULT */ 74 #define _MSC_CTRL_BUSFAULT_MASK 0x1UL /**< Bit mask for MSC_BUSFAULT */ 75 #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL /**< Mode GENERATE for MSC_CTRL */ 76 #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ 77 #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL /**< Mode IGNORE for MSC_CTRL */ 78 #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) /**< Shifted mode GENERATE for MSC_CTRL */ 79 #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ 80 #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) /**< Shifted mode IGNORE for MSC_CTRL */ 81 82 /* Bit fields for MSC READCTRL */ 83 #define _MSC_READCTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_READCTRL */ 84 #define _MSC_READCTRL_MASK 0x000301FFUL /**< Mask for MSC_READCTRL */ 85 #define _MSC_READCTRL_MODE_SHIFT 0 /**< Shift value for MSC_MODE */ 86 #define _MSC_READCTRL_MODE_MASK 0x7UL /**< Bit mask for MSC_MODE */ 87 #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ 88 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ 89 #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ 90 #define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL /**< Mode WS0SCBTP for MSC_READCTRL */ 91 #define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL /**< Mode WS1SCBTP for MSC_READCTRL */ 92 #define _MSC_READCTRL_MODE_WS2 0x00000004UL /**< Mode WS2 for MSC_READCTRL */ 93 #define _MSC_READCTRL_MODE_WS2SCBTP 0x00000005UL /**< Mode WS2SCBTP for MSC_READCTRL */ 94 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) /**< Shifted mode WS0 for MSC_READCTRL */ 95 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_READCTRL */ 96 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) /**< Shifted mode WS1 for MSC_READCTRL */ 97 #define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0) /**< Shifted mode WS0SCBTP for MSC_READCTRL */ 98 #define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0) /**< Shifted mode WS1SCBTP for MSC_READCTRL */ 99 #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 0) /**< Shifted mode WS2 for MSC_READCTRL */ 100 #define MSC_READCTRL_MODE_WS2SCBTP (_MSC_READCTRL_MODE_WS2SCBTP << 0) /**< Shifted mode WS2SCBTP for MSC_READCTRL */ 101 #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ 102 #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ 103 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ 104 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 105 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ 106 #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ 107 #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ 108 #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ 109 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 110 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ 111 #define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ 112 #define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ 113 #define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ 114 #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 115 #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ 116 #define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ 117 #define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ 118 #define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ 119 #define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 120 #define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ 121 #define MSC_READCTRL_RAMCEN (0x1UL << 7) /**< RAM Cache Enable */ 122 #define _MSC_READCTRL_RAMCEN_SHIFT 7 /**< Shift value for MSC_RAMCEN */ 123 #define _MSC_READCTRL_RAMCEN_MASK 0x80UL /**< Bit mask for MSC_RAMCEN */ 124 #define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 125 #define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_READCTRL */ 126 #define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ 127 #define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ 128 #define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ 129 #define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 130 #define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ 131 #define _MSC_READCTRL_BUSSTRATEGY_SHIFT 16 /**< Shift value for MSC_BUSSTRATEGY */ 132 #define _MSC_READCTRL_BUSSTRATEGY_MASK 0x30000UL /**< Bit mask for MSC_BUSSTRATEGY */ 133 #define _MSC_READCTRL_BUSSTRATEGY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 134 #define _MSC_READCTRL_BUSSTRATEGY_CPU 0x00000000UL /**< Mode CPU for MSC_READCTRL */ 135 #define _MSC_READCTRL_BUSSTRATEGY_DMA 0x00000001UL /**< Mode DMA for MSC_READCTRL */ 136 #define _MSC_READCTRL_BUSSTRATEGY_DMAEM1 0x00000002UL /**< Mode DMAEM1 for MSC_READCTRL */ 137 #define _MSC_READCTRL_BUSSTRATEGY_NONE 0x00000003UL /**< Mode NONE for MSC_READCTRL */ 138 #define MSC_READCTRL_BUSSTRATEGY_DEFAULT (_MSC_READCTRL_BUSSTRATEGY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_READCTRL */ 139 #define MSC_READCTRL_BUSSTRATEGY_CPU (_MSC_READCTRL_BUSSTRATEGY_CPU << 16) /**< Shifted mode CPU for MSC_READCTRL */ 140 #define MSC_READCTRL_BUSSTRATEGY_DMA (_MSC_READCTRL_BUSSTRATEGY_DMA << 16) /**< Shifted mode DMA for MSC_READCTRL */ 141 #define MSC_READCTRL_BUSSTRATEGY_DMAEM1 (_MSC_READCTRL_BUSSTRATEGY_DMAEM1 << 16) /**< Shifted mode DMAEM1 for MSC_READCTRL */ 142 #define MSC_READCTRL_BUSSTRATEGY_NONE (_MSC_READCTRL_BUSSTRATEGY_NONE << 16) /**< Shifted mode NONE for MSC_READCTRL */ 143 144 /* Bit fields for MSC WRITECTRL */ 145 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ 146 #define _MSC_WRITECTRL_MASK 0x0000003FUL /**< Mask for MSC_WRITECTRL */ 147 #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ 148 #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ 149 #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ 150 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 151 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 152 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ 153 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ 154 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ 155 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 156 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 157 #define MSC_WRITECTRL_WDOUBLE (0x1UL << 2) /**< Write two words at a time */ 158 #define _MSC_WRITECTRL_WDOUBLE_SHIFT 2 /**< Shift value for MSC_WDOUBLE */ 159 #define _MSC_WRITECTRL_WDOUBLE_MASK 0x4UL /**< Bit mask for MSC_WDOUBLE */ 160 #define _MSC_WRITECTRL_WDOUBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 161 #define MSC_WRITECTRL_WDOUBLE_DEFAULT (_MSC_WRITECTRL_WDOUBLE_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 162 #define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Erase */ 163 #define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ 164 #define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ 165 #define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 166 #define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 167 #define MSC_WRITECTRL_LPERASE (0x1UL << 4) /**< Low-Power Erase */ 168 #define _MSC_WRITECTRL_LPERASE_SHIFT 4 /**< Shift value for MSC_LPERASE */ 169 #define _MSC_WRITECTRL_LPERASE_MASK 0x10UL /**< Bit mask for MSC_LPERASE */ 170 #define _MSC_WRITECTRL_LPERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 171 #define MSC_WRITECTRL_LPERASE_DEFAULT (_MSC_WRITECTRL_LPERASE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 172 #define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ 173 #define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ 174 #define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ 175 #define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 176 #define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 177 178 /* Bit fields for MSC WRITECMD */ 179 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ 180 #define _MSC_WRITECMD_MASK 0x0000933FUL /**< Mask for MSC_WRITECMD */ 181 #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */ 182 #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ 183 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ 184 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 185 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 186 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ 187 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ 188 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ 189 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 190 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 191 #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ 192 #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ 193 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ 194 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 195 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 196 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ 197 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ 198 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ 199 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 200 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 201 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ 202 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ 203 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ 204 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 205 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 206 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ 207 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ 208 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ 209 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 210 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 211 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ 212 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ 213 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ 214 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 215 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 216 #define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass erase region 1 */ 217 #define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ 218 #define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ 219 #define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 220 #define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 221 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ 222 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ 223 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ 224 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 225 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 226 227 /* Bit fields for MSC ADDRB */ 228 #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ 229 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ 230 #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ 231 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ 232 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ 233 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ 234 235 /* Bit fields for MSC WDATA */ 236 #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ 237 #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ 238 #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ 239 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ 240 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ 241 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ 242 243 /* Bit fields for MSC STATUS */ 244 #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ 245 #define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */ 246 #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ 247 #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ 248 #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ 249 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 250 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ 251 #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ 252 #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ 253 #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ 254 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 255 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ 256 #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ 257 #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ 258 #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ 259 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 260 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ 261 #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ 262 #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ 263 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ 264 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ 265 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ 266 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ 267 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ 268 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ 269 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 270 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ 271 #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ 272 #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ 273 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ 274 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 275 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ 276 #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ 277 #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ 278 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ 279 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 280 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ 281 282 /* Bit fields for MSC IF */ 283 #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ 284 #define _MSC_IF_MASK 0x0000000FUL /**< Mask for MSC_IF */ 285 #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ 286 #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 287 #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 288 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 289 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ 290 #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ 291 #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 292 #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 293 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 294 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ 295 #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ 296 #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 297 #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 298 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 299 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ 300 #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ 301 #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 302 #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 303 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 304 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ 305 306 /* Bit fields for MSC IFS */ 307 #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ 308 #define _MSC_IFS_MASK 0x0000000FUL /**< Mask for MSC_IFS */ 309 #define MSC_IFS_ERASE (0x1UL << 0) /**< Erase Done Interrupt Set */ 310 #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 311 #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 312 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 313 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ 314 #define MSC_IFS_WRITE (0x1UL << 1) /**< Write Done Interrupt Set */ 315 #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 316 #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 317 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 318 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ 319 #define MSC_IFS_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Set */ 320 #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 321 #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 322 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 323 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ 324 #define MSC_IFS_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Set */ 325 #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 326 #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 327 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 328 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ 329 330 /* Bit fields for MSC IFC */ 331 #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ 332 #define _MSC_IFC_MASK 0x0000000FUL /**< Mask for MSC_IFC */ 333 #define MSC_IFC_ERASE (0x1UL << 0) /**< Erase Done Interrupt Clear */ 334 #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 335 #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 336 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 337 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ 338 #define MSC_IFC_WRITE (0x1UL << 1) /**< Write Done Interrupt Clear */ 339 #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 340 #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 341 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 342 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ 343 #define MSC_IFC_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Clear */ 344 #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 345 #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 346 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 347 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ 348 #define MSC_IFC_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Clear */ 349 #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 350 #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 351 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 352 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ 353 354 /* Bit fields for MSC IEN */ 355 #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ 356 #define _MSC_IEN_MASK 0x0000000FUL /**< Mask for MSC_IEN */ 357 #define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt Enable */ 358 #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 359 #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 360 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 361 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ 362 #define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt Enable */ 363 #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 364 #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 365 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 366 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ 367 #define MSC_IEN_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Enable */ 368 #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 369 #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 370 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 371 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ 372 #define MSC_IEN_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Enable */ 373 #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 374 #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 375 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 376 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ 377 378 /* Bit fields for MSC LOCK */ 379 #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ 380 #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ 381 #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ 382 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ 383 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ 384 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ 385 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ 386 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ 387 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ 388 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ 389 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ 390 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ 391 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ 392 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ 393 394 /* Bit fields for MSC CMD */ 395 #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ 396 #define _MSC_CMD_MASK 0x00000007UL /**< Mask for MSC_CMD */ 397 #define MSC_CMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ 398 #define _MSC_CMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ 399 #define _MSC_CMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ 400 #define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ 401 #define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ 402 #define MSC_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ 403 #define _MSC_CMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ 404 #define _MSC_CMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ 405 #define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ 406 #define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ 407 #define MSC_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ 408 #define _MSC_CMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ 409 #define _MSC_CMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ 410 #define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ 411 #define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CMD */ 412 413 /* Bit fields for MSC CACHEHITS */ 414 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ 415 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ 416 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ 417 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ 418 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ 419 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ 420 421 /* Bit fields for MSC CACHEMISSES */ 422 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ 423 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ 424 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ 425 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ 426 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ 427 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ 428 429 /* Bit fields for MSC TIMEBASE */ 430 #define _MSC_TIMEBASE_RESETVALUE 0x00000010UL /**< Default value for MSC_TIMEBASE */ 431 #define _MSC_TIMEBASE_MASK 0x0001003FUL /**< Mask for MSC_TIMEBASE */ 432 #define _MSC_TIMEBASE_BASE_SHIFT 0 /**< Shift value for MSC_BASE */ 433 #define _MSC_TIMEBASE_BASE_MASK 0x3FUL /**< Bit mask for MSC_BASE */ 434 #define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_TIMEBASE */ 435 #define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_TIMEBASE */ 436 #define MSC_TIMEBASE_PERIOD (0x1UL << 16) /**< Sets the timebase period */ 437 #define _MSC_TIMEBASE_PERIOD_SHIFT 16 /**< Shift value for MSC_PERIOD */ 438 #define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL /**< Bit mask for MSC_PERIOD */ 439 #define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_TIMEBASE */ 440 #define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL /**< Mode 1US for MSC_TIMEBASE */ 441 #define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL /**< Mode 5US for MSC_TIMEBASE */ 442 #define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_TIMEBASE */ 443 #define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16) /**< Shifted mode 1US for MSC_TIMEBASE */ 444 #define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16) /**< Shifted mode 5US for MSC_TIMEBASE */ 445 446 /* Bit fields for MSC MASSLOCK */ 447 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ 448 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ 449 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ 450 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ 451 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ 452 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ 453 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ 454 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ 455 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ 456 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ 457 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ 458 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ 459 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ 460 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ 461 462 /** @} End of group EFM32GG_MSC */ 463 464 465