1 /***************************************************************************//**
2 * @file
3 * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
4 * peripheral API
5 * @author Energy Micro AS
6 * @version 3.0.0
7 *******************************************************************************
8 * @section License
9 * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
10 *******************************************************************************
11 *
12 * Permission is granted to anyone to use this software for any purpose,
13 * including commercial applications, and to alter it and redistribute it
14 * freely, subject to the following restrictions:
15 *
16 * 1. The origin of this software must not be misrepresented; you must not
17 * claim that you wrote the original software.
18 * 2. Altered source versions must be plainly marked as such, and must not be
19 * misrepresented as being the original software.
20 * 3. This notice may not be removed or altered from any source distribution.
21 *
22 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
23 * obligation to support this Software. Energy Micro AS is providing the
24 * Software "AS IS", with no express or implied warranties of any kind,
25 * including, but not limited to, any implied warranties of merchantability
26 * or fitness for any particular purpose or warranties against infringement
27 * of any proprietary rights of a third party.
28 *
29 * Energy Micro AS will not be liable for any consequential, incidental, or
30 * special damages, or any other relief, or for any claim by any third party,
31 * arising from your use of this Software.
32 *
33 ******************************************************************************/
34 #ifndef __EM_USART_H
35 #define __EM_USART_H
36
37 #include <stdbool.h>
38 #include "em_part.h"
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /***************************************************************************//**
45 * @addtogroup EM_Library
46 * @{
47 ******************************************************************************/
48
49 /***************************************************************************//**
50 * @addtogroup USART
51 * @brief Universal Synchronous/Asynchronous Receiver/Transmitter (USART) peripheral API
52 * @{
53 ******************************************************************************/
54
55 /*******************************************************************************
56 ******************************** ENUMS ************************************
57 ******************************************************************************/
58
59 /** Databit selection. */
60 typedef enum
61 {
62 usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 databits (not available for UART). */
63 usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 databits (not available for UART). */
64 usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 databits (not available for UART). */
65 usartDatabits7 = USART_FRAME_DATABITS_SEVEN, /**< 7 databits (not available for UART). */
66 usartDatabits8 = USART_FRAME_DATABITS_EIGHT, /**< 8 databits. */
67 usartDatabits9 = USART_FRAME_DATABITS_NINE, /**< 9 databits. */
68 usartDatabits10 = USART_FRAME_DATABITS_TEN, /**< 10 databits (not available for UART). */
69 usartDatabits11 = USART_FRAME_DATABITS_ELEVEN, /**< 11 databits (not available for UART). */
70 usartDatabits12 = USART_FRAME_DATABITS_TWELVE, /**< 12 databits (not available for UART). */
71 usartDatabits13 = USART_FRAME_DATABITS_THIRTEEN, /**< 13 databits (not available for UART). */
72 usartDatabits14 = USART_FRAME_DATABITS_FOURTEEN, /**< 14 databits (not available for UART). */
73 usartDatabits15 = USART_FRAME_DATABITS_FIFTEEN, /**< 15 databits (not available for UART). */
74 usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 databits (not available for UART). */
75 } USART_Databits_TypeDef;
76
77
78 /** Enable selection. */
79 typedef enum
80 {
81 /** Disable both receiver and transmitter. */
82 usartDisable = 0x0,
83
84 /** Enable receiver only, transmitter disabled. */
85 usartEnableRx = USART_CMD_RXEN,
86
87 /** Enable transmitter only, receiver disabled. */
88 usartEnableTx = USART_CMD_TXEN,
89
90 /** Enable both receiver and transmitter. */
91 usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN)
92 } USART_Enable_TypeDef;
93
94
95 /** Oversampling selection, used for asynchronous operation. */
96 typedef enum
97 {
98 usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */
99 usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */
100 usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */
101 usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */
102 } USART_OVS_TypeDef;
103
104
105 /** Parity selection, mainly used for asynchronous operation. */
106 typedef enum
107 {
108 usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */
109 usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */
110 usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */
111 } USART_Parity_TypeDef;
112
113
114 /** Stopbits selection, used for asynchronous operation. */
115 typedef enum
116 {
117 usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stopbits. */
118 usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stopbits. */
119 usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stopbits. */
120 usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stopbits. */
121 } USART_Stopbits_TypeDef;
122
123
124 /** Clock polarity/phase mode. */
125 typedef enum
126 {
127 /** Clock idle low, sample on rising edge. */
128 usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING,
129
130 /** Clock idle low, sample on falling edge. */
131 usartClockMode1 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLETRAILING,
132
133 /** Clock idle high, sample on falling edge. */
134 usartClockMode2 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLELEADING,
135
136 /** Clock idle high, sample on rising edge. */
137 usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING
138 } USART_ClockMode_TypeDef;
139
140
141 /** Pulse width selection for IrDA mode. */
142 typedef enum
143 {
144 /** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */
145 usartIrDAPwONE = USART_IRCTRL_IRPW_ONE,
146
147 /** IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 */
148 usartIrDAPwTWO = USART_IRCTRL_IRPW_TWO,
149
150 /** IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 */
151 usartIrDAPwTHREE = USART_IRCTRL_IRPW_THREE,
152
153 /** IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 */
154 usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR
155 } USART_IrDAPw_Typedef;
156
157
158 /** PRS channel selection for IrDA mode. */
159 typedef enum
160 {
161 usartIrDAPrsCh0 = USART_IRCTRL_IRPRSSEL_PRSCH0, /**< PRS channel 0 */
162 usartIrDAPrsCh1 = USART_IRCTRL_IRPRSSEL_PRSCH1, /**< PRS channel 1 */
163 usartIrDAPrsCh2 = USART_IRCTRL_IRPRSSEL_PRSCH2, /**< PRS channel 2 */
164 usartIrDAPrsCh3 = USART_IRCTRL_IRPRSSEL_PRSCH3, /**< PRS channel 3 */
165 usartIrDAPrsCh4 = USART_IRCTRL_IRPRSSEL_PRSCH4, /**< PRS channel 4 */
166 usartIrDAPrsCh5 = USART_IRCTRL_IRPRSSEL_PRSCH5, /**< PRS channel 5 */
167 usartIrDAPrsCh6 = USART_IRCTRL_IRPRSSEL_PRSCH6, /**< PRS channel 6 */
168 usartIrDAPrsCh7 = USART_IRCTRL_IRPRSSEL_PRSCH7 /**< PRS channel 7 */
169 } USART_IrDAPrsSel_Typedef;
170
171 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_TINY_FAMILY)
172 /** I2S format selection. */
173 typedef enum
174 {
175 usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data */
176 usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */
177 usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data */
178 usartI2sFormatW32D16 = USART_I2SCTRL_FORMAT_W32D16, /**< 32-bit word, 16-bit data */
179 usartI2sFormatW32D8 = USART_I2SCTRL_FORMAT_W32D8, /**< 32-bit word, 8-bit data */
180 usartI2sFormatW16D16 = USART_I2SCTRL_FORMAT_W16D16, /**< 16-bit word, 16-bit data */
181 usartI2sFormatW16D8 = USART_I2SCTRL_FORMAT_W16D8, /**< 16-bit word, 8-bit data */
182 usartI2sFormatW8D8 = USART_I2SCTRL_FORMAT_W8D8 /**< 8-bit word, 8-bit data */
183 } USART_I2sFormat_TypeDef;
184
185 /** I2S frame data justify. */
186 typedef enum
187 {
188 usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame */
189 usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame */
190 } USART_I2sJustify_TypeDef;
191
192 /** USART Rx input PRS selection. */
193 typedef enum
194 {
195 usartPrsRxCh0 = USART_INPUT_RXPRSSEL_PRSCH0, /**< PRSCH0 selected as USART_INPUT */
196 usartPrsRxCh1 = USART_INPUT_RXPRSSEL_PRSCH1, /**< PRSCH1 selected as USART_INPUT */
197 usartPrsRxCh2 = USART_INPUT_RXPRSSEL_PRSCH2, /**< PRSCH2 selected as USART_INPUT */
198 usartPrsRxCh3 = USART_INPUT_RXPRSSEL_PRSCH3, /**< PRSCH3 selected as USART_INPUT */
199 usartPrsRxCh4 = USART_INPUT_RXPRSSEL_PRSCH4, /**< PRSCH4 selected as USART_INPUT */
200 usartPrsRxCh5 = USART_INPUT_RXPRSSEL_PRSCH5, /**< PRSCH5 selected as USART_INPUT */
201 usartPrsRxCh6 = USART_INPUT_RXPRSSEL_PRSCH6, /**< PRSCH6 selected as USART_INPUT */
202
203 #if defined(_EFM32_TINY_FAMILY)
204 usartPrsRxCh7 = USART_INPUT_RXPRSSEL_PRSCH7 /**< PRSCH7 selected as USART_INPUT */
205
206 #elif defined(_EFM32_GIANT_FAMILY)
207 usartPrsRxCh7 = USART_INPUT_RXPRSSEL_PRSCH7, /**< PRSCH7 selected as USART_INPUT */
208 usartPrsRxCh8 = USART_INPUT_RXPRSSEL_PRSCH8, /**< PRSCH8 selected as USART_INPUT */
209 usartPrsRxCh9 = USART_INPUT_RXPRSSEL_PRSCH9, /**< PRSCH9 selected as USART_INPUT */
210 usartPrsRxCh10 = USART_INPUT_RXPRSSEL_PRSCH10, /**< PRSCH10 selected as USART_INPUT */
211 usartPrsRxCh11 = USART_INPUT_RXPRSSEL_PRSCH11 /**< PRSCH11 selected as USART_INPUT */
212 #else
213 #error Unknown EFM32 family.
214 #endif
215 } USART_PrsRxCh_TypeDef;
216 #endif
217
218 #if defined (_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
219 /** USART PRS Transmit Trigger Channels */
220 typedef enum
221 {
222 usartPrsTriggerCh0 = USART_TRIGCTRL_TSEL_PRSCH0, /**< PRSCH0 selected as USART Trigger */
223 usartPrsTriggerCh1 = USART_TRIGCTRL_TSEL_PRSCH1, /**< PRSCH0 selected as USART Trigger */
224 usartPrsTriggerCh2 = USART_TRIGCTRL_TSEL_PRSCH2, /**< PRSCH0 selected as USART Trigger */
225 usartPrsTriggerCh3 = USART_TRIGCTRL_TSEL_PRSCH3, /**< PRSCH0 selected as USART Trigger */
226 usartPrsTriggerCh4 = USART_TRIGCTRL_TSEL_PRSCH4, /**< PRSCH0 selected as USART Trigger */
227 usartPrsTriggerCh5 = USART_TRIGCTRL_TSEL_PRSCH5, /**< PRSCH0 selected as USART Trigger */
228 usartPrsTriggerCh6 = USART_TRIGCTRL_TSEL_PRSCH6, /**< PRSCH0 selected as USART Trigger */
229 usartPrsTriggerCh7 = USART_TRIGCTRL_TSEL_PRSCH7, /**< PRSCH0 selected as USART Trigger */
230 } USART_PrsTriggerCh_TypeDef;
231 #endif
232
233 /*******************************************************************************
234 ******************************* STRUCTS ***********************************
235 ******************************************************************************/
236
237 /** Asynchronous mode init structure. */
238 typedef struct
239 {
240 /** Specifies whether TX and/or RX shall be enabled when init completed. */
241 USART_Enable_TypeDef enable;
242
243 /**
244 * USART/UART reference clock assumed when configuring baudrate setup. Set
245 * it to 0 if currently configurated reference clock shall be used.
246 */
247 uint32_t refFreq;
248
249 /** Desired baudrate. */
250 uint32_t baudrate;
251
252 /** Oversampling used. */
253 USART_OVS_TypeDef oversampling;
254
255 /** Number of databits in frame. Notice that UART modules only support 8 or
256 * 9 databits. */
257 USART_Databits_TypeDef databits;
258
259 /** Parity mode to use. */
260 USART_Parity_TypeDef parity;
261
262 /** Number of stopbits to use. */
263 USART_Stopbits_TypeDef stopbits;
264
265 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_TINY_FAMILY)
266 /** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */
267 bool mvdis;
268
269 /** Enable USART Rx via PRS. */
270 bool prsRxEnable;
271
272 /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */
273 USART_PrsRxCh_TypeDef prsRxCh;
274 #endif
275 } USART_InitAsync_TypeDef;
276
277 #if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
278 /** USART PRS trigger enable */
279 typedef struct
280 {
281 #if defined(_EFM32_GIANT_FAMILY)
282 /** Enable AUTOTX */
283 bool autoTxTriggerEnable;
284 #endif
285 /** Trigger receive via PRS channel */
286 bool rxTriggerEnable;
287 /** Trigger transmit via PRS channel */
288 bool txTriggerEnable;
289 /** PRS channel to be used to trigger auto transmission */
290 USART_PrsTriggerCh_TypeDef prsTriggerChannel;
291 } USART_PrsTriggerInit_TypeDef;
292 #endif
293
294 /** Default config for USART async init structure. */
295 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_TINY_FAMILY)
296 #define USART_INITASYNC_DEFAULT \
297 { usartEnable, /* Enable RX/TX when init completed. */ \
298 0, /* Use current configured reference clock for configuring baudrate. */ \
299 115200, /* 115200 bits/s. */ \
300 usartOVS16, /* 16x oversampling. */ \
301 usartDatabits8, /* 8 databits. */ \
302 usartNoParity, /* No parity. */ \
303 usartStopbits1, /* 1 stopbit. */ \
304 false, /* Do not disable majority vote. */ \
305 false, /* Not USART PRS input mode. */ \
306 usartPrsRxCh0 /* PRS channel 0. */ \
307 }
308 #else
309 #define USART_INITASYNC_DEFAULT \
310 { usartEnable, /* Enable RX/TX when init completed. */ \
311 0, /* Use current configured reference clock for configuring baudrate. */ \
312 115200, /* 115200 bits/s. */ \
313 usartOVS16, /* 16x oversampling. */ \
314 usartDatabits8, /* 8 databits. */ \
315 usartNoParity, /* No parity. */ \
316 usartStopbits1 /* 1 stopbit. */ \
317 }
318 #endif
319
320 /** Synchronous mode init structure. */
321 typedef struct
322 {
323 /** Specifies whether TX and/or RX shall be enabled when init completed. */
324 USART_Enable_TypeDef enable;
325
326 /**
327 * USART/UART reference clock assumed when configuring baudrate setup. Set
328 * it to 0 if currently configurated reference clock shall be used.
329 */
330 uint32_t refFreq;
331
332 /** Desired baudrate. */
333 uint32_t baudrate;
334
335 /** Number of databits in frame. */
336 USART_Databits_TypeDef databits;
337
338 /** Select if to operate in master or slave mode. */
339 bool master;
340
341 /** Select if to send most or least significant bit first. */
342 bool msbf;
343
344 /** Clock polarity/phase mode. */
345 USART_ClockMode_TypeDef clockMode;
346
347 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_TINY_FAMILY)
348 /** Enable USART Rx via PRS. */
349 bool prsRxEnable;
350
351 /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */
352 USART_PrsRxCh_TypeDef prsRxCh;
353
354 /** Enable AUTOTX mode. Transmits as long as RX is not full.
355 * If TX is empty, underflows are generated. */
356 bool autoTx;
357 #endif
358 } USART_InitSync_TypeDef;
359
360 /** Default config for USART sync init structure. */
361 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_TINY_FAMILY)
362 #define USART_INITSYNC_DEFAULT \
363 { usartEnable, /* Enable RX/TX when init completed. */ \
364 0, /* Use current configured reference clock for configuring baudrate. */ \
365 1000000, /* 1 Mbits/s. */ \
366 usartDatabits8, /* 8 databits. */ \
367 true, /* Master mode. */ \
368 false, /* Send least significant bit first. */ \
369 usartClockMode0, /* Clock idle low, sample on rising edge. */ \
370 false, /* Not USART PRS input mode. */ \
371 usartPrsRxCh0, /* PRS channel 0. */ \
372 false /* No AUTOTX mode. */ \
373 }
374 #else
375 #define USART_INITSYNC_DEFAULT \
376 { usartEnable, /* Enable RX/TX when init completed. */ \
377 0, /* Use current configured reference clock for configuring baudrate. */ \
378 1000000, /* 1 Mbits/s. */ \
379 usartDatabits8, /* 8 databits. */ \
380 true, /* Master mode. */ \
381 false, /* Send least significant bit first. */ \
382 usartClockMode0 /* Clock idle low, sample on rising edge. */ \
383 }
384 #endif
385
386
387 /** IrDA mode init structure. Inherited from asynchronous mode init structure */
388 typedef struct
389 {
390 /** General Async initialization structure. */
391 USART_InitAsync_TypeDef async;
392
393 /** Set to invert Rx signal before IrDA demodulator. */
394 bool irRxInv;
395
396 /** Set to enable filter on IrDA demodulator. */
397 bool irFilt;
398
399 /** Configure the pulse width generated by the IrDA modulator as a fraction
400 * of the configured USART bit period. */
401 USART_IrDAPw_Typedef irPw;
402
403 /** Enable the PRS channel selected by irPrsSel as input to IrDA module
404 * instead of TX. */
405 bool irPrsEn;
406
407 /** A PRS can be used as input to the pulse modulator instead of TX.
408 * This value selects the channel to use. */
409 USART_IrDAPrsSel_Typedef irPrsSel;
410 } USART_InitIrDA_TypeDef;
411
412
413 /** Default config for IrDA mode init structure. */
414 #define USART_INITIRDA_DEFAULT \
415 { \
416 { usartEnable, /* Enable RX/TX when init completed. */ \
417 0, /* Use current configured reference clock for configuring baudrate. */ \
418 115200, /* 115200 bits/s. */ \
419 usartOVS16, /* 16x oversampling. */ \
420 usartDatabits8, /* 8 databits. */ \
421 usartEvenParity, /* Even parity. */ \
422 usartStopbits1 /* 1 stopbit. */ \
423 }, \
424 false, /* Rx invert disabled. */ \
425 false, /* Filtering disabled. */ \
426 usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
427 false, /* Routing to PRS is disabled. */ \
428 usartIrDAPrsCh0 /* PRS channel 0. */ \
429 }
430
431
432 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_TINY_FAMILY)
433 /** I2S mode init structure. Inherited from synchronous mode init structure */
434 typedef struct
435 {
436 /** General Sync initialization structure. */
437 USART_InitSync_TypeDef sync;
438
439 /** I2S mode. */
440 USART_I2sFormat_TypeDef format;
441
442 /** Delay on I2S data. Set to add a one-cycle delay between a transition
443 * on the word-clock and the start of the I2S word.
444 * Should be set for standard I2S format. */
445 bool delay;
446
447 /** Separate DMA Request For Left/Right Data. */
448 bool dmaSplit;
449
450 /** Justification of I2S data within the frame */
451 USART_I2sJustify_TypeDef justify;
452
453 /** Stero or Mono, set to true for mono. */
454 bool mono;
455 } USART_InitI2s_TypeDef;
456
457
458 /** Default config for I2S mode init structure. */
459 #define USART_INITI2S_DEFAULT \
460 { \
461 { usartEnableTx, /* Enable TX when init completed. */ \
462 0, /* Use current configured reference clock for configuring baudrate. */ \
463 1000000, /* Baudrate 1M bits/s. */ \
464 usartDatabits16, /* 16 databits. */ \
465 true, /* Operate as I2S master. */ \
466 true, /* Most significant bit first. */ \
467 usartClockMode0, /* Clock idle low, sample on rising edge. */ \
468 false, /* Don't enable USARTRx via PRS. */ \
469 usartPrsRxCh0, /* PRS channel selection (dummy). */ \
470 false /* Disable AUTOTX mode. */ \
471 }, \
472 usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
473 true, /* Delay on I2S data. */ \
474 false, /* No DMA split. */ \
475 usartI2sJustifyLeft, /* Data is left-justified within the frame */ \
476 false /* Stereo mode. */ \
477 }
478 #endif
479
480 /*******************************************************************************
481 ***************************** PROTOTYPES **********************************
482 ******************************************************************************/
483
484 void USART_BaudrateAsyncSet(USART_TypeDef *usart,
485 uint32_t refFreq,
486 uint32_t baudrate,
487 USART_OVS_TypeDef ovs);
488 uint32_t USART_BaudrateCalc(uint32_t refFreq,
489 uint32_t clkdiv,
490 bool syncmode,
491 USART_OVS_TypeDef ovs);
492 uint32_t USART_BaudrateGet(USART_TypeDef *usart);
493 void USART_BaudrateSyncSet(USART_TypeDef *usart,
494 uint32_t refFreq,
495 uint32_t baudrate);
496 void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable);
497
498 void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init);
499 void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init);
500 void USART_InitIrDA(const USART_InitIrDA_TypeDef *init);
501
502 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_TINY_FAMILY)
503 void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init);
504 void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init);
505 #endif
506
507
508 /***************************************************************************//**
509 * @brief
510 * Clear one or more pending USART interrupts.
511 *
512 * @param[in] usart
513 * Pointer to USART/UART peripheral register block.
514 *
515 * @param[in] flags
516 * Pending USART/UART interrupt source(s) to clear. Use one or more valid
517 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
518 ******************************************************************************/
USART_IntClear(USART_TypeDef * usart,uint32_t flags)519 __STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags)
520 {
521 usart->IFC = flags;
522 }
523
524
525 /***************************************************************************//**
526 * @brief
527 * Disable one or more USART interrupts.
528 *
529 * @param[in] usart
530 * Pointer to USART/UART peripheral register block.
531 *
532 * @param[in] flags
533 * USART/UART interrupt source(s) to disable. Use one or more valid
534 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
535 ******************************************************************************/
USART_IntDisable(USART_TypeDef * usart,uint32_t flags)536 __STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags)
537 {
538 usart->IEN &= ~(flags);
539 }
540
541
542 /***************************************************************************//**
543 * @brief
544 * Enable one or more USART interrupts.
545 *
546 * @note
547 * Depending on the use, a pending interrupt may already be set prior to
548 * enabling the interrupt. Consider using USART_IntClear() prior to enabling
549 * if such a pending interrupt should be ignored.
550 *
551 * @param[in] usart
552 * Pointer to USART/UART peripheral register block.
553 *
554 * @param[in] flags
555 * USART/UART interrupt source(s) to enable. Use one or more valid
556 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
557 ******************************************************************************/
USART_IntEnable(USART_TypeDef * usart,uint32_t flags)558 __STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags)
559 {
560 usart->IEN |= flags;
561 }
562
563
564 /***************************************************************************//**
565 * @brief
566 * Get pending USART interrupt flags.
567 *
568 * @note
569 * The event bits are not cleared by the use of this function.
570 *
571 * @param[in] usart
572 * Pointer to USART/UART peripheral register block.
573 *
574 * @return
575 * USART/UART interrupt source(s) pending. Returns one or more valid
576 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
577 ******************************************************************************/
USART_IntGet(USART_TypeDef * usart)578 __STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart)
579 {
580 return usart->IF;
581 }
582
583
584 /***************************************************************************//**
585 * @brief
586 * Get enabled and pending USART interrupt flags.
587 * Useful for handling more interrupt sources in the same interrupt handler.
588 *
589 * @param[in] usart
590 * Pointer to USART/UART peripheral register block.
591 *
592 * @note
593 * Interrupt flags are not cleared by the use of this function.
594 *
595 * @return
596 * Pending and enabled USART interrupt sources.
597 * The return value is the bitwise AND combination of
598 * - the OR combination of enabled interrupt sources in USARTx_IEN_nnn
599 * register (USARTx_IEN_nnn) and
600 * - the OR combination of valid interrupt flags of the USART module
601 * (USARTx_IF_nnn).
602 ******************************************************************************/
USART_IntGetEnabled(USART_TypeDef * usart)603 __STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart)
604 {
605 uint32_t tmp;
606
607 /* Store USARTx->IEN in temporary variable in order to define explicit order
608 * of volatile accesses. */
609 tmp = usart->IEN;
610
611 /* Bitwise AND of pending and enabled interrupts */
612 return usart->IF & tmp;
613 }
614
615
616 /***************************************************************************//**
617 * @brief
618 * Set one or more pending USART interrupts from SW.
619 *
620 * @param[in] usart
621 * Pointer to USART/UART peripheral register block.
622 *
623 * @param[in] flags
624 * USART/UART interrupt source(s) to set to pending. Use one or more valid
625 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
626 ******************************************************************************/
USART_IntSet(USART_TypeDef * usart,uint32_t flags)627 __STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags)
628 {
629 usart->IFS = flags;
630 }
631
632 void USART_Reset(USART_TypeDef *usart);
633 uint8_t USART_Rx(USART_TypeDef *usart);
634 uint16_t USART_RxDouble(USART_TypeDef *usart);
635 uint32_t USART_RxDoubleExt(USART_TypeDef *usart);
636 uint16_t USART_RxExt(USART_TypeDef *usart);
637 void USART_Tx(USART_TypeDef *usart, uint8_t data);
638 void USART_TxDouble(USART_TypeDef *usart, uint16_t data);
639 void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data);
640 void USART_TxExt(USART_TypeDef *usart, uint16_t data);
641
642
643 /** @} (end addtogroup USART) */
644 /** @} (end addtogroup EM_Library) */
645
646 #ifdef __cplusplus
647 }
648 #endif
649
650 #endif /* __EM_USART_H */
651