1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: esai_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for esai module.
esai_iomux_config(void)34 void esai_iomux_config(void)
35 {
36 // Config esai.ESAI_RX_CLK to pad ENET_MDIO(V23)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR(0x00000002);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR(0x0001B0B0);
39 // HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_WR(0x00000000);
40 // Mux Register:
41 // IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO(0x020E01EC)
42 // SION [4] - Software Input On Field Reset: DISABLED
43 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
44 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
45 // ENABLED (1) - Force input path of pad.
46 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
47 // Select iomux modes to be used for pad.
48 // ALT1 (1) - Select instance: enet signal: ENET_MDIO
49 // ALT2 (2) - Select instance: esai signal: ESAI_RX_CLK
50 // ALT4 (4) - Select instance: enet signal: ENET_1588_EVENT1_OUT
51 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO22
52 // ALT6 (6) - Select instance: spdif signal: SPDIF_LOCK
53 HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR(
54 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION_V(DISABLED) |
55 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE_V(ALT2));
56 // Pad Control Register:
57 // IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO(0x020E05BC)
58 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
59 // DISABLED (0) - CMOS input
60 // ENABLED (1) - Schmitt trigger input
61 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
62 // 100K_OHM_PD (0) - 100K Ohm Pull Down
63 // 47K_OHM_PU (1) - 47K Ohm Pull Up
64 // 100K_OHM_PU (2) - 100K Ohm Pull Up
65 // 22K_OHM_PU (3) - 22K Ohm Pull Up
66 // PUE [13] - Pull / Keep Select Field Reset: PULL
67 // KEEP (0) - Keeper Enabled
68 // PULL (1) - Pull Enabled
69 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
70 // DISABLED (0) - Pull/Keeper Disabled
71 // ENABLED (1) - Pull/Keeper Enabled
72 // ODE [11] - Open Drain Enable Field Reset: DISABLED
73 // Enables open drain of the pin.
74 // DISABLED (0) - Output is CMOS.
75 // ENABLED (1) - Output is Open Drain.
76 // SPEED [7:6] - Speed Field Reset: 100MHZ
77 // RESERVED0 (0) - Reserved
78 // 50MHZ (1) - Low (50 MHz)
79 // 100MHZ (2) - Medium (100 MHz)
80 // 200MHZ (3) - Maximum (200 MHz)
81 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
82 // HIZ (0) - HI-Z
83 // 240_OHM (1) - 240 Ohm
84 // 120_OHM (2) - 120 Ohm
85 // 80_OHM (3) - 80 Ohm
86 // 60_OHM (4) - 60 Ohm
87 // 48_OHM (5) - 48 Ohm
88 // 40_OHM (6) - 40 Ohm
89 // 34_OHM (7) - 34 Ohm
90 // SRE [0] - Slew Rate Field Reset: SLOW
91 // Slew rate control.
92 // SLOW (0) - Slow Slew Rate
93 // FAST (1) - Fast Slew Rate
94 HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR(
95 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS_V(ENABLED) |
96 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS_V(100K_OHM_PU) |
97 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE_V(PULL) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE_V(ENABLED) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE_V(DISABLED) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED_V(100MHZ) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE_V(40_OHM) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE_V(SLOW));
103 // Pad ENET_MDIO is involved in Daisy Chain.
104 // Input Select Register:
105 // IOMUXC_ESAI_RX_CLK_SELECT_INPUT(0x020E083C)
106 // DAISY [0] - MUX Mode Select Field Reset: ENET_MDIO_ALT2
107 // Selecting Pads Involved in Daisy Chain.
108 // ENET_MDIO_ALT2 (0) - Select signal esai ESAI_RX_CLK as input from pad ENET_MDIO(ALT2).
109 // GPIO01_ALT0 (1) - Select signal esai ESAI_RX_CLK as input from pad GPIO01(ALT0).
110 HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_WR(
111 BF_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY_V(ENET_MDIO_ALT2));
112
113 // Config esai.ESAI_RX_FS to pad GPIO09(T2)
114 // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_WR(0x00000000);
115 // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR(0x0001B0B0);
116 // HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_WR(0x00000001);
117 // Mux Register:
118 // IOMUXC_SW_MUX_CTL_PAD_GPIO09(0x020E0240)
119 // SION [4] - Software Input On Field Reset: DISABLED
120 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
121 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
122 // ENABLED (1) - Force input path of pad.
123 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
124 // Select iomux modes to be used for pad.
125 // ALT0 (0) - Select instance: esai signal: ESAI_RX_FS
126 // ALT1 (1) - Select instance: wdog1 signal: WDOG1_B
127 // ALT2 (2) - Select instance: kpp signal: KEY_COL6
128 // ALT3 (3) - Select instance: ccm signal: CCM_REF_EN_B
129 // ALT4 (4) - Select instance: pwm1 signal: PWM1_OUT
130 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO09
131 // ALT6 (6) - Select instance: usdhc1 signal: SD1_WP
132 HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_WR(
133 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION_V(DISABLED) |
134 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE_V(ALT0));
135 // Pad Control Register:
136 // IOMUXC_SW_PAD_CTL_PAD_GPIO09(0x020E0610)
137 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
138 // DISABLED (0) - CMOS input
139 // ENABLED (1) - Schmitt trigger input
140 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
141 // 100K_OHM_PD (0) - 100K Ohm Pull Down
142 // 47K_OHM_PU (1) - 47K Ohm Pull Up
143 // 100K_OHM_PU (2) - 100K Ohm Pull Up
144 // 22K_OHM_PU (3) - 22K Ohm Pull Up
145 // PUE [13] - Pull / Keep Select Field Reset: PULL
146 // KEEP (0) - Keeper Enabled
147 // PULL (1) - Pull Enabled
148 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
149 // DISABLED (0) - Pull/Keeper Disabled
150 // ENABLED (1) - Pull/Keeper Enabled
151 // ODE [11] - Open Drain Enable Field Reset: DISABLED
152 // Enables open drain of the pin.
153 // DISABLED (0) - Output is CMOS.
154 // ENABLED (1) - Output is Open Drain.
155 // SPEED [7:6] - Speed Field Reset: 100MHZ
156 // RESERVED0 (0) - Reserved
157 // 50MHZ (1) - Low (50 MHz)
158 // 100MHZ (2) - Medium (100 MHz)
159 // 200MHZ (3) - Maximum (200 MHz)
160 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
161 // HIZ (0) - HI-Z
162 // 240_OHM (1) - 240 Ohm
163 // 120_OHM (2) - 120 Ohm
164 // 80_OHM (3) - 80 Ohm
165 // 60_OHM (4) - 60 Ohm
166 // 48_OHM (5) - 48 Ohm
167 // 40_OHM (6) - 40 Ohm
168 // 34_OHM (7) - 34 Ohm
169 // SRE [0] - Slew Rate Field Reset: SLOW
170 // Slew rate control.
171 // SLOW (0) - Slow Slew Rate
172 // FAST (1) - Fast Slew Rate
173 HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR(
174 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS_V(ENABLED) |
175 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS_V(100K_OHM_PU) |
176 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE_V(PULL) |
177 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE_V(ENABLED) |
178 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE_V(DISABLED) |
179 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED_V(100MHZ) |
180 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE_V(40_OHM) |
181 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE_V(SLOW));
182 // Pad GPIO09 is involved in Daisy Chain.
183 // Input Select Register:
184 // IOMUXC_ESAI_RX_FS_SELECT_INPUT(0x020E082C)
185 // DAISY [0] - MUX Mode Select Field Reset: ENET_REF_CLK_ALT2
186 // Selecting Pads Involved in Daisy Chain.
187 // ENET_REF_CLK_ALT2 (0) - Select signal esai ESAI_RX_FS as input from pad ENET_REF_CLK(ALT2).
188 // GPIO09_ALT0 (1) - Select signal esai ESAI_RX_FS as input from pad GPIO09(ALT0).
189 HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_WR(
190 BF_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY_V(GPIO09_ALT0));
191
192 // Config esai.ESAI_TX0 to pad GPIO17(R1)
193 // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR(0x00000000);
194 // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR(0x0001B0B0);
195 // HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_WR(0x00000000);
196 // Mux Register:
197 // IOMUXC_SW_MUX_CTL_PAD_GPIO17(0x020E0218)
198 // SION [4] - Software Input On Field Reset: DISABLED
199 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
200 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
201 // ENABLED (1) - Force input path of pad.
202 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
203 // Select iomux modes to be used for pad.
204 // ALT0 (0) - Select instance: esai signal: ESAI_TX0
205 // ALT1 (1) - Select instance: enet signal: ENET_1588_EVENT3_IN
206 // ALT2 (2) - Select instance: ccm signal: CCM_PMIC_READY
207 // ALT3 (3) - Select instance: sdma signal: SDMA_EXT_EVENT0
208 // ALT4 (4) - Select instance: spdif signal: SPDIF_OUT
209 // ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO12
210 HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR(
211 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION_V(DISABLED) |
212 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE_V(ALT0));
213 // Pad Control Register:
214 // IOMUXC_SW_PAD_CTL_PAD_GPIO17(0x020E05E8)
215 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
216 // DISABLED (0) - CMOS input
217 // ENABLED (1) - Schmitt trigger input
218 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
219 // 100K_OHM_PD (0) - 100K Ohm Pull Down
220 // 47K_OHM_PU (1) - 47K Ohm Pull Up
221 // 100K_OHM_PU (2) - 100K Ohm Pull Up
222 // 22K_OHM_PU (3) - 22K Ohm Pull Up
223 // PUE [13] - Pull / Keep Select Field Reset: PULL
224 // KEEP (0) - Keeper Enabled
225 // PULL (1) - Pull Enabled
226 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
227 // DISABLED (0) - Pull/Keeper Disabled
228 // ENABLED (1) - Pull/Keeper Enabled
229 // ODE [11] - Open Drain Enable Field Reset: DISABLED
230 // Enables open drain of the pin.
231 // DISABLED (0) - Output is CMOS.
232 // ENABLED (1) - Output is Open Drain.
233 // SPEED [7:6] - Speed Field Reset: 100MHZ
234 // NOTE: Read Only Field
235 // The value of this field is fixed and cannot be changed.
236 // RESERVED0 (0) - Reserved
237 // 50MHZ (1) - Low (50 MHz)
238 // 100MHZ (2) - Medium (100 MHz)
239 // 200MHZ (3) - Maximum (200 MHz)
240 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
241 // HIZ (0) - HI-Z
242 // 240_OHM (1) - 240 Ohm
243 // 120_OHM (2) - 120 Ohm
244 // 80_OHM (3) - 80 Ohm
245 // 60_OHM (4) - 60 Ohm
246 // 48_OHM (5) - 48 Ohm
247 // 40_OHM (6) - 40 Ohm
248 // 34_OHM (7) - 34 Ohm
249 // SRE [0] - Slew Rate Field Reset: SLOW
250 // Slew rate control.
251 // SLOW (0) - Slow Slew Rate
252 // FAST (1) - Fast Slew Rate
253 HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR(
254 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS_V(ENABLED) |
255 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS_V(100K_OHM_PU) |
256 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE_V(PULL) |
257 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE_V(ENABLED) |
258 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE_V(DISABLED) |
259 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE_V(40_OHM) |
260 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE_V(SLOW));
261 // Pad GPIO17 is involved in Daisy Chain.
262 // Input Select Register:
263 // IOMUXC_ESAI_SDO0_SELECT_INPUT(0x020E0844)
264 // DAISY [0] - MUX Mode Select Field Reset: GPIO17_ALT0
265 // Selecting Pads Involved in Daisy Chain.
266 // GPIO17_ALT0 (0) - Select signal esai ESAI_TX0 as input from pad GPIO17(ALT0).
267 // NAND_CS2_B_ALT2 (1) - Select signal esai ESAI_TX0 as input from pad NAND_CS2_B(ALT2).
268 HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_WR(
269 BF_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY_V(GPIO17_ALT0));
270
271 // Config esai.ESAI_TX1 to pad NAND_CS3_B(D16)
272 // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_WR(0x00000002);
273 // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR(0x0001B0B0);
274 // HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_WR(0x00000001);
275 // Mux Register:
276 // IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B(0x020E0280)
277 // SION [4] - Software Input On Field Reset: DISABLED
278 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
279 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
280 // ENABLED (1) - Force input path of pad.
281 // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
282 // Select iomux modes to be used for pad.
283 // ALT0 (0) - Select instance: gpmi signal: NAND_CE3_B
284 // ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG1
285 // ALT2 (2) - Select instance: esai signal: ESAI_TX1
286 // ALT3 (3) - Select instance: eim signal: EIM_ADDR26
287 // ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO16
288 // ALT9 (9) - Select instance: i2c4 signal: I2C4_SDA
289 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_WR(
290 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION_V(DISABLED) |
291 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE_V(ALT2));
292 // Pad Control Register:
293 // IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B(0x020E0668)
294 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
295 // DISABLED (0) - CMOS input
296 // ENABLED (1) - Schmitt trigger input
297 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
298 // 100K_OHM_PD (0) - 100K Ohm Pull Down
299 // 47K_OHM_PU (1) - 47K Ohm Pull Up
300 // 100K_OHM_PU (2) - 100K Ohm Pull Up
301 // 22K_OHM_PU (3) - 22K Ohm Pull Up
302 // PUE [13] - Pull / Keep Select Field Reset: PULL
303 // KEEP (0) - Keeper Enabled
304 // PULL (1) - Pull Enabled
305 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
306 // DISABLED (0) - Pull/Keeper Disabled
307 // ENABLED (1) - Pull/Keeper Enabled
308 // ODE [11] - Open Drain Enable Field Reset: DISABLED
309 // Enables open drain of the pin.
310 // DISABLED (0) - Output is CMOS.
311 // ENABLED (1) - Output is Open Drain.
312 // SPEED [7:6] - Speed Field Reset: 100MHZ
313 // RESERVED0 (0) - Reserved
314 // 50MHZ (1) - Low (50 MHz)
315 // 100MHZ (2) - Medium (100 MHz)
316 // 200MHZ (3) - Maximum (200 MHz)
317 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
318 // HIZ (0) - HI-Z
319 // 240_OHM (1) - 240 Ohm
320 // 120_OHM (2) - 120 Ohm
321 // 80_OHM (3) - 80 Ohm
322 // 60_OHM (4) - 60 Ohm
323 // 48_OHM (5) - 48 Ohm
324 // 40_OHM (6) - 40 Ohm
325 // 34_OHM (7) - 34 Ohm
326 // SRE [0] - Slew Rate Field Reset: SLOW
327 // Slew rate control.
328 // SLOW (0) - Slow Slew Rate
329 // FAST (1) - Fast Slew Rate
330 HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR(
331 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS_V(ENABLED) |
332 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS_V(100K_OHM_PU) |
333 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE_V(PULL) |
334 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE_V(ENABLED) |
335 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE_V(DISABLED) |
336 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED_V(100MHZ) |
337 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE_V(40_OHM) |
338 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE_V(SLOW));
339 // Pad NAND_CS3_B is involved in Daisy Chain.
340 // Input Select Register:
341 // IOMUXC_ESAI_SDO1_SELECT_INPUT(0x020E0848)
342 // DAISY [0] - MUX Mode Select Field Reset: GPIO18_ALT0
343 // Selecting Pads Involved in Daisy Chain.
344 // GPIO18_ALT0 (0) - Select signal esai ESAI_TX1 as input from pad GPIO18(ALT0).
345 // NAND_CS3_B_ALT2 (1) - Select signal esai ESAI_TX1 as input from pad NAND_CS3_B(ALT2).
346 HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_WR(
347 BF_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY_V(NAND_CS3_B_ALT2));
348
349 // Config esai.ESAI_TX2_RX3 to pad GPIO05(R4)
350 // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_WR(0x00000000);
351 // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR(0x0001B0B0);
352 // HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_WR(0x00000001);
353 // Mux Register:
354 // IOMUXC_SW_MUX_CTL_PAD_GPIO05(0x020E0230)
355 // SION [4] - Software Input On Field Reset: DISABLED
356 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
357 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
358 // ENABLED (1) - Force input path of pad.
359 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
360 // Select iomux modes to be used for pad.
361 // ALT0 (0) - Select instance: esai signal: ESAI_TX2_RX3
362 // ALT2 (2) - Select instance: kpp signal: KEY_ROW7
363 // ALT3 (3) - Select instance: ccm signal: CCM_CLKO1
364 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO05
365 // ALT6 (6) - Select instance: i2c3 signal: I2C3_SCL
366 // ALT7 (7) - Select instance: arm signal: ARM_EVENTI
367 HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_WR(
368 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION_V(DISABLED) |
369 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE_V(ALT0));
370 // Pad Control Register:
371 // IOMUXC_SW_PAD_CTL_PAD_GPIO05(0x020E0600)
372 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
373 // DISABLED (0) - CMOS input
374 // ENABLED (1) - Schmitt trigger input
375 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
376 // 100K_OHM_PD (0) - 100K Ohm Pull Down
377 // 47K_OHM_PU (1) - 47K Ohm Pull Up
378 // 100K_OHM_PU (2) - 100K Ohm Pull Up
379 // 22K_OHM_PU (3) - 22K Ohm Pull Up
380 // PUE [13] - Pull / Keep Select Field Reset: PULL
381 // KEEP (0) - Keeper Enabled
382 // PULL (1) - Pull Enabled
383 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
384 // DISABLED (0) - Pull/Keeper Disabled
385 // ENABLED (1) - Pull/Keeper Enabled
386 // ODE [11] - Open Drain Enable Field Reset: DISABLED
387 // Enables open drain of the pin.
388 // DISABLED (0) - Output is CMOS.
389 // ENABLED (1) - Output is Open Drain.
390 // SPEED [7:6] - Speed Field Reset: 100MHZ
391 // RESERVED0 (0) - Reserved
392 // 50MHZ (1) - Low (50 MHz)
393 // 100MHZ (2) - Medium (100 MHz)
394 // 200MHZ (3) - Maximum (200 MHz)
395 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
396 // HIZ (0) - HI-Z
397 // 240_OHM (1) - 240 Ohm
398 // 120_OHM (2) - 120 Ohm
399 // 80_OHM (3) - 80 Ohm
400 // 60_OHM (4) - 60 Ohm
401 // 48_OHM (5) - 48 Ohm
402 // 40_OHM (6) - 40 Ohm
403 // 34_OHM (7) - 34 Ohm
404 // SRE [0] - Slew Rate Field Reset: SLOW
405 // Slew rate control.
406 // SLOW (0) - Slow Slew Rate
407 // FAST (1) - Fast Slew Rate
408 HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR(
409 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS_V(ENABLED) |
410 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS_V(100K_OHM_PU) |
411 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE_V(PULL) |
412 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE_V(ENABLED) |
413 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE_V(DISABLED) |
414 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED_V(100MHZ) |
415 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE_V(40_OHM) |
416 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE_V(SLOW));
417 // Pad GPIO05 is involved in Daisy Chain.
418 // Input Select Register:
419 // IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT(0x020E084C)
420 // DAISY [0] - MUX Mode Select Field Reset: ENET_TX_DATA1_ALT2
421 // Selecting Pads Involved in Daisy Chain.
422 // ENET_TX_DATA1_ALT2 (0) - Select signal esai ESAI_TX2_RX3 as input from pad ENET_TX_DATA1(ALT2).
423 // GPIO05_ALT0 (1) - Select signal esai ESAI_TX2_RX3 as input from pad GPIO05(ALT0).
424 HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_WR(
425 BF_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY_V(GPIO05_ALT0));
426
427 // Config esai.ESAI_TX3_RX2 to pad ENET_TX_EN(V21)
428 // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_WR(0x00000002);
429 // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR(0x0001B0B0);
430 // HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_WR(0x00000000);
431 // Mux Register:
432 // IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN(0x020E0200)
433 // SION [4] - Software Input On Field Reset: DISABLED
434 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
435 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
436 // ENABLED (1) - Force input path of pad.
437 // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
438 // Select iomux modes to be used for pad.
439 // ALT1 (1) - Select instance: enet signal: ENET_TX_EN
440 // ALT2 (2) - Select instance: esai signal: ESAI_TX3_RX2
441 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO28
442 // ALT9 (9) - Select instance: i2c4 signal: I2C4_SCL
443 HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_WR(
444 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION_V(DISABLED) |
445 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE_V(ALT2));
446 // Pad Control Register:
447 // IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN(0x020E05D0)
448 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
449 // DISABLED (0) - CMOS input
450 // ENABLED (1) - Schmitt trigger input
451 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
452 // 100K_OHM_PD (0) - 100K Ohm Pull Down
453 // 47K_OHM_PU (1) - 47K Ohm Pull Up
454 // 100K_OHM_PU (2) - 100K Ohm Pull Up
455 // 22K_OHM_PU (3) - 22K Ohm Pull Up
456 // PUE [13] - Pull / Keep Select Field Reset: PULL
457 // KEEP (0) - Keeper Enabled
458 // PULL (1) - Pull Enabled
459 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
460 // DISABLED (0) - Pull/Keeper Disabled
461 // ENABLED (1) - Pull/Keeper Enabled
462 // ODE [11] - Open Drain Enable Field Reset: DISABLED
463 // Enables open drain of the pin.
464 // DISABLED (0) - Output is CMOS.
465 // ENABLED (1) - Output is Open Drain.
466 // SPEED [7:6] - Speed Field Reset: 100MHZ
467 // RESERVED0 (0) - Reserved
468 // 50MHZ (1) - Low (50 MHz)
469 // 100MHZ (2) - Medium (100 MHz)
470 // 200MHZ (3) - Maximum (200 MHz)
471 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
472 // HIZ (0) - HI-Z
473 // 240_OHM (1) - 240 Ohm
474 // 120_OHM (2) - 120 Ohm
475 // 80_OHM (3) - 80 Ohm
476 // 60_OHM (4) - 60 Ohm
477 // 48_OHM (5) - 48 Ohm
478 // 40_OHM (6) - 40 Ohm
479 // 34_OHM (7) - 34 Ohm
480 // SRE [0] - Slew Rate Field Reset: SLOW
481 // Slew rate control.
482 // SLOW (0) - Slow Slew Rate
483 // FAST (1) - Fast Slew Rate
484 HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR(
485 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS_V(ENABLED) |
486 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS_V(100K_OHM_PU) |
487 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE_V(PULL) |
488 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE_V(ENABLED) |
489 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE_V(DISABLED) |
490 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED_V(100MHZ) |
491 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE_V(40_OHM) |
492 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE_V(SLOW));
493 // Pad ENET_TX_EN is involved in Daisy Chain.
494 // Input Select Register:
495 // IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT(0x020E0850)
496 // DAISY [0] - MUX Mode Select Field Reset: ENET_TX_EN_ALT2
497 // Selecting Pads Involved in Daisy Chain.
498 // ENET_TX_EN_ALT2 (0) - Select signal esai ESAI_TX3_RX2 as input from pad ENET_TX_EN(ALT2).
499 // GPIO16_ALT0 (1) - Select signal esai ESAI_TX3_RX2 as input from pad GPIO16(ALT0).
500 HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_WR(
501 BF_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY_V(ENET_TX_EN_ALT2));
502
503 // Config esai.ESAI_TX4_RX1 to pad ENET_TX_DATA0(U20)
504 // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_WR(0x00000002);
505 // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR(0x0001B0B0);
506 // HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_WR(0x00000000);
507 // Mux Register:
508 // IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0(0x020E0204)
509 // SION [4] - Software Input On Field Reset: DISABLED
510 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
511 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
512 // ENABLED (1) - Force input path of pad.
513 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
514 // Select iomux modes to be used for pad.
515 // ALT1 (1) - Select instance: enet signal: ENET_TX_DATA0
516 // ALT2 (2) - Select instance: esai signal: ESAI_TX4_RX1
517 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO30
518 HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_WR(
519 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION_V(DISABLED) |
520 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE_V(ALT2));
521 // Pad Control Register:
522 // IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0(0x020E05D4)
523 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
524 // DISABLED (0) - CMOS input
525 // ENABLED (1) - Schmitt trigger input
526 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
527 // 100K_OHM_PD (0) - 100K Ohm Pull Down
528 // 47K_OHM_PU (1) - 47K Ohm Pull Up
529 // 100K_OHM_PU (2) - 100K Ohm Pull Up
530 // 22K_OHM_PU (3) - 22K Ohm Pull Up
531 // PUE [13] - Pull / Keep Select Field Reset: PULL
532 // KEEP (0) - Keeper Enabled
533 // PULL (1) - Pull Enabled
534 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
535 // DISABLED (0) - Pull/Keeper Disabled
536 // ENABLED (1) - Pull/Keeper Enabled
537 // ODE [11] - Open Drain Enable Field Reset: DISABLED
538 // Enables open drain of the pin.
539 // DISABLED (0) - Output is CMOS.
540 // ENABLED (1) - Output is Open Drain.
541 // SPEED [7:6] - Speed Field Reset: 100MHZ
542 // RESERVED0 (0) - Reserved
543 // 50MHZ (1) - Low (50 MHz)
544 // 100MHZ (2) - Medium (100 MHz)
545 // 200MHZ (3) - Maximum (200 MHz)
546 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
547 // HIZ (0) - HI-Z
548 // 240_OHM (1) - 240 Ohm
549 // 120_OHM (2) - 120 Ohm
550 // 80_OHM (3) - 80 Ohm
551 // 60_OHM (4) - 60 Ohm
552 // 48_OHM (5) - 48 Ohm
553 // 40_OHM (6) - 40 Ohm
554 // 34_OHM (7) - 34 Ohm
555 // SRE [0] - Slew Rate Field Reset: SLOW
556 // Slew rate control.
557 // SLOW (0) - Slow Slew Rate
558 // FAST (1) - Fast Slew Rate
559 HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR(
560 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS_V(ENABLED) |
561 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS_V(100K_OHM_PU) |
562 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE_V(PULL) |
563 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE_V(ENABLED) |
564 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE_V(DISABLED) |
565 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED_V(100MHZ) |
566 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE_V(40_OHM) |
567 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE_V(SLOW));
568 // Pad ENET_TX_DATA0 is involved in Daisy Chain.
569 // Input Select Register:
570 // IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT(0x020E0854)
571 // DAISY [0] - MUX Mode Select Field Reset: ENET_TX_DATA0_ALT2
572 // Selecting Pads Involved in Daisy Chain.
573 // ENET_TX_DATA0_ALT2 (0) - Select signal esai ESAI_TX4_RX1 as input from pad ENET_TX_DATA0(ALT2).
574 // GPIO07_ALT0 (1) - Select signal esai ESAI_TX4_RX1 as input from pad GPIO07(ALT0).
575 HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_WR(
576 BF_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY_V(ENET_TX_DATA0_ALT2));
577
578 // Config esai.ESAI_TX5_RX0 to pad ENET_MDC(V20)
579 // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_WR(0x00000002);
580 // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR(0x0001B0B0);
581 // HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_WR(0x00000000);
582 // Mux Register:
583 // IOMUXC_SW_MUX_CTL_PAD_ENET_MDC(0x020E01E8)
584 // SION [4] - Software Input On Field Reset: DISABLED
585 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
586 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
587 // ENABLED (1) - Force input path of pad.
588 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
589 // Select iomux modes to be used for pad.
590 // ALT0 (0) - Select instance: mlb signal: MLB_DATA
591 // ALT1 (1) - Select instance: enet signal: ENET_MDC
592 // ALT2 (2) - Select instance: esai signal: ESAI_TX5_RX0
593 // ALT4 (4) - Select instance: enet signal: ENET_1588_EVENT1_IN
594 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO31
595 HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_WR(
596 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION_V(DISABLED) |
597 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE_V(ALT2));
598 // Pad Control Register:
599 // IOMUXC_SW_PAD_CTL_PAD_ENET_MDC(0x020E05B8)
600 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
601 // DISABLED (0) - CMOS input
602 // ENABLED (1) - Schmitt trigger input
603 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
604 // 100K_OHM_PD (0) - 100K Ohm Pull Down
605 // 47K_OHM_PU (1) - 47K Ohm Pull Up
606 // 100K_OHM_PU (2) - 100K Ohm Pull Up
607 // 22K_OHM_PU (3) - 22K Ohm Pull Up
608 // PUE [13] - Pull / Keep Select Field Reset: PULL
609 // KEEP (0) - Keeper Enabled
610 // PULL (1) - Pull Enabled
611 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
612 // DISABLED (0) - Pull/Keeper Disabled
613 // ENABLED (1) - Pull/Keeper Enabled
614 // ODE [11] - Open Drain Enable Field Reset: DISABLED
615 // Enables open drain of the pin.
616 // DISABLED (0) - Output is CMOS.
617 // ENABLED (1) - Output is Open Drain.
618 // SPEED [7:6] - Speed Field Reset: 100MHZ
619 // RESERVED0 (0) - Reserved
620 // 50MHZ (1) - Low (50 MHz)
621 // 100MHZ (2) - Medium (100 MHz)
622 // 200MHZ (3) - Maximum (200 MHz)
623 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
624 // HIZ (0) - HI-Z
625 // 240_OHM (1) - 240 Ohm
626 // 120_OHM (2) - 120 Ohm
627 // 80_OHM (3) - 80 Ohm
628 // 60_OHM (4) - 60 Ohm
629 // 48_OHM (5) - 48 Ohm
630 // 40_OHM (6) - 40 Ohm
631 // 34_OHM (7) - 34 Ohm
632 // SRE [0] - Slew Rate Field Reset: SLOW
633 // Slew rate control.
634 // SLOW (0) - Slow Slew Rate
635 // FAST (1) - Fast Slew Rate
636 HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR(
637 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS_V(ENABLED) |
638 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS_V(100K_OHM_PU) |
639 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE_V(PULL) |
640 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE_V(ENABLED) |
641 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE_V(DISABLED) |
642 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED_V(100MHZ) |
643 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE_V(40_OHM) |
644 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE_V(SLOW));
645 // Pad ENET_MDC is involved in Daisy Chain.
646 // Input Select Register:
647 // IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT(0x020E0858)
648 // DAISY [0] - MUX Mode Select Field Reset: ENET_MDC_ALT2
649 // Selecting Pads Involved in Daisy Chain.
650 // ENET_MDC_ALT2 (0) - Select signal esai ESAI_TX5_RX0 as input from pad ENET_MDC(ALT2).
651 // GPIO08_ALT0 (1) - Select signal esai ESAI_TX5_RX0 as input from pad GPIO08(ALT0).
652 HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_WR(
653 BF_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY_V(ENET_MDC_ALT2));
654
655 // Config esai.ESAI_TX_CLK to pad ENET_CRS_DV(U21)
656 // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_WR(0x00000002);
657 // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR(0x0001B0B0);
658 // HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_WR(0x00000000);
659 // Mux Register:
660 // IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV(0x020E01E4)
661 // SION [4] - Software Input On Field Reset: DISABLED
662 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
663 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
664 // ENABLED (1) - Force input path of pad.
665 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
666 // Select iomux modes to be used for pad.
667 // ALT1 (1) - Select instance: enet signal: ENET_RX_EN
668 // ALT2 (2) - Select instance: esai signal: ESAI_TX_CLK
669 // ALT3 (3) - Select instance: spdif signal: SPDIF_EXT_CLK
670 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO25
671 HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_WR(
672 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION_V(DISABLED) |
673 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE_V(ALT2));
674 // Pad Control Register:
675 // IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV(0x020E05B4)
676 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
677 // DISABLED (0) - CMOS input
678 // ENABLED (1) - Schmitt trigger input
679 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
680 // 100K_OHM_PD (0) - 100K Ohm Pull Down
681 // 47K_OHM_PU (1) - 47K Ohm Pull Up
682 // 100K_OHM_PU (2) - 100K Ohm Pull Up
683 // 22K_OHM_PU (3) - 22K Ohm Pull Up
684 // PUE [13] - Pull / Keep Select Field Reset: PULL
685 // KEEP (0) - Keeper Enabled
686 // PULL (1) - Pull Enabled
687 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
688 // DISABLED (0) - Pull/Keeper Disabled
689 // ENABLED (1) - Pull/Keeper Enabled
690 // ODE [11] - Open Drain Enable Field Reset: DISABLED
691 // Enables open drain of the pin.
692 // DISABLED (0) - Output is CMOS.
693 // ENABLED (1) - Output is Open Drain.
694 // SPEED [7:6] - Speed Field Reset: 100MHZ
695 // NOTE: Read Only Field
696 // The value of this field is fixed and cannot be changed.
697 // RESERVED0 (0) - Reserved
698 // 50MHZ (1) - Low (50 MHz)
699 // 100MHZ (2) - Medium (100 MHz)
700 // 200MHZ (3) - Maximum (200 MHz)
701 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
702 // HIZ (0) - HI-Z
703 // 240_OHM (1) - 240 Ohm
704 // 120_OHM (2) - 120 Ohm
705 // 80_OHM (3) - 80 Ohm
706 // 60_OHM (4) - 60 Ohm
707 // 48_OHM (5) - 48 Ohm
708 // 40_OHM (6) - 40 Ohm
709 // 34_OHM (7) - 34 Ohm
710 // SRE [0] - Slew Rate Field Reset: SLOW
711 // Slew rate control.
712 // SLOW (0) - Slow Slew Rate
713 // FAST (1) - Fast Slew Rate
714 HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR(
715 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS_V(ENABLED) |
716 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS_V(100K_OHM_PU) |
717 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE_V(PULL) |
718 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE_V(ENABLED) |
719 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE_V(DISABLED) |
720 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE_V(40_OHM) |
721 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE_V(SLOW));
722 // Pad ENET_CRS_DV is involved in Daisy Chain.
723 // Input Select Register:
724 // IOMUXC_ESAI_TX_CLK_SELECT_INPUT(0x020E0840)
725 // DAISY [0] - MUX Mode Select Field Reset: ENET_CRS_DV_ALT2
726 // Selecting Pads Involved in Daisy Chain.
727 // ENET_CRS_DV_ALT2 (0) - Select signal esai ESAI_TX_CLK as input from pad ENET_CRS_DV(ALT2).
728 // GPIO06_ALT0 (1) - Select signal esai ESAI_TX_CLK as input from pad GPIO06(ALT0).
729 HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_WR(
730 BF_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY_V(ENET_CRS_DV_ALT2));
731
732 // Config esai.ESAI_TX_FS to pad ENET_RX_DATA1(W22)
733 // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_WR(0x00000002);
734 // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR(0x0001B0B0);
735 // HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_WR(0x00000000);
736 // Mux Register:
737 // IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1(0x020E01FC)
738 // SION [4] - Software Input On Field Reset: DISABLED
739 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
740 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
741 // ENABLED (1) - Force input path of pad.
742 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
743 // Select iomux modes to be used for pad.
744 // ALT0 (0) - Select instance: mlb signal: MLB_SIG
745 // ALT1 (1) - Select instance: enet signal: ENET_RX_DATA1
746 // ALT2 (2) - Select instance: esai signal: ESAI_TX_FS
747 // ALT4 (4) - Select instance: enet signal: ENET_1588_EVENT3_OUT
748 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO26
749 HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_WR(
750 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION_V(DISABLED) |
751 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE_V(ALT2));
752 // Pad Control Register:
753 // IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1(0x020E05CC)
754 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
755 // DISABLED (0) - CMOS input
756 // ENABLED (1) - Schmitt trigger input
757 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
758 // 100K_OHM_PD (0) - 100K Ohm Pull Down
759 // 47K_OHM_PU (1) - 47K Ohm Pull Up
760 // 100K_OHM_PU (2) - 100K Ohm Pull Up
761 // 22K_OHM_PU (3) - 22K Ohm Pull Up
762 // PUE [13] - Pull / Keep Select Field Reset: PULL
763 // KEEP (0) - Keeper Enabled
764 // PULL (1) - Pull Enabled
765 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
766 // DISABLED (0) - Pull/Keeper Disabled
767 // ENABLED (1) - Pull/Keeper Enabled
768 // ODE [11] - Open Drain Enable Field Reset: DISABLED
769 // Enables open drain of the pin.
770 // DISABLED (0) - Output is CMOS.
771 // ENABLED (1) - Output is Open Drain.
772 // SPEED [7:6] - Speed Field Reset: 100MHZ
773 // RESERVED0 (0) - Reserved
774 // 50MHZ (1) - Low (50 MHz)
775 // 100MHZ (2) - Medium (100 MHz)
776 // 200MHZ (3) - Maximum (200 MHz)
777 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
778 // HIZ (0) - HI-Z
779 // 240_OHM (1) - 240 Ohm
780 // 120_OHM (2) - 120 Ohm
781 // 80_OHM (3) - 80 Ohm
782 // 60_OHM (4) - 60 Ohm
783 // 48_OHM (5) - 48 Ohm
784 // 40_OHM (6) - 40 Ohm
785 // 34_OHM (7) - 34 Ohm
786 // SRE [0] - Slew Rate Field Reset: SLOW
787 // Slew rate control.
788 // SLOW (0) - Slow Slew Rate
789 // FAST (1) - Fast Slew Rate
790 HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR(
791 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS_V(ENABLED) |
792 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS_V(100K_OHM_PU) |
793 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE_V(PULL) |
794 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE_V(ENABLED) |
795 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE_V(DISABLED) |
796 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED_V(100MHZ) |
797 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE_V(40_OHM) |
798 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE_V(SLOW));
799 // Pad ENET_RX_DATA1 is involved in Daisy Chain.
800 // Input Select Register:
801 // IOMUXC_ESAI_TX_FS_SELECT_INPUT(0x020E0830)
802 // DAISY [0] - MUX Mode Select Field Reset: ENET_RX_DATA1_ALT2
803 // Selecting Pads Involved in Daisy Chain.
804 // ENET_RX_DATA1_ALT2 (0) - Select signal esai ESAI_TX_FS as input from pad ENET_RX_DATA1(ALT2).
805 // GPIO02_ALT0 (1) - Select signal esai ESAI_TX_FS as input from pad GPIO02(ALT0).
806 HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_WR(
807 BF_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY_V(ENET_RX_DATA1_ALT2));
808 }
809