1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-11-09 shelton first version 9 */ 10 11 #ifndef __DMA_CONFIG_H__ 12 #define __DMA_CONFIG_H__ 13 14 #include <rtthread.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /* DMA1 channel1 */ 21 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) 22 #define SPI1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler 23 #define SPI1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 24 #define SPI1_RX_DMA_CHANNEL DMA1_CHANNEL1 25 #define SPI1_RX_DMA_IRQ DMA1_Channel1_IRQn 26 #define SPI1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 27 #define SPI1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI1_RX 28 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) 29 #define UART1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler 30 #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 31 #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL1 32 #define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn 33 #define UART1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 34 #define UART1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_RX 35 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) 36 #define I2C1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler 37 #define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 38 #define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL1 39 #define I2C1_RX_DMA_IRQ DMA1_Channel1_IRQn 40 #define I2C1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 41 #define I2C1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_RX 42 #endif 43 44 /* DMA1 channel2 */ 45 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) 46 #define SPI1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler 47 #define SPI1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 48 #define SPI1_TX_DMA_CHANNEL DMA1_CHANNEL2 49 #define SPI1_TX_DMA_IRQ DMA1_Channel2_IRQn 50 #define SPI1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 51 #define SPI1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI1_TX 52 #elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_CHANNEL) 53 #define UART1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler 54 #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 55 #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL2 56 #define UART1_TX_DMA_IRQ DMA1_Channel2_IRQn 57 #define UART1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 58 #define UART1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_TX 59 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) 60 #define I2C1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler 61 #define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 62 #define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 63 #define I2C1_TX_DMA_IRQ DMA1_Channel2_IRQn 64 #define I2C1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 65 #define I2C1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_TX 66 #endif 67 68 /* DMA1 channel3 */ 69 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) 70 #define SPI2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler 71 #define SPI2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 72 #define SPI2_RX_DMA_CHANNEL DMA1_CHANNEL3 73 #define SPI2_RX_DMA_IRQ DMA1_Channel3_IRQn 74 #define SPI2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 75 #define SPI2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI2_RX 76 #elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) 77 #define UART2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler 78 #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 79 #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL3 80 #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn 81 #define UART2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 82 #define UART2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_RX 83 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) 84 #define I2C2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler 85 #define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 86 #define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL3 87 #define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn 88 #define I2C2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 89 #define I2C2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_RX 90 #endif 91 92 /* DMA1 channel4 */ 93 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) 94 #define SPI2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler 95 #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 96 #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL4 97 #define SPI2_TX_DMA_IRQ DMA1_Channel4_IRQn 98 #define SPI2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 99 #define SPI2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI2_TX 100 #elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_CHANNEL) 101 #define UART2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler 102 #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 103 #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL4 104 #define UART2_TX_DMA_IRQ DMA1_Channel4_IRQn 105 #define UART2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 106 #define UART2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_TX 107 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) 108 #define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler 109 #define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 110 #define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 111 #define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn 112 #define I2C2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 113 #define I2C2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_TX 114 #endif 115 116 /* DMA1 channel5 */ 117 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) 118 #define SPI3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler 119 #define SPI3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 120 #define SPI3_RX_DMA_CHANNEL DMA1_CHANNEL5 121 #define SPI3_RX_DMA_IRQ DMA1_Channel5_IRQn 122 #define SPI3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 123 #define SPI3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI3_RX 124 #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL) 125 #define UART3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler 126 #define UART3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 127 #define UART3_RX_DMA_CHANNEL DMA1_CHANNEL5 128 #define UART3_RX_DMA_IRQ DMA1_Channel5_IRQn 129 #define UART3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 130 #define UART3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_RX 131 #elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) 132 #define I2C3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler 133 #define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 134 #define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL5 135 #define I2C3_RX_DMA_IRQ DMA1_Channel5_IRQn 136 #define I2C3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 137 #define I2C3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_RX 138 #endif 139 140 /* DMA1 channel6 */ 141 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) 142 #define SPI3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler 143 #define SPI3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 144 #define SPI3_TX_DMA_CHANNEL DMA1_CHANNEL6 145 #define SPI3_TX_DMA_IRQ DMA1_Channel6_IRQn 146 #define SPI3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 147 #define SPI3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI3_TX 148 #elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_CHANNEL) 149 #define UART3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler 150 #define UART3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 151 #define UART3_TX_DMA_CHANNEL DMA1_CHANNEL6 152 #define UART3_TX_DMA_IRQ DMA1_Channel6_IRQn 153 #define UART3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 154 #define UART3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_TX 155 #elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) 156 #define I2C3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler 157 #define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 158 #define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL6 159 #define I2C3_TX_DMA_IRQ DMA1_Channel6_IRQn 160 #define I2C3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 161 #define I2C3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_TX 162 #endif 163 164 /* DMA1 channel7 */ 165 #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_CHANNEL) 166 #define UART4_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler 167 #define UART4_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 168 #define UART4_RX_DMA_CHANNEL DMA1_CHANNEL7 169 #define UART4_RX_DMA_IRQ DMA1_Channel7_IRQn 170 #define UART4_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL7 171 #define UART4_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART4_RX 172 #endif 173 174 /* DMA2 channel1 */ 175 #if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_CHANNEL) 176 #define UART4_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler 177 #define UART4_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 178 #define UART4_TX_DMA_CHANNEL DMA2_CHANNEL1 179 #define UART4_TX_DMA_IRQ DMA2_Channel1_IRQn 180 #define UART4_TX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL1 181 #define UART4_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART4_TX 182 #endif 183 184 /* DMA2 channel2 */ 185 #if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_CHANNEL) 186 #define UART5_RX_DMA_IRQHandler DMA2_Channel2_IRQHandler 187 #define UART5_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 188 #define UART5_RX_DMA_CHANNEL DMA2_CHANNEL2 189 #define UART5_RX_DMA_IRQ DMA2_Channel2_IRQn 190 #define UART5_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL2 191 #define UART5_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART5_RX 192 #endif 193 194 /* DMA2 channel3 */ 195 #if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_CHANNEL) 196 #define UART5_TX_DMA_IRQHandler DMA2_Channel3_IRQHandler 197 #define UART5_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 198 #define UART5_TX_DMA_CHANNEL DMA2_CHANNEL3 199 #define UART5_TX_DMA_IRQ DMA2_Channel3_IRQn 200 #define UART5_TX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL3 201 #define UART5_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART5_TX 202 #endif 203 204 /* DMA2 channel4 */ 205 #if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_CHANNEL) 206 #define UART6_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler 207 #define UART6_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 208 #define UART6_RX_DMA_CHANNEL DMA2_CHANNEL4 209 #define UART6_RX_DMA_IRQ DMA2_Channel4_IRQn 210 #define UART6_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL4 211 #define UART6_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART6_RX 212 #endif 213 214 /* DMA2 channel5 */ 215 #if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_CHANNEL) 216 #define UART6_TX_DMA_IRQHandler DMA2_Channel5_IRQHandler 217 #define UART6_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 218 #define UART6_TX_DMA_CHANNEL DMA2_CHANNEL5 219 #define UART6_TX_DMA_IRQ DMA2_Channel5_IRQn 220 #define UART6_TX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL5 221 #define UART6_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART6_TX 222 #endif 223 224 /* DMA2 channel6 */ 225 #if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_CHANNEL) 226 #define UART7_RX_DMA_IRQHandler DMA2_Channel6_IRQHandler 227 #define UART7_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 228 #define UART7_RX_DMA_CHANNEL DMA2_CHANNEL6 229 #define UART7_RX_DMA_IRQ DMA2_Channel6_IRQn 230 #define UART7_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL6 231 #define UART7_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_UART7_RX 232 #endif 233 234 /* DMA2 channel7 */ 235 #if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_CHANNEL) 236 #define UART7_TX_DMA_IRQHandler DMA2_Channel7_IRQHandler 237 #define UART7_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 238 #define UART7_TX_DMA_CHANNEL DMA2_CHANNEL7 239 #define UART7_TX_DMA_IRQ DMA2_Channel7_IRQn 240 #define UART7_TX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL7 241 #define UART7_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_UART7_TX 242 #endif 243 244 #ifdef __cplusplus 245 } 246 #endif 247 248 #endif /* __DMA_CONFIG_H__ */ 249