1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-11-09 shelton first version 9 */ 10 11 #ifndef __DMA_CONFIG_H__ 12 #define __DMA_CONFIG_H__ 13 14 #include <rtthread.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /* DMA1 channel1 */ 21 /* DMA1 channel2 */ 22 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) 23 #define SPI1_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler 24 #define SPI1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 25 #define SPI1_RX_DMA_CHANNEL DMA1_CHANNEL2 26 #define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn 27 #elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_CHANNEL) 28 #define UART3_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler 29 #define UART3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 30 #define UART3_TX_DMA_CHANNEL DMA1_CHANNEL2 31 #define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn 32 #endif 33 34 /* DMA1 channel3 */ 35 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) 36 #define SPI1_TX_DMA_IRQHandler DMA1_Channel3_IRQHandler 37 #define SPI1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 38 #define SPI1_TX_DMA_CHANNEL DMA1_CHANNEL3 39 #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn 40 #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL) 41 #define UART3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler 42 #define UART3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 43 #define UART3_RX_DMA_CHANNEL DMA1_CHANNEL3 44 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn 45 #endif 46 47 /* DMA1 channel4 */ 48 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) 49 #define SPI2_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler 50 #define SPI2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 51 #define SPI2_RX_DMA_CHANNEL DMA1_CHANNEL4 52 #define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn 53 #elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_CHANNEL) 54 #define UART1_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler 55 #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 56 #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL4 57 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn 58 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) 59 #define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler 60 #define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 61 #define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 62 #define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn 63 #endif 64 65 /* DMA1 channel5 */ 66 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) 67 #define SPI2_TX_DMA_IRQHandler DMA1_Channel5_IRQHandler 68 #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 69 #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL5 70 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn 71 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) 72 #define UART1_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler 73 #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 74 #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL5 75 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn 76 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) 77 #define I2C2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler 78 #define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 79 #define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 80 #define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn 81 #endif 82 83 /* DMA1 channel6 */ 84 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) 85 #define UART2_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler 86 #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 87 #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL6 88 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn 89 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) 90 #define I2C1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler 91 #define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 92 #define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL6 93 #define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn 94 #endif 95 96 /* DMA1 channel7 */ 97 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_CHANNEL) 98 #define UART2_TX_DMA_IRQHandler DMA1_Channel7_IRQHandler 99 #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 100 #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL7 101 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn 102 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) 103 #define I2C1_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler 104 #define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 105 #define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL7 106 #define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn 107 #endif 108 109 /* DMA2 channel3 */ 110 #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_CHANNEL) 111 #define UART4_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler 112 #define UART4_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 113 #define UART4_RX_DMA_CHANNEL DMA2_CHANNEL3 114 #define UART4_RX_DMA_IRQ DMA2_Channel3_IRQn 115 #endif 116 /* DMA2 channel4 */ 117 /* DMA2 channel5 */ 118 #if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_CHANNEL) 119 #define UART4_TX_DMA_IRQHandler DMA2_Channel4_5_IRQHandler 120 #define UART4_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK 121 #define UART4_TX_DMA_CHANNEL DMA2_CHANNEL5 122 #define UART4_TX_DMA_IRQ DMA2_Channel4_5_IRQn 123 #endif 124 125 #ifdef __cplusplus 126 } 127 #endif 128 129 #endif /* __DMA_CONFIG_H__ */ 130