1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2023-01-31 shelton first version 9 */ 10 11 #ifndef __DMA_CONFIG_H__ 12 #define __DMA_CONFIG_H__ 13 14 #include <rtthread.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /* DMA1 channel1 */ 21 /* DMA1 channel2 */ 22 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) 23 #define SPI1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 24 #define SPI1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 25 #define SPI1_RX_DMA_CHANNEL DMA1_CHANNEL2 26 #define SPI1_RX_DMA_IRQ DMA1_Channel3_2_IRQn 27 #elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_CHANNEL) 28 #define UART1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 29 #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 30 #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL2 31 #define UART1_TX_DMA_IRQ DMA1_Channel3_2_IRQn 32 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) 33 #define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 34 #define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 35 #define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 36 #define I2C1_TX_DMA_IRQ DMA1_Channel3_2_IRQn 37 #endif 38 39 /* DMA1 channel3 */ 40 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) 41 #define SPI1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 42 #define SPI1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 43 #define SPI1_TX_DMA_CHANNEL DMA1_CHANNEL3 44 #define SPI1_TX_DMA_IRQ DMA1_Channel3_2_IRQn 45 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) 46 #define UART1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 47 #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 48 #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL3 49 #define UART1_RX_DMA_IRQ DMA1_Channel3_2_IRQn 50 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) 51 #define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 52 #define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 53 #define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL3 54 #define I2C1_RX_DMA_IRQ DMA1_Channel3_2_IRQn 55 #endif 56 57 /* DMA1 channel4 */ 58 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) 59 #define SPI2_TX_RX_DMA_IRQHandler DMA1_Channel5_4_IRQHandler 60 #define SPI2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 61 #define SPI2_RX_DMA_CHANNEL DMA1_CHANNEL4 62 #define SPI2_RX_DMA_IRQ DMA1_Channel5_4_IRQn 63 #elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_CHANNEL) 64 #define UART2_TX_RX_DMA_IRQHandler DMA1_Channel5_4_IRQHandler 65 #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 66 #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL4 67 #define UART2_TX_DMA_IRQ DMA1_Channel5_4_IRQn 68 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) 69 #define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel5_4_IRQHandler 70 #define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 71 #define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 72 #define I2C2_TX_DMA_IRQ DMA1_Channel5_4_IRQn 73 #endif 74 75 /* DMA1 channel5 */ 76 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) 77 #define SPI2_TX_RX_DMA_IRQHandler DMA1_Channel5_4_IRQHandler 78 #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 79 #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL5 80 #define SPI2_TX_DMA_IRQ DMA1_Channel5_4_IRQn 81 #elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) 82 #define UART2_TX_RX_DMA_IRQHandler DMA1_Channel5_4_IRQHandler 83 #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 84 #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL5 85 #define UART2_RX_DMA_IRQ DMA1_Channel5_4_IRQn 86 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) 87 #define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel5_4_IRQHandler 88 #define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 89 #define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 90 #define I2C2_RX_DMA_IRQ DMA1_Channel5_4_IRQn 91 #endif 92 93 #ifdef __cplusplus 94 } 95 #endif 96 97 #endif /* __DMA_CONFIG_H__ */ 98