1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2023-01-31 shelton first version 9 */ 10 11 #ifndef __DMA_CONFIG_H__ 12 #define __DMA_CONFIG_H__ 13 14 #include <rtthread.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /* DMA1 channel1 */ 21 /* DMA1 channel2 */ 22 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) 23 #define SPI1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 24 #define SPI1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 25 #define SPI1_RX_DMA_CHANNEL DMA1_CHANNEL2 26 #define SPI1_RX_DMA_IRQ DMA1_Channel3_2_IRQn 27 #define SPI1_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL2 28 #define SPI1_RX_DMA_REQ_ID DMA_FLEXIBLE_SPI1_RX 29 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) 30 #define UART1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 31 #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 32 #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL2 33 #define UART1_RX_DMA_IRQ DMA1_Channel3_2_IRQn 34 #define UART1_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL2 35 #define UART1_RX_DMA_REQ_ID DMA_FLEXIBLE_UART1_RX 36 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) 37 #define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 38 #define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 39 #define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL2 40 #define I2C1_RX_DMA_IRQ DMA1_Channel3_2_IRQn 41 #define I2C1_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL2 42 #define I2C1_RX_DMA_REQ_ID DMA_FLEXIBLE_I2C1_RX 43 #endif 44 45 /* DMA1 channel3 */ 46 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) 47 #define SPI1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 48 #define SPI1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 49 #define SPI1_TX_DMA_CHANNEL DMA1_CHANNEL3 50 #define SPI1_TX_DMA_IRQ DMA1_Channel3_2_IRQn 51 #define SPI1_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL3 52 #define SPI1_TX_DMA_REQ_ID DMA_FLEXIBLE_SPI1_TX 53 #elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_CHANNEL) 54 #define UART1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 55 #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 56 #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL3 57 #define UART1_TX_DMA_IRQ DMA1_Channel3_2_IRQn 58 #define UART1_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL3 59 #define UART1_TX_DMA_REQ_ID DMA_FLEXIBLE_UART1_TX 60 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) 61 #define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler 62 #define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 63 #define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL3 64 #define I2C1_TX_DMA_IRQ DMA1_Channel3_2_IRQn 65 #define I2C1_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL3 66 #define I2C1_TX_DMA_REQ_ID DMA_FLEXIBLE_I2C1_TX 67 #endif 68 69 /* DMA1 channel4 */ 70 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) 71 #define SPI3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler 72 #define SPI2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 73 #define SPI2_RX_DMA_CHANNEL DMA1_CHANNEL4 74 #define SPI2_RX_DMA_IRQ DMA1_Channel7_4_IRQn 75 #define SPI2_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL4 76 #define SPI2_RX_DMA_REQ_ID DMA_FLEXIBLE_SPI2_RX 77 #elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) 78 #define UART3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler 79 #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 80 #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL4 81 #define UART2_RX_DMA_IRQ DMA1_Channel7_4_IRQn 82 #define UART2_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL4 83 #define UART2_RX_DMA_REQ_ID DMA_FLEXIBLE_UART2_RX 84 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) 85 #define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler 86 #define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 87 #define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL4 88 #define I2C2_RX_DMA_IRQ DMA1_Channel7_4_IRQn 89 #define I2C2_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL4 90 #define I2C2_RX_DMA_REQ_ID DMA_FLEXIBLE_I2C2_RX 91 #endif 92 93 /* DMA1 channel5 */ 94 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) 95 #define SPI3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler 96 #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 97 #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL5 98 #define SPI2_TX_DMA_IRQ DMA1_Channel7_4_IRQn 99 #define SPI2_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL5 100 #define SPI2_TX_DMA_REQ_ID DMA_FLEXIBLE_SPI2_TX 101 #elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_CHANNEL) 102 #define UART3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler 103 #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 104 #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL5 105 #define UART2_TX_DMA_IRQ DMA1_Channel7_4_IRQn 106 #define UART2_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL5 107 #define UART2_TX_DMA_REQ_ID DMA_FLEXIBLE_UART2_TX 108 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) 109 #define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler 110 #define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 111 #define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL5 112 #define I2C2_TX_DMA_IRQ DMA1_Channel7_4_IRQn 113 #define I2C2_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL5 114 #define I2C2_TX_DMA_REQ_ID DMA_FLEXIBLE_I2C2_TX 115 #endif 116 117 /* DMA1 channel6 */ 118 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL) 119 #define SPI3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler 120 #define SPI3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 121 #define SPI3_RX_DMA_CHANNEL DMA1_CHANNEL6 122 #define SPI3_RX_DMA_IRQ DMA1_Channel7_4_IRQn 123 #define SPI3_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL6 124 #define SPI3_RX_DMA_REQ_ID DMA_FLEXIBLE_SPI3_RX 125 #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL) 126 #define UART3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler 127 #define UART3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 128 #define UART3_RX_DMA_CHANNEL DMA1_CHANNEL6 129 #define UART3_RX_DMA_IRQ DMA1_Channel7_4_IRQn 130 #define UART3_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL6 131 #define UART3_RX_DMA_REQ_ID DMA_FLEXIBLE_UART3_RX 132 #endif 133 134 /* DMA1 channel7 */ 135 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL) 136 #define SPI3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler 137 #define SPI3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 138 #define SPI3_TX_DMA_CHANNEL DMA1_CHANNEL7 139 #define SPI3_TX_DMA_IRQ DMA1_Channel7_4_IRQn 140 #define SPI3_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL7 141 #define SPI3_TX_DMA_REQ_ID DMA_FLEXIBLE_SPI3_TX 142 #elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_CHANNEL) 143 #define UART3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler 144 #define UART3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 145 #define UART3_TX_DMA_CHANNEL DMA1_CHANNEL7 146 #define UART3_TX_DMA_IRQ DMA1_Channel7_4_IRQn 147 #define UART3_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL7 148 #define UART3_TX_DMA_REQ_ID DMA_FLEXIBLE_UART3_TX 149 #endif 150 151 #ifdef __cplusplus 152 } 153 #endif 154 155 #endif /* __DMA_CONFIG_H__ */ 156