1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024-07-31 shelton first version 9 */ 10 11 #ifndef __I2C_CONFIG_H__ 12 #define __I2C_CONFIG_H__ 13 14 #include <rtthread.h> 15 #include "dma_config.h" 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 #define HWI2C_OWN_ADDRESS 0x0 22 23 #define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler 24 #define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler 25 #define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler 26 #define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler 27 #define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler 28 #define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler 29 30 #ifdef BSP_USING_HARD_I2C1 31 #define I2C1_CONFIG \ 32 { \ 33 .i2c_x = I2C1, \ 34 .i2c_name = "hwi2c1", \ 35 .timing = 0xC0F03030, \ 36 .ev_irqn = I2C1_EVT_IRQn, \ 37 .er_irqn = I2C1_ERR_IRQn, \ 38 } 39 #endif /* BSP_USING_HARD_I2C1 */ 40 41 #ifdef BSP_I2C1_RX_USING_DMA 42 #define I2C1_RX_DMA_CONFIG \ 43 { \ 44 .dma_channel = I2C1_RX_DMA_CHANNEL, \ 45 .dma_clock = I2C1_RX_DMA_CLOCK, \ 46 .dma_irqn = I2C1_RX_DMA_IRQ, \ 47 .dmamux_channel = I2C1_RX_DMA_MUX_CHANNEL, \ 48 .request_id = I2C1_RX_DMA_REQ_ID, \ 49 } 50 #endif /* BSP_I2C1_RX_USING_DMA */ 51 52 #ifdef BSP_I2C1_TX_USING_DMA 53 #define I2C1_TX_DMA_CONFIG \ 54 { \ 55 .dma_channel = I2C1_TX_DMA_CHANNEL, \ 56 .dma_clock = I2C1_TX_DMA_CLOCK, \ 57 .dma_irqn = I2C1_TX_DMA_IRQ, \ 58 .dmamux_channel = I2C1_TX_DMA_MUX_CHANNEL, \ 59 .request_id = I2C1_TX_DMA_REQ_ID, \ 60 } 61 #endif /* BSP_I2C1_TX_USING_DMA */ 62 63 #ifdef BSP_USING_HARD_I2C2 64 #define I2C2_CONFIG \ 65 { \ 66 .i2c_x = I2C2, \ 67 .i2c_name = "hwi2c2", \ 68 .timing = 0xC0F03030, \ 69 .ev_irqn = I2C2_EVT_IRQn, \ 70 .er_irqn = I2C2_ERR_IRQn, \ 71 } 72 #endif /* BSP_USING_HARD_I2C2 */ 73 74 #ifdef BSP_I2C2_RX_USING_DMA 75 #define I2C2_RX_DMA_CONFIG \ 76 { \ 77 .dma_channel = I2C2_RX_DMA_CHANNEL, \ 78 .dma_clock = I2C2_RX_DMA_CLOCK, \ 79 .dma_irqn = I2C2_RX_DMA_IRQ, \ 80 .dmamux_channel = I2C2_RX_DMA_MUX_CHANNEL, \ 81 .request_id = I2C2_RX_DMA_REQ_ID, \ 82 } 83 #endif /* BSP_I2C2_RX_USING_DMA */ 84 85 #ifdef BSP_I2C2_TX_USING_DMA 86 #define I2C2_TX_DMA_CONFIG \ 87 { \ 88 .dma_channel = I2C2_TX_DMA_CHANNEL, \ 89 .dma_clock = I2C2_TX_DMA_CLOCK, \ 90 .dma_irqn = I2C2_TX_DMA_IRQ, \ 91 .dmamux_channel = I2C2_TX_DMA_MUX_CHANNEL, \ 92 .request_id = I2C2_TX_DMA_REQ_ID, \ 93 } 94 #endif /* BSP_I2C2_TX_USING_DMA */ 95 96 #ifdef BSP_USING_HARD_I2C3 97 #define I2C3_CONFIG \ 98 { \ 99 .i2c_x = I2C3, \ 100 .i2c_name = "hwi2c3", \ 101 .timing = 0xC0F03030, \ 102 .ev_irqn = I2C3_EVT_IRQn, \ 103 .er_irqn = I2C3_ERR_IRQn, \ 104 } 105 #endif /* BSP_USING_HARD_I2C3 */ 106 107 #ifdef BSP_I2C3_RX_USING_DMA 108 #define I2C3_RX_DMA_CONFIG \ 109 { \ 110 .dma_channel = I2C3_RX_DMA_CHANNEL, \ 111 .dma_clock = I2C3_RX_DMA_CLOCK, \ 112 .dma_irqn = I2C3_RX_DMA_IRQ, \ 113 .dmamux_channel = I2C3_RX_DMA_MUX_CHANNEL, \ 114 .request_id = I2C3_RX_DMA_REQ_ID, \ 115 } 116 #endif /* BSP_I2C3_RX_USING_DMA */ 117 118 #ifdef BSP_I2C3_TX_USING_DMA 119 #define I2C3_TX_DMA_CONFIG \ 120 { \ 121 .dma_channel = I2C3_TX_DMA_CHANNEL, \ 122 .dma_clock = I2C3_TX_DMA_CLOCK, \ 123 .dma_irqn = I2C3_TX_DMA_IRQ, \ 124 .dmamux_channel = I2C3_TX_DMA_MUX_CHANNEL, \ 125 .request_id = I2C3_TX_DMA_REQ_ID, \ 126 } 127 #endif /* BSP_I2C3_TX_USING_DMA */ 128 129 #ifdef __cplusplus 130 } 131 #endif 132 133 #endif /*__I2C_CONFIG_H__ */ 134 135