1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: flexcan1_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for flexcan1 module.
flexcan1_iomux_config(void)34 void flexcan1_iomux_config(void)
35 {
36 // Config flexcan1.FLEXCAN1_RX to pad KEY_ROW2(W4)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(0x00000002);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(0x0001B0B0);
39 // HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(0x00000001);
40 // Mux Register:
41 // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2(0x020E0260)
42 // SION [4] - Software Input On Field Reset: DISABLED
43 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
44 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
45 // ENABLED (1) - Force input path of pad.
46 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
47 // Select iomux modes to be used for pad.
48 // ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS2
49 // ALT1 (1) - Select instance: enet signal: ENET_TX_DATA2
50 // ALT2 (2) - Select instance: flexcan1 signal: FLEXCAN1_RX
51 // ALT3 (3) - Select instance: kpp signal: KEY_ROW2
52 // ALT4 (4) - Select instance: usdhc2 signal: SD2_VSELECT
53 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO11
54 // ALT6 (6) - Select instance: hdmi signal: HDMI_TX_CEC_LINE
55 HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(
56 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION_V(DISABLED) |
57 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_V(ALT2));
58 // Pad Control Register:
59 // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2(0x020E0648)
60 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
61 // DISABLED (0) - CMOS input
62 // ENABLED (1) - Schmitt trigger input
63 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
64 // 100K_OHM_PD (0) - 100K Ohm Pull Down
65 // 47K_OHM_PU (1) - 47K Ohm Pull Up
66 // 100K_OHM_PU (2) - 100K Ohm Pull Up
67 // 22K_OHM_PU (3) - 22K Ohm Pull Up
68 // PUE [13] - Pull / Keep Select Field Reset: PULL
69 // KEEP (0) - Keeper Enabled
70 // PULL (1) - Pull Enabled
71 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
72 // DISABLED (0) - Pull/Keeper Disabled
73 // ENABLED (1) - Pull/Keeper Enabled
74 // ODE [11] - Open Drain Enable Field Reset: DISABLED
75 // Enables open drain of the pin.
76 // DISABLED (0) - Output is CMOS.
77 // ENABLED (1) - Output is Open Drain.
78 // SPEED [7:6] - Speed Field Reset: 100MHZ
79 // RESERVED0 (0) - Reserved
80 // 50MHZ (1) - Low (50 MHz)
81 // 100MHZ (2) - Medium (100 MHz)
82 // 200MHZ (3) - Maximum (200 MHz)
83 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
84 // HIZ (0) - HI-Z
85 // 240_OHM (1) - 240 Ohm
86 // 120_OHM (2) - 120 Ohm
87 // 80_OHM (3) - 80 Ohm
88 // 60_OHM (4) - 60 Ohm
89 // 48_OHM (5) - 48 Ohm
90 // 40_OHM (6) - 40 Ohm
91 // 34_OHM (7) - 34 Ohm
92 // SRE [0] - Slew Rate Field Reset: SLOW
93 // Slew rate control.
94 // SLOW (0) - Slow Slew Rate
95 // FAST (1) - Fast Slew Rate
96 HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(
97 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS_V(ENABLED) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_V(100K_OHM_PU) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE_V(PULL) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE_V(ENABLED) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE_V(DISABLED) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_V(100MHZ) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_V(40_OHM) |
104 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE_V(SLOW));
105 // Pad KEY_ROW2 is involved in Daisy Chain.
106 // Input Select Register:
107 // IOMUXC_FLEXCAN1_RX_SELECT_INPUT(0x020E07C8)
108 // DAISY [1:0] - MUX Mode Select Field Reset: GPIO08_ALT3
109 // Selecting Pads Involved in Daisy Chain.
110 // GPIO08_ALT3 (0) - Select signal flexcan1 FLEXCAN1_RX as input from pad GPIO08(ALT3).
111 // KEY_ROW2_ALT2 (1) - Select signal flexcan1 FLEXCAN1_RX as input from pad KEY_ROW2(ALT2).
112 // SD3_CLK_ALT2 (2) - Select signal flexcan1 FLEXCAN1_RX as input from pad SD3_CLK(ALT2).
113 HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(
114 BF_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_V(KEY_ROW2_ALT2));
115
116 // Config flexcan1.FLEXCAN1_TX to pad KEY_COL2(W6)
117 // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(0x00000002);
118 // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(0x0001B0B0);
119 // Mux Register:
120 // IOMUXC_SW_MUX_CTL_PAD_KEY_COL2(0x020E024C)
121 // SION [4] - Software Input On Field Reset: DISABLED
122 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
123 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
124 // ENABLED (1) - Force input path of pad.
125 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
126 // Select iomux modes to be used for pad.
127 // ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS1
128 // ALT1 (1) - Select instance: enet signal: ENET_RX_DATA2
129 // ALT2 (2) - Select instance: flexcan1 signal: FLEXCAN1_TX
130 // ALT3 (3) - Select instance: kpp signal: KEY_COL2
131 // ALT4 (4) - Select instance: enet signal: ENET_MDC
132 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO10
133 // ALT6 (6) - Select instance: usb signal: USB_H1_PWR_CTL_WAKE
134 HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(
135 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION_V(DISABLED) |
136 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_V(ALT2));
137 // Pad Control Register:
138 // IOMUXC_SW_PAD_CTL_PAD_KEY_COL2(0x020E0634)
139 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
140 // DISABLED (0) - CMOS input
141 // ENABLED (1) - Schmitt trigger input
142 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
143 // 100K_OHM_PD (0) - 100K Ohm Pull Down
144 // 47K_OHM_PU (1) - 47K Ohm Pull Up
145 // 100K_OHM_PU (2) - 100K Ohm Pull Up
146 // 22K_OHM_PU (3) - 22K Ohm Pull Up
147 // PUE [13] - Pull / Keep Select Field Reset: PULL
148 // KEEP (0) - Keeper Enabled
149 // PULL (1) - Pull Enabled
150 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
151 // DISABLED (0) - Pull/Keeper Disabled
152 // ENABLED (1) - Pull/Keeper Enabled
153 // ODE [11] - Open Drain Enable Field Reset: DISABLED
154 // Enables open drain of the pin.
155 // DISABLED (0) - Output is CMOS.
156 // ENABLED (1) - Output is Open Drain.
157 // SPEED [7:6] - Speed Field Reset: 100MHZ
158 // RESERVED0 (0) - Reserved
159 // 50MHZ (1) - Low (50 MHz)
160 // 100MHZ (2) - Medium (100 MHz)
161 // 200MHZ (3) - Maximum (200 MHz)
162 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
163 // HIZ (0) - HI-Z
164 // 240_OHM (1) - 240 Ohm
165 // 120_OHM (2) - 120 Ohm
166 // 80_OHM (3) - 80 Ohm
167 // 60_OHM (4) - 60 Ohm
168 // 48_OHM (5) - 48 Ohm
169 // 40_OHM (6) - 40 Ohm
170 // 34_OHM (7) - 34 Ohm
171 // SRE [0] - Slew Rate Field Reset: SLOW
172 // Slew rate control.
173 // SLOW (0) - Slow Slew Rate
174 // FAST (1) - Fast Slew Rate
175 HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(
176 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS_V(ENABLED) |
177 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_V(100K_OHM_PU) |
178 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE_V(PULL) |
179 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE_V(ENABLED) |
180 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE_V(DISABLED) |
181 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_V(100MHZ) |
182 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_V(40_OHM) |
183 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE_V(SLOW));
184 }
185