1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_HOST_H
10 #define _FSL_HOST_H
11
12 #include "fsl_common.h"
13 #include "board.h"
14 #if defined(FSL_FEATURE_SOC_SDHC_COUNT) && FSL_FEATURE_SOC_SDHC_COUNT > 0U
15 #include "fsl_sdhc.h"
16 #elif defined(FSL_FEATURE_SOC_SDIF_COUNT) && FSL_FEATURE_SOC_SDIF_COUNT > 0U
17 #include "fsl_sdif.h"
18 #elif defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT > 0U
19 #include "fsl_usdhc.h"
20 #if (FSL_FEATURE_SOC_IOMUXC_COUNT != 0U)
21 #include "fsl_iomuxc.h"
22 #else
23 #include "fsl_port.h"
24 #endif
25 #endif
26
27 /*!
28 * @addtogroup CARD
29 * @{
30 */
31
32 /*******************************************************************************
33 * Definitions
34 ******************************************************************************/
35 /* add cache line size align */
36 #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
37 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
38 #if defined(FSL_FEATURE_L2DCACHE_LINESIZE_BYTE)
39 #define SDMMC_DATA_BUFFER_ALIGN_CAHCE MAX(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE, FSL_FEATURE_L2DCACHE_LINESIZE_BYTE)
40 #else
41 #define SDMMC_DATA_BUFFER_ALIGN_CAHCE FSL_FEATURE_L1DCACHE_LINESIZE_BYTE
42 #endif
43 #else
44 #define SDMMC_DATA_BUFFER_ALIGN_CAHCE 1
45 #endif
46 #else
47 #define SDMMC_DATA_BUFFER_ALIGN_CAHCE 1
48 #endif
49
50 #define HOST_NOT_SUPPORT 0U /*!< use this define to indicate the host not support feature*/
51 #define HOST_SUPPORT 1U /*!< use this define to indicate the host support feature*/
52 /* select host */
53 #if defined(FSL_FEATURE_SOC_SDHC_COUNT) && FSL_FEATURE_SOC_SDHC_COUNT > 0U
54
55 /* SDR104 mode freq */
56 #if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ
57 #define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ
58 #else
59 #define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ
60 #endif
61 /* HS200 mode freq */
62 #if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ
63 #define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200
64 #else
65 #define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200
66 #endif
67 /* HS400 mode freq */
68 #if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ
69 #define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ /* host do not support HS400 */
70 #else
71 #define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400
72 #endif
73
74 /*define host baseaddr ,clk freq, IRQ number*/
75 #define MMC_HOST_BASEADDR BOARD_SDHC_BASEADDR
76 #define MMC_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ
77 #define MMC_HOST_IRQ BOARD_SDHC_IRQ
78 #define SD_HOST_BASEADDR BOARD_SDHC_BASEADDR
79 #define SD_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ
80 #define SD_HOST_IRQ BOARD_SDHC_IRQ
81
82 /* define for card bus speed/strength cnofig */
83 #define CARD_BUS_FREQ_50MHZ (0U)
84 #define CARD_BUS_FREQ_100MHZ0 (0U)
85 #define CARD_BUS_FREQ_100MHZ1 (0U)
86 #define CARD_BUS_FREQ_200MHZ (0U)
87
88 #define CARD_BUS_STRENGTH_0 (0U)
89 #define CARD_BUS_STRENGTH_1 (0U)
90 #define CARD_BUS_STRENGTH_2 (0U)
91 #define CARD_BUS_STRENGTH_3 (0U)
92 #define CARD_BUS_STRENGTH_4 (0U)
93 #define CARD_BUS_STRENGTH_5 (0U)
94 #define CARD_BUS_STRENGTH_6 (0U)
95 #define CARD_BUS_STRENGTH_7 (0U)
96
97 #define HOST_TYPE SDHC_Type
98 #define HOST_CONFIG sdhc_host_t
99 #define HOST_TRANSFER sdhc_transfer_t
100 #define HOST_COMMAND sdhc_command_t
101 #define HOST_DATA sdhc_data_t
102 #define HOST_BUS_WIDTH_TYPE sdhc_data_bus_width_t
103 #define HOST_CAPABILITY sdhc_capability_t
104
105 #define CARD_DATA0_STATUS_MASK kSDHC_Data0LineLevelFlag
106 #define CARD_DATA0_NOT_BUSY kSDHC_Data0LineLevelFlag
107 #define CARD_DATA1_STATUS_MASK kSDHC_Data1LineLevelFlag
108 #define CARD_DATA2_STATUS_MASK kSDHC_Data2LineLevelFlag
109 #define CARD_DATA3_STATUS_MASK kSDHC_Data3LineLevelFlag
110
111 #define kHOST_DATABUSWIDTH1BIT kSDHC_DataBusWidth1Bit /*!< 1-bit mode */
112 #define kHOST_DATABUSWIDTH4BIT kSDHC_DataBusWidth4Bit /*!< 4-bit mode */
113 #define kHOST_DATABUSWIDTH8BIT kSDHC_DataBusWidth8Bit /*!< 8-bit mode */
114
115 #define HOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */
116 #define HOST_TUINIG_STEP (1U) /*!< standard tuning step */
117 #define HOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */
118 #define HOST_TUNING_DELAY_MAX (0x7FU)
119 #define HOST_RETUNING_REQUEST (1U)
120 #define HOST_TUNING_ERROR (2U)
121
122 /* function pointer define */
123 #define HOST_TRANSFER_FUNCTION sdhc_transfer_function_t
124 #define GET_HOST_CAPABILITY(base, capability) (SDHC_GetCapability(base, capability))
125 #define GET_HOST_STATUS(base) (SDHC_GetPresentStatusFlags(base))
126 #define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (SDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ))
127 #define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDHC_SetDataBusWidth(base, busWidth))
128 #define HOST_SEND_CARD_ACTIVE(base, timeout) (SDHC_SetCardActive(base, timeout))
129 #define HOST_SWITCH_VOLTAGE180V(base, enable18v)
130 #define HOST_SWITCH_VOLTAGE120V(base, enable12v)
131 #define HOST_CONFIG_IO_STRENGTH(speed, strength)
132 #define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag)
133 #define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U)
134 #define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U)
135 #define HOST_CONFIG_SD_IO(speed, strength)
136 #define HOST_CONFIG_MMC_IO(speed, strength)
137 #define HOST_ENABLE_DDR_MODE(base, flag)
138 #define HOST_FORCE_SDCLOCK_ON(base, enable)
139 #define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag)
140 #define HOST_ADJUST_MANUAL_TUNING_DELAY(base, delay)
141 #define HOST_AUTO_MANUAL_TUNING_ENABLE(base, flag)
142 #define HOST_ENABLE_CARD_CLOCK(base, enable) (SDHC_EnableSdClock(base, enable))
143 #define HOST_RESET_TUNING(base, timeout)
144 #define HOST_CHECK_TUNING_ERROR(base) (0U)
145 #define HOST_ADJUST_TUNING_DELAY(base, delay)
146 #define HOST_AUTO_STANDARD_RETUNING_TIMER(base)
147
148 #define HOST_ENABLE_HS400_MODE(base, flag)
149 #define HOST_RESET_STROBE_DLL(base)
150 #define HOST_ENABLE_STROBE_DLL(base, flag)
151 #define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval)
152 #define HOST_GET_STROBE_DLL_STATUS(base)
153 /* sd card power */
154 #define HOST_INIT_SD_POWER()
155 #define HOST_ENABLE_SD_POWER(enable)
156 #define HOST_SWITCH_VCC_TO_180V()
157 #define HOST_SWITCH_VCC_TO_330V()
158 /* mmc card power */
159 #define HOST_INIT_MMC_POWER()
160 #define HOST_ENABLE_MMC_POWER(enable)
161 #define HOST_ENABLE_TUNING_FLAG(data)
162 #define HOST_CARD_DETECT_INTERRUPT_HANDLER BOARD_SDHC_CD_PORT_IRQ_HANDLER
163 #define HOST_CARD_DETECT_IRQ BOARD_SDHC_CD_PORT_IRQ
164
165 /*! @brief SDHC host capability*/
166 enum _host_capability
167 {
168 kHOST_SupportAdma = kSDHC_SupportAdmaFlag,
169 kHOST_SupportHighSpeed = kSDHC_SupportHighSpeedFlag,
170 kHOST_SupportDma = kSDHC_SupportDmaFlag,
171 kHOST_SupportSuspendResume = kSDHC_SupportSuspendResumeFlag,
172 kHOST_SupportV330 = kSDHC_SupportV330Flag,
173 kHOST_SupportV300 = HOST_NOT_SUPPORT,
174 kHOST_SupportV180 = HOST_NOT_SUPPORT,
175 kHOST_SupportV120 = HOST_NOT_SUPPORT,
176 kHOST_Support4BitBusWidth = kSDHC_Support4BitFlag,
177 kHOST_Support8BitBusWidth = kSDHC_Support8BitFlag,
178 kHOST_SupportDDR50 = HOST_NOT_SUPPORT,
179 kHOST_SupportSDR104 = HOST_NOT_SUPPORT,
180 kHOST_SupportSDR50 = HOST_NOT_SUPPORT,
181 kHOST_SupportHS200 = HOST_NOT_SUPPORT,
182 kHOST_SupportHS400 = HOST_NOT_SUPPORT,
183
184 };
185
186 /* Endian mode. */
187 #define SDHC_ENDIAN_MODE kSDHC_EndianModeLittle
188
189 /* DMA mode */
190 #define SDHC_DMA_MODE kSDHC_DmaModeAdma2
191 /* address align */
192 #define HOST_DMA_BUFFER_ADDR_ALIGN (SDHC_ADMA2_ADDRESS_ALIGN)
193
194 /* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */
195 #define SDHC_READ_WATERMARK_LEVEL (0x80U)
196 #define SDHC_WRITE_WATERMARK_LEVEL (0x80U)
197
198 /* ADMA table length united as word.
199 *
200 * SD card driver can't support ADMA1 transfer mode currently.
201 * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time.
202 * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set.
203 */
204 #define SDHC_ADMA_TABLE_WORDS (8U)
205
206 #elif defined(FSL_FEATURE_SOC_SDIF_COUNT) && FSL_FEATURE_SOC_SDIF_COUNT > 0U
207
208 /* SDR104 mode freq */
209 #if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ
210 #define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ
211 #else
212 #define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ
213 #endif
214 /* HS200 mode freq */
215 #if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ
216 #define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200
217 #else
218 #define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200
219 #endif
220 /* HS400 mode freq */
221 #if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ
222 #define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ /* host do not support HS400 */
223 #else
224 #define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400
225 #endif
226
227 /*define host baseaddr ,clk freq, IRQ number*/
228 #define MMC_HOST_BASEADDR BOARD_SDIF_BASEADDR
229 #define MMC_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ
230 #define MMC_HOST_IRQ BOARD_SDIF_IRQ
231 #define SD_HOST_BASEADDR BOARD_SDIF_BASEADDR
232 #define SD_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ
233 #define SD_HOST_IRQ BOARD_SDIF_IRQ
234
235 /* define for card bus speed/strength cnofig */
236 #define CARD_BUS_FREQ_50MHZ (0U)
237 #define CARD_BUS_FREQ_100MHZ0 (0U)
238 #define CARD_BUS_FREQ_100MHZ1 (0U)
239 #define CARD_BUS_FREQ_200MHZ (0U)
240
241 #define CARD_BUS_STRENGTH_0 (0U)
242 #define CARD_BUS_STRENGTH_1 (0U)
243 #define CARD_BUS_STRENGTH_2 (0U)
244 #define CARD_BUS_STRENGTH_3 (0U)
245 #define CARD_BUS_STRENGTH_4 (0U)
246 #define CARD_BUS_STRENGTH_5 (0U)
247 #define CARD_BUS_STRENGTH_6 (0U)
248 #define CARD_BUS_STRENGTH_7 (0U)
249
250 #define HOST_TYPE SDIF_Type
251 #define HOST_CONFIG sdif_host_t
252 #define HOST_TRANSFER sdif_transfer_t
253 #define HOST_COMMAND sdif_command_t
254 #define HOST_DATA sdif_data_t
255 #define HOST_BUS_WIDTH_TYPE sdif_bus_width_t
256 #define HOST_CAPABILITY sdif_capability_t
257
258 #define CARD_DATA0_STATUS_MASK SDIF_STATUS_DATA_BUSY_MASK
259 #define CARD_DATA0_NOT_BUSY 0U
260
261 #define CARD_DATA1_STATUS_MASK (0U)
262 #define CARD_DATA2_STATUS_MASK (0U)
263 #define CARD_DATA3_STATUS_MASK (0U)
264
265 #define kHOST_DATABUSWIDTH1BIT kSDIF_Bus1BitWidth /*!< 1-bit mode */
266 #define kHOST_DATABUSWIDTH4BIT kSDIF_Bus4BitWidth /*!< 4-bit mode */
267 #define kHOST_DATABUSWIDTH8BIT kSDIF_Bus8BitWidth /*!< 8-bit mode */
268
269 #define HOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */
270 #define HOST_TUINIG_STEP (1U) /*!< standard tuning step */
271 #define HOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */
272 #define HOST_TUNING_DELAY_MAX (0x7FU)
273 #define HOST_RETUNING_REQUEST (1U)
274 #define HOST_TUNING_ERROR (2U)
275 /* function pointer define */
276 #define HOST_TRANSFER_FUNCTION sdif_transfer_function_t
277 #define GET_HOST_CAPABILITY(base, capability) (SDIF_GetCapability(base, capability))
278 #define GET_HOST_STATUS(base) (SDIF_GetControllerStatus(base))
279 #define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (SDIF_SetCardClock(base, sourceClock_HZ, busClock_HZ))
280 #define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDIF_SetCardBusWidth(base, busWidth))
281 #define HOST_SEND_CARD_ACTIVE(base, timeout) (SDIF_SendCardActive(base, timeout))
282 #define HOST_SWITCH_VOLTAGE180V(base, enable18v)
283 #define HOST_SWITCH_VOLTAGE120V(base, enable12v)
284 #define HOST_CONFIG_IO_STRENGTH(speed, strength)
285 #define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag)
286 #define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U)
287 #define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U)
288 #define HOST_CONFIG_SD_IO(speed, strength)
289 #define HOST_CONFIG_MMC_IO(speed, strength)
290 #define HOST_ENABLE_DDR_MODE(base, flag)
291 #define HOST_FORCE_SDCLOCK_ON(base, enable)
292 #define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag)
293 #define HOST_ADJUST_MANUAL_TUNING_DELAY(base, delay)
294 #define HOST_AUTO_MANUAL_TUNING_ENABLE(base, flag)
295 #define HOST_ENABLE_CARD_CLOCK(base, enable) (SDIF_EnableCardClock(base, enable))
296 #define HOST_RESET_TUNING(base, timeout)
297 #define HOST_CHECK_TUNING_ERROR(base) (0U)
298 #define HOST_ADJUST_TUNING_DELAY(base, delay)
299 #define HOST_AUTO_STANDARD_RETUNING_TIMER(base)
300
301 #define HOST_ENABLE_HS400_MODE(base, flag)
302 #define HOST_RESET_STROBE_DLL(base)
303 #define HOST_ENABLE_STROBE_DLL(base, flag)
304 #define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval)
305 #define HOST_GET_STROBE_DLL_STATUS(base)
306 /* sd card power */
307 #define HOST_INIT_SD_POWER()
308 #define HOST_ENABLE_SD_POWER(enable)
309 #define HOST_SWITCH_VCC_TO_180V()
310 #define HOST_SWITCH_VCC_TO_330V()
311 /* mmc card power */
312 #define HOST_INIT_MMC_POWER()
313 #define HOST_ENABLE_MMC_POWER(enable)
314 #define HOST_ENABLE_TUNING_FLAG(data)
315 /*! @brief SDIF host capability*/
316 enum _host_capability
317 {
318 kHOST_SupportHighSpeed = kSDIF_SupportHighSpeedFlag,
319 kHOST_SupportDma = kSDIF_SupportDmaFlag,
320 kHOST_SupportSuspendResume = kSDIF_SupportSuspendResumeFlag,
321 kHOST_SupportV330 = kSDIF_SupportV330Flag,
322 kHOST_SupportV300 = HOST_NOT_SUPPORT,
323 kHOST_SupportV180 = HOST_NOT_SUPPORT,
324 kHOST_SupportV120 = HOST_NOT_SUPPORT,
325 kHOST_Support4BitBusWidth = kSDIF_Support4BitFlag,
326 kHOST_Support8BitBusWidth = HOST_NOT_SUPPORT, /* mask the 8 bit here,user can change depend on your board */
327 kHOST_SupportDDR50 = HOST_NOT_SUPPORT,
328 kHOST_SupportSDR104 = HOST_NOT_SUPPORT,
329 kHOST_SupportSDR50 = HOST_NOT_SUPPORT,
330 kHOST_SupportHS200 = HOST_NOT_SUPPORT,
331 kHOST_SupportHS400 = HOST_NOT_SUPPORT,
332
333 };
334
335 /*! @brief DMA table length united as word
336 * One dma table item occupy four words which can transfer maximum 2*8188 bytes in dual DMA mode
337 * and 8188 bytes in chain mode
338 * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set.
339 * user need check the DMA descriptor table lenght if bigger enough.
340 */
341 #define SDIF_DMA_TABLE_WORDS (0x40U)
342 /* address align */
343 #define HOST_DMA_BUFFER_ADDR_ALIGN (4U)
344
345 #elif defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT > 0U
346 /* SDR104 mode freq */
347 #if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ
348 #define HOST_SUPPORT_SDR104_FREQ BOARD_SD_HOST_SUPPORT_SDR104_FREQ
349 #else
350 #define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ
351 #endif
352 /* HS200 mode freq */
353 #if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ
354 #define HOST_SUPPORT_HS200_FREQ BOARD_SD_HOST_SUPPORT_HS200_FREQ
355 #else
356 #define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200
357 #endif
358 /* HS400 mode freq */
359 #if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ
360 #define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ
361 #else
362 #define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400
363 #endif
364
365 /*define host baseaddr ,clk freq, IRQ number*/
366 #define MMC_HOST_BASEADDR BOARD_MMC_HOST_BASEADDR
367 #define MMC_HOST_CLK_FREQ BOARD_MMC_HOST_CLK_FREQ
368 #define MMC_HOST_IRQ BOARD_MMC_HOST_IRQ
369 #define SD_HOST_BASEADDR BOARD_SD_HOST_BASEADDR
370 #define SD_HOST_CLK_FREQ BOARD_SD_HOST_CLK_FREQ
371 #define SD_HOST_IRQ BOARD_SD_HOST_IRQ
372
373 #define HOST_TYPE USDHC_Type
374 #define HOST_CONFIG usdhc_host_t
375 #define HOST_TRANSFER usdhc_transfer_t
376 #define HOST_COMMAND usdhc_command_t
377 #define HOST_DATA usdhc_data_t
378
379 #define CARD_DATA0_STATUS_MASK kUSDHC_Data0LineLevelFlag
380 #define CARD_DATA1_STATUS_MASK kUSDHC_Data1LineLevelFlag
381 #define CARD_DATA2_STATUS_MASK kUSDHC_Data2LineLevelFlag
382 #define CARD_DATA3_STATUS_MASK kUSDHC_Data3LineLevelFlag
383 #define CARD_DATA0_NOT_BUSY kUSDHC_Data0LineLevelFlag
384
385 #define HOST_BUS_WIDTH_TYPE usdhc_data_bus_width_t
386 #define HOST_CAPABILITY usdhc_capability_t
387
388 #define kHOST_DATABUSWIDTH1BIT kUSDHC_DataBusWidth1Bit /*!< 1-bit mode */
389 #define kHOST_DATABUSWIDTH4BIT kUSDHC_DataBusWidth4Bit /*!< 4-bit mode */
390 #define kHOST_DATABUSWIDTH8BIT kUSDHC_DataBusWidth8Bit /*!< 8-bit mode */
391
392 #define HOST_STANDARD_TUNING_START (10U) /*!< standard tuning start point */
393 #define HOST_TUINIG_STEP (2U) /*!< standard tuning step */
394 #define HOST_RETUNING_TIMER_COUNT (0U) /*!< Re-tuning timer */
395 #define HOST_TUNING_DELAY_MAX (0x7FU)
396 #define HOST_RETUNING_REQUEST kStatus_USDHC_ReTuningRequest
397 #define HOST_TUNING_ERROR kStatus_USDHC_TuningError
398 /* define for card bus speed/strength cnofig */
399 #define CARD_BUS_FREQ_50MHZ (0U)
400 #define CARD_BUS_FREQ_100MHZ0 (1U)
401 #define CARD_BUS_FREQ_100MHZ1 (2U)
402 #define CARD_BUS_FREQ_200MHZ (3U)
403
404 #define CARD_BUS_STRENGTH_0 (0U)
405 #define CARD_BUS_STRENGTH_1 (1U)
406 #define CARD_BUS_STRENGTH_2 (2U)
407 #define CARD_BUS_STRENGTH_3 (3U)
408 #define CARD_BUS_STRENGTH_4 (4U)
409 #define CARD_BUS_STRENGTH_5 (5U)
410 #define CARD_BUS_STRENGTH_6 (6U)
411 #define CARD_BUS_STRENGTH_7 (7U)
412
413 #define HOST_STROBE_DLL_DELAY_TARGET (7U)
414 #define HOST_STROBE_DLL_DELAY_UPDATE_INTERVAL (4U)
415
416 /* function pointer define */
417 #define HOST_TRANSFER_FUNCTION usdhc_transfer_function_t
418 #define GET_HOST_CAPABILITY(base, capability) (USDHC_GetCapability(base, capability))
419 #define GET_HOST_STATUS(base) (USDHC_GetPresentStatusFlags(base))
420 #define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (USDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ))
421 #define HOST_ENABLE_CARD_CLOCK(base, enable)
422 #define HOST_FORCE_SDCLOCK_ON(base, enable) (USDHC_ForceClockOn(base, enable))
423 #define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (USDHC_SetDataBusWidth(base, busWidth))
424 #define HOST_SEND_CARD_ACTIVE(base, timeout) (USDHC_SetCardActive(base, timeout))
425 #define HOST_SWITCH_VOLTAGE180V(base, enable18v) (UDSHC_SelectVoltage(base, enable18v))
426 #define HOST_SWITCH_VOLTAGE120V(base, enable12v)
427 #define HOST_CONFIG_SD_IO(speed, strength) BOARD_SD_PIN_CONFIG(speed, strength)
428 #define HOST_CONFIG_MMC_IO(speed, strength) BOARD_MMC_PIN_CONFIG(speed, strength)
429 #define HOST_SWITCH_VCC_TO_180V()
430 #define HOST_SWITCH_VCC_TO_330V()
431
432 #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
433 #define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U)
434 #define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U)
435 #define HOST_AUTO_STANDARD_RETUNING_TIMER(base)
436 #define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag)
437 #define HOST_CHECK_TUNING_ERROR(base) (0U)
438 #define HOST_ADJUST_TUNING_DELAY(base, delay)
439 #else
440 #define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) \
441 (USDHC_EnableStandardTuning(base, HOST_STANDARD_TUNING_START, HOST_TUINIG_STEP, flag))
442 #define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (USDHC_GetExecuteStdTuningStatus(base))
443 #define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (USDHC_CheckStdTuningResult(base))
444 #define HOST_AUTO_STANDARD_RETUNING_TIMER(base) (USDHC_SetRetuningTimer(base, HOST_RETUNING_TIMER_COUNT))
445 #define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) (USDHC_EnableManualTuning(base, flag))
446 #define HOST_ADJUST_TUNING_DELAY(base, delay) (USDHC_AdjustDelayForManualTuning(base, delay))
447 #define HOST_AUTO_TUNING_ENABLE(base, flag) (USDHC_EnableAutoTuning(base, flag))
448 #define HOST_CHECK_TUNING_ERROR(base) (USDHC_CheckTuningError(base))
449 #endif
450
451 #define HOST_AUTO_TUNING_CONFIG(base) (USDHC_EnableAutoTuningForCmdAndData(base))
452 #define HOST_RESET_TUNING(base, timeout) \
453 { \
454 (USDHC_Reset(base, kUSDHC_ResetTuning | kUSDHC_ResetData | kUSDHC_ResetCommand, timeout)); \
455 }
456
457 #define HOST_ENABLE_DDR_MODE(base, flag) (USDHC_EnableDDRMode(base, flag, 1U))
458
459 #if FSL_FEATURE_USDHC_HAS_HS400_MODE
460 #define HOST_ENABLE_HS400_MODE(base, flag) (USDHC_EnableHS400Mode(base, flag))
461 #define HOST_RESET_STROBE_DLL(base) (USDHC_ResetStrobeDLL(base))
462 #define HOST_ENABLE_STROBE_DLL(base, flag) (USDHC_EnableStrobeDLL(base, flag))
463 #define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval) (USDHC_ConfigStrobeDLL(base, delay, updateInterval))
464 #define HOST_GET_STROBE_DLL_STATUS (base)(USDHC_GetStrobeDLLStatus(base))
465 #else
466 #define HOST_ENABLE_HS400_MODE(base, flag)
467 #define HOST_RESET_STROBE_DLL(base)
468 #define HOST_ENABLE_STROBE_DLL(base, flag)
469 #define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval)
470 #define HOST_GET_STROBE_DLL_STATUS(base)
471 #endif
472
473 /* sd card power */
474 #define HOST_INIT_SD_POWER() BOARD_USDHC_SDCARD_POWER_CONTROL_INIT()
475 #define HOST_ENABLE_SD_POWER(enable) BOARD_USDHC_SDCARD_POWER_CONTROL(enable)
476 /* mmc card power */
477 #define HOST_INIT_MMC_POWER() BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT()
478 #define HOST_ENABLE_MMC_POWER(enable) BOARD_USDHC_MMCCARD_POWER_CONTROL(enable)
479 /* sd card detect */
480 #define HOST_CARD_DETECT_STATUS() BOARD_USDHC_CD_STATUS()
481 #define HOST_CARD_DETECT_INIT() BOARD_USDHC_CD_GPIO_INIT()
482 #define HOST_CARD_DETECT_INTERRUPT_STATUS() BOARD_USDHC_CD_INTERRUPT_STATUS()
483 #define HOST_CARD_DETECT_INTERRUPT_CLEAR(flag) BOARD_USDHC_CD_CLEAR_INTERRUPT(flag)
484 #define HOST_CARD_DETECT_INTERRUPT_HANDLER BOARD_USDHC_CD_PORT_IRQ_HANDLER
485 #define HOST_CARD_DETECT_IRQ BOARD_USDHC_CD_PORT_IRQ
486 /* define card detect pin voltage level when card inserted */
487 #if defined BOARD_USDHC_CARD_INSERT_CD_LEVEL
488 #define HOST_CARD_INSERT_CD_LEVEL BOARD_USDHC_CARD_INSERT_CD_LEVEL
489 #else
490 #define HOST_CARD_INSERT_CD_LEVEL (0U)
491 #endif
492 #define HOST_ENABLE_TUNING_FLAG(data) (data.executeTuning = true)
493 /*! @brief USDHC host capability*/
494 enum _host_capability
495 {
496 kHOST_SupportAdma = kUSDHC_SupportAdmaFlag,
497 kHOST_SupportHighSpeed = kUSDHC_SupportHighSpeedFlag,
498 kHOST_SupportDma = kUSDHC_SupportDmaFlag,
499 kHOST_SupportSuspendResume = kUSDHC_SupportSuspendResumeFlag,
500 kHOST_SupportV330 = kUSDHC_SupportV330Flag, /* this define should depend on your board config */
501 kHOST_SupportV300 = kUSDHC_SupportV300Flag, /* this define should depend on your board config */
502 #if defined(BOARD_SD_SUPPORT_180V) && !BOARD_SD_SUPPORT_180V
503 kHOST_SupportV180 = HOST_NOT_SUPPORT, /* this define should depend on you board config */
504 #else
505 kHOST_SupportV180 = kUSDHC_SupportV180Flag, /* this define should depend on you board config */
506 #endif
507 kHOST_SupportV120 = HOST_NOT_SUPPORT,
508 kHOST_Support4BitBusWidth = kUSDHC_Support4BitFlag,
509 #if defined(BOARD_MMC_SUPPORT_8BIT_BUS)
510 #if BOARD_MMC_SUPPORT_8BIT_BUS
511 kHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag,
512 #else
513 kHOST_Support8BitBusWidth = HOST_NOT_SUPPORT,
514 #endif
515 #else
516 kHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag,
517 #endif
518 kHOST_SupportDDR50 = kUSDHC_SupportDDR50Flag,
519 kHOST_SupportSDR104 = kUSDHC_SupportSDR104Flag,
520 kHOST_SupportSDR50 = kUSDHC_SupportSDR50Flag,
521 kHOST_SupportHS200 = kUSDHC_SupportSDR104Flag,
522 #if FSL_FEATURE_USDHC_HAS_HS400_MODE
523 kHOST_SupportHS400 = HOST_SUPPORT
524 #else
525 kHOST_SupportHS400 = HOST_NOT_SUPPORT,
526 #endif
527 };
528
529 /* Endian mode. */
530 #define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle
531
532 /* DMA mode */
533 #define USDHC_DMA_MODE kUSDHC_DmaModeAdma2
534 /* address align */
535 #define HOST_DMA_BUFFER_ADDR_ALIGN (USDHC_ADMA2_ADDRESS_ALIGN)
536
537 /* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */
538 #define USDHC_READ_WATERMARK_LEVEL (0x80U)
539 #define USDHC_WRITE_WATERMARK_LEVEL (0x80U)
540
541 /* ADMA table length united as word.
542 *
543 * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time.
544 * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set.
545 */
546 #define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */
547 #define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
548 #define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */
549 #define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */
550 #define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */
551
552 #endif
553
554 /*! @brief host Endian mode
555 * corresponding to driver define
556 */
557 enum _host_endian_mode
558 {
559 kHOST_EndianModeBig = 0U, /*!< Big endian mode */
560 kHOST_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */
561 kHOST_EndianModeLittle = 2U, /*!< Little endian mode */
562 };
563
564 #define EVENT_TIMEOUT_TRANSFER_COMPLETE (1000U)
565 #define EVENT_TIMEOUT_CARD_DETECT (~0U)
566
567 /*******************************************************************************
568 * API
569 ******************************************************************************/
570 #if defined(__cplusplus)
571 extern "C" {
572 #endif
573
574 /*!
575 * @name adaptor function
576 * @{
577 */
578
579 /*!
580 * @brief host not support function, this function is used for host not support feature
581 * @param void parameter ,used to avoid build warning
582 * @retval kStatus_Fail ,host do not suppport
583 */
HOST_NotSupport(void * parameter)584 static inline status_t HOST_NotSupport(void *parameter)
585 {
586 parameter = parameter;
587 return kStatus_Success;
588 }
589
590 /*!
591 * @brief Detect card insert, only need for SD cases.
592 * @param hostBase the pointer to host base address
593 * @retval kStatus_Success detect card insert
594 * @retval kStatus_Fail card insert event fail
595 */
596 status_t CardInsertDetect(HOST_TYPE *hostBase);
597
598 /*!
599 * @brief Init host controller.
600 * @param host the pointer to host structure in card structure.
601 * @retval kStatus_Success host init success
602 * @retval kStatus_Fail event fail
603 */
604 status_t HOST_Init(void *host);
605
606 /*!
607 * @brief reset host controller.
608 * @param host base address.
609 */
610 void HOST_Reset(HOST_TYPE *hostBase);
611
612 /*!
613 * @brief Deinit host controller.
614 * @param host the pointer to host structure in card structure.
615 */
616 void HOST_Deinit(void *host);
617
618 /* @} */
619
620 #if defined(__cplusplus)
621 }
622 #endif
623
624 #endif
625