1 /** 2 ****************************************************************************** 3 * @file ft32f0xx_rcc.h 4 * @author FMD AE 5 * @brief This file contains all the functions prototypes for the RCC 6 * firmware library. 7 * @version V1.0.0 8 * @data 2021-07-01 9 ****************************************************************************** 10 */ 11 12 13 /* Define to prevent recursive inclusion -------------------------------------*/ 14 #ifndef __FT32F0XX_RCC_H 15 #define __FT32F0XX_RCC_H 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /* Includes ------------------------------------------------------------------*/ 22 #include "ft32f0xx.h" 23 24 25 /** @addtogroup RCC 26 * @{ 27 */ 28 29 /* Exported types ------------------------------------------------------------*/ 30 31 typedef struct 32 { 33 uint32_t SYSCLK_Frequency; 34 uint32_t HCLK_Frequency; 35 uint32_t PCLK_Frequency; 36 uint32_t ADCCLK_Frequency; 37 uint32_t CECCLK_Frequency; 38 uint32_t I2C1CLK_Frequency; 39 uint32_t USART1CLK_Frequency; 40 uint32_t USART2CLK_Frequency; 41 uint32_t USART3CLK_Frequency; 42 uint32_t USBCLK_Frequency; 43 }RCC_ClocksTypeDef; 44 45 /* Exported constants --------------------------------------------------------*/ 46 47 /** @defgroup RCC_Exported_Constants 48 * @{ 49 */ 50 51 /** @defgroup RCC_HSE_configuration 52 * @{ 53 */ 54 55 #define RCC_HSE_OFF ((uint8_t)0x00) 56 #define RCC_HSE_ON ((uint8_t)0x01) 57 #define RCC_HSE_Bypass ((uint8_t)0x05) 58 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 59 ((HSE) == RCC_HSE_Bypass)) 60 61 /** 62 * @} 63 */ 64 65 /** @defgroup RCC_PLL_Clock_Source 66 * @{ 67 */ 68 69 #define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2 70 #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */ 71 #define RCC_PLLSource_HSE RCC_CFGR_PLLSRC_HSE_PREDIV 72 #define RCC_PLLSource_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV 73 #define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV 74 75 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ 76 ((SOURCE) == RCC_PLLSource_HSI48) || \ 77 ((SOURCE) == RCC_PLLSource_HSI) || \ 78 ((SOURCE) == RCC_PLLSource_HSE) || \ 79 ((SOURCE) == RCC_PLLSource_PREDIV1)) 80 /** 81 * @} 82 */ 83 84 /** @defgroup RCC_PLL_Multiplication_Factor 85 * @{ 86 */ 87 88 #define RCC_PLLMul_2 RCC_CFGR_PLLMULL2 89 #define RCC_PLLMul_3 RCC_CFGR_PLLMULL3 90 #define RCC_PLLMul_4 RCC_CFGR_PLLMULL4 91 #define RCC_PLLMul_5 RCC_CFGR_PLLMULL5 92 #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6 93 #define RCC_PLLMul_7 RCC_CFGR_PLLMULL7 94 #define RCC_PLLMul_8 RCC_CFGR_PLLMULL8 95 #define RCC_PLLMul_9 RCC_CFGR_PLLMULL9 96 #define RCC_PLLMul_10 RCC_CFGR_PLLMULL10 97 #define RCC_PLLMul_11 RCC_CFGR_PLLMULL11 98 #define RCC_PLLMul_12 RCC_CFGR_PLLMULL12 99 #define RCC_PLLMul_13 RCC_CFGR_PLLMULL13 100 #define RCC_PLLMul_14 RCC_CFGR_PLLMULL14 101 #define RCC_PLLMul_15 RCC_CFGR_PLLMULL15 102 #define RCC_PLLMul_16 RCC_CFGR_PLLMULL16 103 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ 104 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 105 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 106 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 107 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ 108 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ 109 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ 110 ((MUL) == RCC_PLLMul_16)) 111 /** 112 * @} 113 */ 114 115 /** @defgroup RCC_PREDIV1_division_factor 116 * @{ 117 */ 118 #define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1 119 #define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2 120 #define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3 121 #define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4 122 #define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5 123 #define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6 124 #define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7 125 #define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8 126 #define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9 127 #define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10 128 #define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11 129 #define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12 130 #define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13 131 #define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14 132 #define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15 133 #define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16 134 135 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ 136 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ 137 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ 138 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ 139 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ 140 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ 141 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ 142 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) 143 /** 144 * @} 145 */ 146 147 /** @defgroup RCC_System_Clock_Source 148 * @{ 149 */ 150 151 #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI 152 #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE 153 #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL 154 #define RCC_SYSCLKSource_HSI48 RCC_CFGR_SW_HSI48 155 156 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 157 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 158 ((SOURCE) == RCC_SYSCLKSource_HSI48) || \ 159 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 160 /** 161 * @} 162 */ 163 164 /** @defgroup RCC_AHB_Clock_Source 165 * @{ 166 */ 167 168 #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 169 #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 170 #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 171 #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 172 #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 173 #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 174 #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 175 #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 176 #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 177 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 178 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 179 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 180 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 181 ((HCLK) == RCC_SYSCLK_Div512)) 182 /** 183 * @} 184 */ 185 186 /** @defgroup RCC_APB_Clock_Source 187 * @{ 188 */ 189 190 #define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1 191 #define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2 192 #define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4 193 #define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8 194 #define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16 195 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 196 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 197 ((PCLK) == RCC_HCLK_Div16)) 198 /** 199 * @} 200 */ 201 202 /** @defgroup RCC_ADC_clock_source 203 * @{ 204 */ 205 /* These defines are obsolete and kept for legacy purpose only. 206 Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */ 207 #define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000) 208 #define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000) 209 #define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000) 210 211 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \ 212 ((ADCCLK) == RCC_ADCCLK_PCLK_Div4)) 213 214 /** 215 * @} 216 */ 217 218 219 /** 220 * @} 221 */ 222 223 /** @defgroup RCC_I2C_clock_source 224 * @{ 225 */ 226 227 #define RCC_I2C1CLK_HSI ((uint32_t)0x00000000) 228 #define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW 229 230 #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK)) 231 232 /** 233 * @} 234 */ 235 236 /** @defgroup RCC_USB_clock_source 237 * @brief 238 * @{ 239 */ 240 241 #define RCC_USBCLK_HSI48 ((uint32_t)0x00000000) 242 #define RCC_USBCLK_PLLCLK RCC_CFGR3_USBSW 243 244 #define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK)) 245 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCC_USART_clock_source 251 * @{ 252 */ 253 254 #define RCC_USART1CLK_PCLK ((uint32_t)0x10000000) 255 #define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001) 256 #define RCC_USART1CLK_LSE ((uint32_t)0x10000002) 257 #define RCC_USART1CLK_HSI ((uint32_t)0x10000003) 258 259 #define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) 260 #define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) 261 #define RCC_USART2CLK_LSE ((uint32_t)0x20020000) 262 #define RCC_USART2CLK_HSI ((uint32_t)0x20030000) 263 264 #define RCC_USART3CLK_PCLK ((uint32_t)0x30000000) 265 #define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000) 266 #define RCC_USART3CLK_LSE ((uint32_t)0x30080000) 267 #define RCC_USART3CLK_HSI ((uint32_t)0x300C0000) 268 269 270 #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || \ 271 ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \ 272 ((USARTCLK) == RCC_USART1CLK_LSE) || \ 273 ((USARTCLK) == RCC_USART1CLK_HSI) || \ 274 ((USARTCLK) == RCC_USART2CLK_PCLK) || \ 275 ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \ 276 ((USARTCLK) == RCC_USART2CLK_LSE) || \ 277 ((USARTCLK) == RCC_USART2CLK_HSI)|| \ 278 ((USARTCLK) == RCC_USART3CLK_PCLK) || \ 279 ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \ 280 ((USARTCLK) == RCC_USART3CLK_LSE) || \ 281 ((USARTCLK) == RCC_USART3CLK_HSI)) 282 283 /** 284 * @} 285 */ 286 287 /** @defgroup RCC_Interrupt_Source 288 * @{ 289 */ 290 291 #define RCC_IT_LSIRDY ((uint8_t)0x01) 292 #define RCC_IT_LSERDY ((uint8_t)0x02) 293 #define RCC_IT_HSIRDY ((uint8_t)0x04) 294 #define RCC_IT_HSERDY ((uint8_t)0x08) 295 #define RCC_IT_PLLRDY ((uint8_t)0x10) 296 #define RCC_IT_HSI14RDY ((uint8_t)0x20) 297 #define RCC_IT_HSI48RDY ((uint8_t)0x40) 298 #define RCC_IT_CSS ((uint8_t)0x80) 299 300 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) 301 302 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 303 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 304 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \ 305 ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY)) 306 307 #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) 308 309 /** 310 * @} 311 */ 312 313 /** @defgroup RCC_LSE_Configuration 314 * @{ 315 */ 316 317 #define RCC_LSE_OFF ((uint32_t)0x00000000) 318 #define RCC_LSE_ON RCC_BDCR_LSEON 319 #define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP)) 320 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 321 ((LSE) == RCC_LSE_Bypass)) 322 /** 323 * @} 324 */ 325 326 /** @defgroup RCC_RTC_Clock_Source 327 * @{ 328 */ 329 330 #define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE 331 #define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI 332 #define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE 333 334 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 335 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 336 ((SOURCE) == RCC_RTCCLKSource_HSE_Div32)) 337 /** 338 * @} 339 */ 340 341 /** @defgroup RCC_LSE_Drive_Configuration 342 * @{ 343 */ 344 345 #define RCC_LSEDrive_Low ((uint32_t)0x00000000) 346 #define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0 347 #define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1 348 #define RCC_LSEDrive_High RCC_BDCR_LSEDRV 349 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ 350 ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) 351 /** 352 * @} 353 */ 354 355 /** @defgroup RCC_AHB_Peripherals 356 * @{ 357 */ 358 359 #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN 360 #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN 361 #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN 362 #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN 363 #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN 364 #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN 365 #define RCC_AHBPeriph_TS RCC_AHBENR_TSEN 366 #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN 367 #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN 368 #define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN 369 #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN 370 #define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN 371 372 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00)) 373 #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00)) 374 375 /** 376 * @} 377 */ 378 379 /** @defgroup RCC_APB2_Peripherals 380 * @{ 381 */ 382 383 #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN 384 #define RCC_APB2Periph_USART6 RCC_APB2ENR_USART6EN 385 #define RCC_APB2Periph_USART7 RCC_APB2ENR_USART7EN 386 #define RCC_APB2Periph_USART8 RCC_APB2ENR_USART8EN 387 #define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN 388 #define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN 389 #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN 390 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN 391 #define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN 392 #define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN 393 #define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN 394 #define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN 395 396 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A51E) == 0x00) && ((PERIPH) != 0x00)) 397 398 /** 399 * @} 400 */ 401 402 /** @defgroup RCC_APB1_Peripherals 403 * @{ 404 */ 405 406 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN 407 #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN 408 #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN 409 #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN 410 #define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN 411 #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN 412 #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN 413 #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN 414 #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN 415 #define RCC_APB1Periph_USART4 RCC_APB1ENR_USART4EN 416 #define RCC_APB1Periph_USART5 RCC_APB1ENR_USART5EN 417 #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN 418 #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN 419 #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN 420 #define RCC_APB1Periph_CAN RCC_APB1ENR_CANEN 421 #define RCC_APB1Periph_CRS RCC_APB1ENR_CRSEN 422 #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN 423 #define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN 424 #define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN 425 426 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8581B6CC) == 0x00) && ((PERIPH) != 0x00)) 427 /** 428 * @} 429 */ 430 431 /** @defgroup RCC_MCO_Clock_Source 432 * @{ 433 */ 434 435 #define RCC_MCOSource_NoClock ((uint8_t)0x00) 436 #define RCC_MCOSource_HSI14 ((uint8_t)0x01) 437 #define RCC_MCOSource_LSI ((uint8_t)0x02) 438 #define RCC_MCOSource_LSE ((uint8_t)0x03) 439 #define RCC_MCOSource_SYSCLK ((uint8_t)0x04) 440 #define RCC_MCOSource_HSI ((uint8_t)0x05) 441 #define RCC_MCOSource_HSE ((uint8_t)0x06) 442 #define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07) 443 #define RCC_MCOSource_HSI48 ((uint8_t)0x08) 444 #define RCC_MCOSource_PLLCLK ((uint8_t)0x87) 445 446 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \ 447 ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \ 448 ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \ 449 ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_HSI48) || \ 450 ((SOURCE) == RCC_MCOSource_PLLCLK) || ((SOURCE) == RCC_MCOSource_LSE)) 451 /** 452 * @} 453 */ 454 455 /** @defgroup RCC_MCOPrescaler 456 * @{ 457 */ 458 #if !defined (FT32F051) 459 #define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1 460 #define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2 461 #define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4 462 #define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8 463 #define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16 464 #define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32 465 #define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64 466 #define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128 467 468 #define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \ 469 ((PRESCALER) == RCC_MCOPrescaler_2) || \ 470 ((PRESCALER) == RCC_MCOPrescaler_4) || \ 471 ((PRESCALER) == RCC_MCOPrescaler_8) || \ 472 ((PRESCALER) == RCC_MCOPrescaler_16) || \ 473 ((PRESCALER) == RCC_MCOPrescaler_32) || \ 474 ((PRESCALER) == RCC_MCOPrescaler_64) || \ 475 ((PRESCALER) == RCC_MCOPrescaler_128)) 476 #endif /* FT32F051 */ 477 /** 478 * @} 479 */ 480 481 /** @defgroup RCC_Flag 482 * @{ 483 */ 484 #define RCC_FLAG_HSIRDY ((uint8_t)0x01) 485 #define RCC_FLAG_HSERDY ((uint8_t)0x11) 486 #define RCC_FLAG_PLLRDY ((uint8_t)0x19) 487 #define RCC_FLAG_LSERDY ((uint8_t)0x21) 488 #define RCC_FLAG_LSIRDY ((uint8_t)0x41) 489 #define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57) 490 #define RCC_FLAG_OBLRST ((uint8_t)0x59) 491 #define RCC_FLAG_PINRST ((uint8_t)0x5A) 492 #define RCC_FLAG_PORRST ((uint8_t)0x5B) 493 #define RCC_FLAG_SFTRST ((uint8_t)0x5C) 494 #define RCC_FLAG_IWDGRST ((uint8_t)0x5D) 495 #define RCC_FLAG_WWDGRST ((uint8_t)0x5E) 496 #define RCC_FLAG_LPWRRST ((uint8_t)0x5F) 497 #define RCC_FLAG_HSI14RDY ((uint8_t)0x61) 498 #define RCC_FLAG_HSI48RDY ((uint8_t)0x71) 499 500 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 501 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 502 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \ 503 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 504 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || \ 505 ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \ 506 ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_HSI48RDY)|| \ 507 ((FLAG) == RCC_FLAG_V18PWRRSTF)) 508 509 #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 510 #define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 511 512 /** 513 * @} 514 */ 515 516 /** 517 * @} 518 */ 519 520 /* Exported macro ------------------------------------------------------------*/ 521 /* Exported functions ------------------------------------------------------- */ 522 523 /* Function used to set the RCC clock configuration to the default reset state */ 524 void RCC_DeInit(void); 525 526 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ 527 void RCC_HSEConfig(uint8_t RCC_HSE); 528 ErrorStatus RCC_WaitForHSEStartUp(void); 529 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 530 void RCC_HSICmd(FunctionalState NewState); 531 void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue); 532 void RCC_HSI14Cmd(FunctionalState NewState); 533 void RCC_HSI14ADCRequestCmd(FunctionalState NewState); 534 void RCC_LSEConfig(uint32_t RCC_LSE); 535 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive); 536 void RCC_LSICmd(FunctionalState NewState); 537 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); 538 void RCC_PLLCmd(FunctionalState NewState); 539 void RCC_HSI48Cmd(FunctionalState NewState); 540 uint32_t RCC_GetHSI48CalibrationValue(void); 541 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div); 542 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 543 #ifdef FT32F051 544 void RCC_MCOConfig(uint8_t RCC_MCOSource); 545 #else 546 void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler); 547 #endif /* FT32F051 */ 548 549 /* System, AHB and APB busses clocks configuration functions ******************/ 550 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 551 uint8_t RCC_GetSYSCLKSource(void); 552 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 553 void RCC_PCLKConfig(uint32_t RCC_HCLK); 554 void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete. 555 For proper ADC clock selection, refer to 556 ADC_ClockModeConfig() in the ADC driver */ 557 void RCC_CECCLKConfig(uint32_t RCC_CECCLK); 558 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK); 559 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK); 560 void RCC_USBCLKConfig(uint32_t RCC_USBCLK); 561 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 562 563 /* Peripheral clocks configuration functions **********************************/ 564 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 565 void RCC_RTCCLKCmd(FunctionalState NewState); 566 void RCC_BackupResetCmd(FunctionalState NewState); 567 568 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 569 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 570 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 571 572 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 573 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 574 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 575 576 /* Interrupts and flags management functions **********************************/ 577 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 578 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 579 void RCC_ClearFlag(void); 580 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 581 void RCC_ClearITPendingBit(uint8_t RCC_IT); 582 583 #ifdef __cplusplus 584 } 585 #endif 586 587 #endif /* __FT32F0XX_RCC_H */ 588 589 /** 590 * @} 591 */ 592 593 /** 594 * @} 595 */ 596 597 /************************ (C) COPYRIGHT FMD *****END OF FILE****/ 598