1 /*
2  * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
3  *
4  * SPDX-License-Identifier: Apache-2.0.
5  *
6  * @Date: 2021-04-07 09:53:07
7  * @LastEditTime: 2021-05-26 15:39:16
8  * @Description:  This files is for pin mux
9  *
10  * @Modify History:
11  *  Ver   Who        Date         Changes
12  * ----- ------     --------    --------------------------------------
13  */
14 
15 #ifndef FT_BSP_MUX_H
16 #define FT_BSP_MUX_H
17 
18 #ifdef __cplusplus
19 extern "C"
20 {
21 #endif
22 
23 #include "ft_types.h"
24 
25 /* pad pin multi-function demu */
26 #define FT_PIN_DEMUX_BASE 0x28180000
27 #define FT_PIN_DEMUX_REG200_OFFSET 0x200
28 #define FT_PIN_DEMUX_REG204_OFFSET 0x204
29 #define FT_PIN_DEMUX_REG208_OFFSET 0x208
30 #define FT_PIN_DEMUX_REG210_OFFSET 0x210
31 #define FT_PIN_DEMUX_REG214_OFFSET 0x214
32 
33 /* i2c mux function option */
34 #define I2C1_SCL_PIN_REG200_MASK ((u32)0x3 << 28) /* all_pll_lock_pad [29:28] */
35 #define I2C1_SCL_PIN_REG200_BIT ((u32)0x2 << 28)
36 #define I2C1_SDA_PIN_REG200_MASK ((u32)0x3 << 24) /* cru_clk_obv_pad [25:24] */
37 #define I2C1_SDA_PIN_REG200_BIT ((u32)0x2 << 24)
38 #define I2C2_SCL_PIN_REG204_MASK ((u32)0x3 << 8) /* swdo_swj_pad [9: 8] */
39 #define I2C2_SCL_PIN_REG204_BIT ((u32)0x2 << 8)
40 #define I2C2_SDA_PIN_REG204_MASK ((u32)0x3 << 6) /* tdo_swj_pad [7: 6] */
41 #define I2C2_SDA_PIN_REG204_BIT ((u32)0x2 << 6)
42 #define I2C3_SCL_PIN_REG204_MASK ((u32)0x3 << 0) /* hdt_mb_done_state_pad [1 : 0] */
43 #define I2C3_SCL_PIN_REG204_BIT ((u32)0x2 << 0)
44 #define I2C3_SDA_PIN_REG208_MASK ((u32)0x3 << 30) /* hdt_mb_fail_state_pad [31 : 30] */
45 #define I2C3_SDA_PIN_REG208_BIT ((u32)0x2 << 30)
46 
47 #define SPI1_PORTA5_PIN_REG208_BIT ((u32)0x1 << 16)
48 
49 #define SPI1_CSN0_PIN_REG210_MASK ((u32)0x3 << 0) /* uart_2_rxd_pad [1 : 0] */
50 #define SPI1_CSN0_PIN_REG210_BIT ((u32)0x1 << 0)
51 #define SPI1_SCK_PIN_REG214_MASK ((u32)0x3 << 28) /* uart_2_txd_pad [29 : 28] */
52 #define SPI1_SCK_PIN_REG214_BIT ((u32)0x1 << 28)
53 #define SPI1_SO_PIN_REG214_MASK ((u32)0x3 << 24) /* uart_3_rxd_pad [25 : 24] */
54 #define SPI1_SO_PIN_REG214_BIT ((u32)0x1 << 24)
55 #define SPI1_SI_PIN_REG214_MASK ((u32)0x3 << 20) /* uart_3_txd_pad [21 : 20] */
56 #define SPI1_SI_PIN_REG214_BIT ((u32)0x1 << 20)
57 
58 /* i2c ctrl instance */
59 #define I2C0_ID 0
60 #define I2C1_ID 1
61 #define I2C2_ID 2
62 #define I2C3_ID 3
63 
64 /* spi ctrl instance */
65 #define SPI0_ID 0
66 #define SPI1_ID 1
67 
68     void Ft_setI2cMux(FT_IN u32 I2cId);
69     void Ft_setSpiMux(FT_IN u32 SpiId);
70 
71 #ifdef __cplusplus
72 }
73 #endif
74 
75 #endif
76