1 /* 2 * @ : Copyright (c) 2021 Phytium Information Technology, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0. 5 * 6 * Date: 2021-03-30 14:57:03 7 * @LastEditTime: 2021-05-24 14:35:00 8 * Description: definitions of BSP parameters 9 * Modify History: 10 * * * Ver Who Date Changes 11 * * ----- ------ -------- ---------------------------------------------- 12 * 1.00 Huanghe 2021/3/1 init 13 */ 14 15 #ifndef FT_PARAMETERS_H 16 #define FT_PARAMETERS_H 17 18 /* Device register address */ 19 #define FT_DEV_BASE_ADDR 0x28000000 20 #define FT_DEV_END_ADDR 0x2FFFFFFF 21 22 /******** UART ************/ 23 24 #define FT_UART_NUM 4 25 #define FT_UART_REG_LENGTH 0x18000 26 27 #define FT_UART0_ID 0 28 #define FT_UART0_BASE_ADDR 0x28000000 29 #define FT_UART0_CLK_FREQ_HZ 48000000 30 31 #define FT_UART1_ID 1 32 #define FT_UART1_BASE_ADDR 0x28001000 33 #define FT_UART1_CLK_FREQ_HZ 48000000 34 35 #define FT_UART2_ID 2 36 #define FT_UART2_BASE_ADDR 0x28002000 37 #define FT_UART2_CLK_FREQ_HZ 48000000 38 39 #define FT_UART3_BASE_ADDR 0x28003000 40 #define FT_UART3_ID 3 41 #define FT_UART3_CLK_FREQ_HZ 48000000 42 43 #define FT_STDOUT_BASEADDRESS FT_UART1_BASE_ADDR 44 #define FT_STDIN_BASEADDRESS FT_UART1_BASE_ADDR 45 46 /****** GIC v3 *****/ 47 #define FT_GICV3_INSTANCES_NUM 1U 48 #define GICV3_REG_LENGTH 0x00009000 49 50 /* 51 * The maximum priority value that can be used in the GIC. 52 */ 53 #define GICV3_MAX_INTR_PRIO_VAL 240U 54 #define GICV3_INTR_PRIO_MASK 0x000000f0U 55 56 #define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ 57 #define SGI_INT_MAX 16 58 #define SPI_START_INT_NUM 32 /* SPI start at ID32 */ 59 #define PPI_START_INT_NUM 16 /* PPI start at ID16 */ 60 #define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ 61 62 #define FT_GICV3_BASEADDRESS 0x29900000U 63 #define FT_GICV3_DISTRIBUTOR_BASEADDRESS (FT_GICV3_BASEADDRESS + 0) 64 #define FT_GICV3_RD_BASEADDRESS (FT_GICV3_BASEADDRESS + 0x80000U) 65 #define FT_GICV3_SGI_BASEADDRESS (FT_GICV3_RD_BASEADDRESS + (1U << 16)) 66 67 #define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM 68 69 /** Gmac **/ 70 #define FT_GMAC_INSTANCES_NUM 2U 71 #define FT_GMAC_REG_LENGTH 0x00009000 72 73 #define FT_GMAC_COMMON_ADDR 0x2820B000U 74 75 #define FT_GMAC0_ID 0 76 #define FT_GMAC0_BASEADDR 0x2820C000U 77 #define FT_GMAC0_DEFAULT_ADDR \ 78 { \ 79 0x11, 0x1c, 0x2c, 0x5c, 0x66, 0x88 \ 80 } 81 82 #define FT_GMAC1_ID 1 83 #define FT_GMAC1_BASEADDR 0x28210000U 84 85 /** @defgroup ENET_Buffers_setting 86 * @{ 87 */ 88 #define GMAC_MAX_PACKET_SIZE 1600 /* GMAC_HEADER + GMAC_EXTRA + VLAN_TAG + MAX_GMAC_PAYLOAD + GMAC_CRC */ 89 #define GMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 90 #define GMAC_CRC 4 /* Gmac CRC */ 91 #define GMAC_EXTRA 2 /* Extra bytes in some cases */ 92 #define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ 93 #define MIN_GMAC_PAYLOAD 46 /* Minimum Gmac payload size */ 94 #define MAX_GMAC_PAYLOAD 1500 /* Maximum Gmac payload size */ 95 #define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ 96 #define RX_DESCNUM 1024U /* Rx buffers of size GMAC_MAX_PACKET_SIZE */ 97 #define TX_DESCNUM 1024U /* Tx buffers of size GMAC_MAX_PACKET_SIZE */ 98 99 #define PHY_USING_AR8035 100 101 #define GMAC0_ISRNUM 81 102 #define GMAC0_ISRPRIORITY 0 103 104 #define GMAC1_ISRNUM 82 105 #define GMAC1_ISRPRIORITY 0 106 107 /* SDC */ 108 #define FT_SDC_NUM 1 109 #define FT_SDC_INSTANCE 0 110 #define FT_SDC_BASEADDR 0x28207C00U 111 #define FT_SDC_REG_LENGTH 0x4000 112 #define FT_SDC_FREQ 600000000 113 114 /* pin MUX/DEMUX */ 115 116 #define FT_PIN_MUX_BASEADDR 0x28180000 117 #define FT_PIN_MUX_REG_LENGTH 0x10000 118 119 /* CAN */ 120 121 #define FT_CAN_NUM 3 122 #define FT_CAN_REG_LENGTH 0x1000 123 #define FT_CAN0_BASEADDR 0x28207000 124 #define FT_CAN1_BASEADDR 0x28207400 125 #define FT_CAN2_BASEADDR 0x28207800 126 #define FT_CAN0_IRQNUM 119 127 #define FT_CAN1_IRQNUM 123 128 #define FT_CAN2_IRQNUM 124 129 #define FT_CAN_BAUDRATE 1000000 /* 1M */ 130 #define FT_CAN_CLK 600000000 131 132 /* pci */ 133 134 #define FT_PCI_CONFIG_BASEADDR 0x40000000 135 #define FT_PCI_CONFIG_REG_LENGTH 0x10000000 136 137 #define FT_PCI_IO_CONFIG_BASEADDR 0x50000000 138 #define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000 139 140 #define FT_PCI_MEM32_BASEADDR 0x58000000 141 #define FT_PCI_MEM32_REG_LENGTH 0x27000000 142 143 /* qspi */ 144 #define FT_QSPI_NUM 1U 145 #define FT_QSPI_INSTANCE 0 146 #define FT_QSPI_MAX_CS_NUM 4 147 #define FT_QSPI_BASEADDR 0x28014000 148 149 #define FT_QSPI_FLASH_CAP_4MB 0 150 #define FT_QSPI_FLASH_CAP_8MB 1 151 #define FT_QSPI_FLASH_CAP_16MB 2 152 #define FT_QSPI_FLASH_CAP_32MB 3 153 #define FT_QSPI_FLASH_CAP_64MB 4 154 #define FT_QSPI_FLASH_CAP_128MB 5 155 #define FT_QSPI_FLASH_CAP_256MB 6 156 157 #define FT_QSPI_ADDR_SEL_3 0 158 #define FT_QSPI_ADDR_SEL_4 1 159 160 #define FT_QSPI_SCK_DIV_128 0 161 #define FT_QSPI_SCK_DIV_2 1 162 #define FT_QSPI_SCK_DIV_4 2 163 #define FT_QSPI_SCK_DIV_8 3 164 #define FT_QSPI_SCK_DIV_16 4 165 #define FT_QSPI_SCK_DIV_32 5 166 #define FT_QSPI_SCK_DIV_64 6 167 168 #define FT_QSPI_TRANSFER_1_1_1 0 169 #define FT_QSPI_TRANSFER_1_1_2 1 170 #define FT_QSPI_TRANSFER_1_1_4 2 171 #define FT_QSPI_TRANSFER_1_2_2 3 172 #define FT_QSPI_TRANSFER_1_4_4 4 173 #define FT_QSPI_TRANSFER_2_2_2 5 174 #define FT_QSPI_TRANSFER_4_4_4 6 175 176 /* smp */ 177 178 #define FT_SMP_EN 179 180 #endif // ! 181