1 /* 2 * @ : Copyright (c) 2021 Phytium Information Technology, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0. 5 * 6 * @Date: 2021-03-31 14:59:20 7 * @LastEditTime: 2021-04-19 17:04:44 8 * @Description: This files is for implementation of sd ctrl 9 * 10 * @Modify History: * * Ver Who Date Changes 11 * ----- ------ -------- -------------------------------------- 12 */ 13 14 #ifndef FTSDCTRL_H 15 #define FTSDCTRL_H 16 #include "ft_types.h" 17 #include "ft_error_code.h" 18 19 /* sd ctrl module debug tag */ 20 #define FT_SD_CTRL_DEBUG_TAG "FT_SD_CTRL" 21 22 /* definition of errcode for sd module */ 23 #define FTSDC_SUCCESS FST_SUCCESS /* 成功 */ 24 #define FTSDC_FAILURE FT_MAKE_ERRCODE(errModeSdCtrl, errBspGeneral, FST_FAILURE) /* Normal */ 25 #define FTSDC_TIMEOUT FT_MAKE_ERRCODE(errModeSdCtrl, errBspGeneral, FST_TIMEOUT) /* Timeout */ 26 #define FTSDC_EILSEQ FT_MAKE_ERRCODE(errModeSdCtrl, errBspGeneral, FST_EILSEQ) /* Illegal byte sequence. */ 27 #define FTSDC_INVALID_PARAM FT_MAKE_ERRCODE(errModeSdCtrl, errBspGeneral, FST_INVALID_PARAM) /* Illegal byte sequence. */ 28 29 /* type of response to sd cmds */ 30 #define FTSDCTRL_CMD_RES_NONE 0 /* No response */ 31 #define FTSDCTRL_CMD_RES_LONG 1 /* The response length is long, code length is 128 */ 32 #define FTSDCTRL_CMD_RES_SHORT 2 /* The response length is short, code length is 32 */ 33 34 /* irq enable bits */ 35 #define FTSDCTRL_DATA_WRITE_IRQ_MASK 0x1 36 #define FTSDCTRL_DATA_READ_IRQ_MASK 0x2 37 #define FTSDCTRL_CMD_IRQ_MASK 0x4 38 39 /* type of irq callback */ 40 typedef enum 41 { 42 FTSDCTRL_DMADATAIRQID = 0x1U, /* Select dma interrupt */ 43 FTSDCTRL_CMDIRQID = 0x2U, /* Select cmd interrupt */ 44 FTSDCTRL_ERRORIRQID = 0x3U, /* Select error interrupt */ 45 } FSdCtrl_IrqCallbackSelect_t; 46 47 /* normal irq enable bits for NORMAL_INT_EN_REG_OFFSET */ 48 typedef enum 49 { 50 NORMAL_IRQ_CC = 1, /* Command completion interrupt */ 51 NORMAL_IRQ_CR = 2, /* Card removal interrupt */ 52 NORMAL_IRQ_EI = 4 /* Command error interrupt */ 53 } FSdCtrl_NormalIrqSelect_t; 54 55 /* error irq enable bits for ERROR_INT_EN_REG_OFFSET */ 56 typedef enum 57 { 58 ERROR_IRQ_CTE = 1, /* Command timeout error interrupted */ 59 ERROR_IRQ_CCRCE = 2, /* Command CRC error interrupt */ 60 ERROR_IRQ_CIR = 4, /* Command index error interrupt */ 61 ERROR_IRQ_CNR = 8 /* Command response error interrupted */ 62 } FSdCtrl_ErrorIrqSelect_t; 63 64 /* data trans irq bits for BD_ISR_EN_REG_OFFSET */ 65 typedef enum 66 { 67 BD_IRQ_TRS = 1, /* DMA transmission has been interrupted */ 68 BD_IRQ_DTE = 2, /* Timeout interrupt */ 69 BD_IRQ_CMDE = 4, /* Command response error interrupted */ 70 BD_IRQ_TRE = 8, /* Command response error interrupt CRC response error interrupt */ 71 BD_IRQ_NRCRC = 0x10, /* No CRC response interruption */ 72 BD_IRQ_DATFRAX = 0x20, /* AXI bus forces to release interrupts */ 73 BD_IRQ_RESPE = 0x40, /* Read SD card operation, AXI BR channel complete interrupt */ 74 BD_IRQ_DAIS = 0x80, /* DMA error interrupt */ 75 } FSdCtrl_BdIrqSelect; 76 77 /* types of irq */ 78 typedef enum 79 { 80 FTSDC_NORMAL_ISR = 0U, 81 FTSDC_BD_ISR, 82 FTSDC_ERROR_ISR 83 } FSdCtrl_IsrCallbackSelect_t; 84 85 /* voltage supply range type of SD Card follow POWER_CONTROLL_REG 86 */ 87 typedef enum 88 { 89 FSDC_HIGH_V = 0, /* SD card operate within the voltage range of 2.7-3.6 V */ 90 FSDC_DUAL_V, /* SD card operate within the Low Voltage Range (T.B.D) and 2.7-3.6 V */ 91 92 MAX_FSDC_VOLTAGE_TYPE 93 } FSdCtrl_VRangeType_t; 94 95 /* read-write property of SD Card */ 96 typedef enum 97 { 98 FSDC_RW_CARD = 0, 99 FSDC_RO_CARD, 100 101 MAX_FSDC_WR_CARD_TYPE 102 } FSdCtrl_WRType_t; 103 104 /* capacity type of SD Card */ 105 typedef enum 106 { 107 FSDC_SD_CARD = 0, 108 FSDC_SDHC_CARD, 109 FSDC_SDXC_CARD, 110 111 MAX_FSDC_CARD_CAPACITY_TYPE 112 } FSdCtrl_CapacityType_t; 113 114 /* speed class of SD Card */ 115 typedef enum 116 { 117 FSDC_CLASS0 = 0, 118 FSDC_CLASS2, 119 FSDC_CLASS4, 120 FSDC_CLASS6, 121 122 MAX_FSDC_CLASS_TYPE 123 } FSdCtrl_ClassType_t; 124 125 /** 126 * This typedef contains configuration information for the sd device. 127 */ 128 typedef struct 129 { 130 u32 instanceId; /* Unique ID of device */ 131 u32 baseAddress; /* Base address of the device */ 132 u32 inputClockHz; /* Input clock frequency */ 133 u32 cardDetect; /* Card Detect */ 134 u32 writeProtect; /* Write Protect */ 135 u32 busWidth; /* Bus Width */ 136 u32 dmaIrqNum; /* dma irq number */ 137 u32 normalIrqNum; /* normal irq number */ 138 u32 errIrqNum; /* error irq number */ 139 u8 workMode; /* Work mode for data transfers , 140 If the mask bit is 0, polling is used , 141 follow irq enable bits*/ 142 } FSdCtrl_Config_t; 143 144 typedef void (*FtsdCtrl_irqCallback_t)(void *args); 145 146 /* irq callback and iput args */ 147 typedef struct 148 { 149 FtsdCtrl_irqCallback_t pDmaDataCallback; /* DMA data interrupt function pointer */ 150 void *pDmaDataArgs; 151 152 FtsdCtrl_irqCallback_t pCmdCallback; /* Commond interrupt function pointer */ 153 void *pCmdArgs; 154 155 FtsdCtrl_irqCallback_t pErrorCallback; /* Error interrupt function pointer */ 156 void *pErrorArgs; 157 } FSdCtrl_IrqConfig_t; 158 159 typedef struct FtsdCtrl FtsdCtrl_t; 160 typedef void (*pFtsdCtrl_delayTimer_t)(ft_base_t delayUs); 161 typedef ft_error_t (*pFtsdCtrl_irqWaitCallback_t)(FtsdCtrl_t *FtsdCtrl); 162 163 /* ctrl instance of sd */ 164 struct FtsdCtrl 165 { 166 FSdCtrl_Config_t config; 167 u32 isReady; /* Device is initialized and ready */ 168 /*************reserved**************/ 169 FSdCtrl_VRangeType_t voltageType; 170 FSdCtrl_WRType_t writeReadType; 171 FSdCtrl_CapacityType_t capacityType; 172 FSdCtrl_ClassType_t speedClassType; 173 /*************reserved**************/ 174 FSdCtrl_IrqConfig_t irqConfig; 175 pFtsdCtrl_irqWaitCallback_t writeWaitCallback; /* function pointer .Used to determine whether the data transmission is complete*/ 176 pFtsdCtrl_irqWaitCallback_t readWaitCallback; /* function pointer .Used to determine whether the data received is complete*/ 177 pFtsdCtrl_irqWaitCallback_t cmdWaitCallback; /* function pointer . Used to determine whether the command is complete */ 178 }; 179 180 u32 FSdCtrl_PrepareCmdRaw(FT_IN u32 cmdIndex, FT_IN u32 rspType); 181 void FSdCtrl_WriteData(FT_INOUT FtsdCtrl_t *pFtsdCtrl, FT_IN UINTPTR dataAddr, FT_IN UINTPTR cmdArg, FT_IN u32 blkNum); 182 void FSdCtrl_ReadData(FT_INOUT FtsdCtrl_t *pFtsdCtrl, 183 FT_IN UINTPTR dataAddr, 184 FT_IN UINTPTR cardAddr, 185 FT_IN u32 blkNum); 186 ft_error_t FSdCtrl_WaitCmdEnd(FT_OUT FtsdCtrl_t *pFtsdCtrl, 187 FT_IN pFtsdCtrl_delayTimer_t pDelayTimer_fun, 188 FT_IN u32 rspType, 189 FT_OUT u32 *cmdRsp); 190 ft_error_t FSdCtrl_WaitReadDataEnd(FT_INOUT FtsdCtrl_t *pFtsdCtrl, 191 FT_IN pFtsdCtrl_delayTimer_t pDelayTimer_fun, 192 FT_IN u32 blkNum); 193 ft_error_t FSdCtrl_WaitWriteDataEnd(FT_INOUT FtsdCtrl_t *pFtsdCtrl, 194 FT_IN pFtsdCtrl_delayTimer_t pDelayTimer_fun, 195 FT_IN u32 blkNum); 196 197 void FSdCtrl_DoCmd(FT_INOUT FtsdCtrl_t *pFtsdCtrl, FT_IN u32 cmdIndex, FT_IN u32 rspType, u32 arg); 198 void FSdCtrl_DoACmd(FT_INOUT FtsdCtrl_t *pFtsdCtrl, 199 FT_IN u32 cmdIndex, 200 FT_IN u32 rspType, 201 u32 arg); 202 void FSdCtrl_NormalIrq(FT_INOUT FtsdCtrl_t *pFtsdCtrl); 203 void FSdCtrl_DmaIrq(FT_INOUT FtsdCtrl_t *pFtsdCtrl); 204 void FSdCtrl_ErrIrq(FT_INOUT FtsdCtrl_t *pFtsdCtrl); 205 bool_t FSdCtrl_CardDetect(FT_INOUT FtsdCtrl_t *pFtsdCtrl); 206 207 FSdCtrl_Config_t *FSdCtrl_LookupConfig(u32 instanceId); 208 /* This routine performs per device specific initialization of Phytium SDHC.*/ 209 ft_error_t FsdCtrl_Init(FT_INOUT FtsdCtrl_t *pFtsdCtrl); 210 void FSdCtrl_ClkFreqSetup(FT_INOUT FtsdCtrl_t *pFtsdCtrl, FT_IN u32 sdClk); 211 void FSdCtrl_ResetDma(FT_INOUT FtsdCtrl_t *pFtsdCtrl); 212 /* reset sd ctrl during init */ 213 void FSdCtrl_Reset(FT_INOUT FtsdCtrl_t *pFtsdCtrl, pFtsdCtrl_delayTimer_t fDelayTimer); 214 215 /* set irq call backs */ 216 ft_error_t FSdCtrl_SetHandler(FT_INOUT FtsdCtrl_t *pFtsdCtrl, FT_IN FSdCtrl_IrqCallbackSelect_t selectIndex, 217 void *FuncPtr, 218 void *Args); 219 220 /* register call-backs to determinate wheather write、read and cmd is complete */ 221 void FSdCtrl_WriteWaitRegister(FT_INOUT FtsdCtrl_t *pFtsdCtrl, FT_IN pFtsdCtrl_irqWaitCallback_t callBack); 222 void FSdCtrl_ReadWaitRegister(FT_INOUT FtsdCtrl_t *pFtsdCtrl, FT_IN pFtsdCtrl_irqWaitCallback_t callBack); 223 void FSdCtrl_CmdWaitRegister(FT_INOUT FtsdCtrl_t *pFtsdCtrl, FT_IN pFtsdCtrl_irqWaitCallback_t callBack); 224 void FSdCtrl_ErrWaitRegister(FT_INOUT FtsdCtrl_t *pFtsdCtrl, FT_IN pFtsdCtrl_irqWaitCallback_t callBack); 225 226 /* get irq status */ 227 u32 FSdCtrl_GetNormalIrqStatus(FT_INOUT FtsdCtrl_t *pFtsdCtrl); 228 u32 FSdCtrl_GetDataIrqStatus(FT_INOUT FtsdCtrl_t *pFtsdCtrl); 229 u32 FSdCtrl_GetErrorIrqStatus(FT_INOUT FtsdCtrl_t *pFtsdCtrl); 230 231 /* enable selected normal irq */ 232 void FSdCtrl_NormalIrqSet(FtsdCtrl_t *pFtsdCtrl, FT_IN FSdCtrl_NormalIrqSelect_t flgs); 233 void FSdCtrl_BdIrqSet(FtsdCtrl_t *pFtsdCtrl, FT_IN FSdCtrl_BdIrqSelect flgs); 234 235 #endif // 236