1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: gpio4_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for gpio4 module.
gpio4_iomux_config(void)34 void gpio4_iomux_config(void)
35 {
36 // Config gpio4.GPIO4_IO05 to pad GPIO19(P5)
37 // RGMII_INT_B
38 // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR(0x00000005);
39 // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR(0x0001B0B0);
40 // Mux Register:
41 // IOMUXC_SW_MUX_CTL_PAD_GPIO19(0x020E0220)
42 // SION [4] - Software Input On Field Reset: DISABLED
43 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
44 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
45 // ENABLED (1) - Force input path of pad.
46 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
47 // Select iomux modes to be used for pad.
48 // ALT0 (0) - Select instance: kpp signal: KEY_COL5
49 // ALT1 (1) - Select instance: enet signal: ENET_1588_EVENT0_OUT
50 // ALT2 (2) - Select instance: spdif signal: SPDIF_OUT
51 // ALT3 (3) - Select instance: ccm signal: CCM_CLKO1
52 // ALT4 (4) - Select instance: ecspi1 signal: ECSPI1_RDY
53 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO05
54 // ALT6 (6) - Select instance: enet signal: ENET_TX_ER
55 HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR(
56 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION_V(DISABLED) |
57 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE_V(ALT5));
58 // Pad Control Register:
59 // IOMUXC_SW_PAD_CTL_PAD_GPIO19(0x020E05F0)
60 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
61 // DISABLED (0) - CMOS input
62 // ENABLED (1) - Schmitt trigger input
63 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
64 // 100K_OHM_PD (0) - 100K Ohm Pull Down
65 // 47K_OHM_PU (1) - 47K Ohm Pull Up
66 // 100K_OHM_PU (2) - 100K Ohm Pull Up
67 // 22K_OHM_PU (3) - 22K Ohm Pull Up
68 // PUE [13] - Pull / Keep Select Field Reset: PULL
69 // KEEP (0) - Keeper Enabled
70 // PULL (1) - Pull Enabled
71 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
72 // DISABLED (0) - Pull/Keeper Disabled
73 // ENABLED (1) - Pull/Keeper Enabled
74 // ODE [11] - Open Drain Enable Field Reset: DISABLED
75 // Enables open drain of the pin.
76 // DISABLED (0) - Output is CMOS.
77 // ENABLED (1) - Output is Open Drain.
78 // SPEED [7:6] - Speed Field Reset: 100MHZ
79 // RESERVED0 (0) - Reserved
80 // 50MHZ (1) - Low (50 MHz)
81 // 100MHZ (2) - Medium (100 MHz)
82 // 200MHZ (3) - Maximum (200 MHz)
83 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
84 // HIZ (0) - HI-Z
85 // 240_OHM (1) - 240 Ohm
86 // 120_OHM (2) - 120 Ohm
87 // 80_OHM (3) - 80 Ohm
88 // 60_OHM (4) - 60 Ohm
89 // 48_OHM (5) - 48 Ohm
90 // 40_OHM (6) - 40 Ohm
91 // 34_OHM (7) - 34 Ohm
92 // SRE [0] - Slew Rate Field Reset: SLOW
93 // Slew rate control.
94 // SLOW (0) - Slow Slew Rate
95 // FAST (1) - Fast Slew Rate
96 HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR(
97 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS_V(ENABLED) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS_V(100K_OHM_PU) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE_V(PULL) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE_V(ENABLED) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE_V(DISABLED) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED_V(100MHZ) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE_V(40_OHM) |
104 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE_V(SLOW));
105
106 // Config gpio4.GPIO4_IO09 to pad KEY_ROW1(U6)
107 // MLB_INT_B
108 // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_WR(0x00000005);
109 // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR(0x0001B0B0);
110 // Mux Register:
111 // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1(0x020E025C)
112 // SION [4] - Software Input On Field Reset: DISABLED
113 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
114 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
115 // ENABLED (1) - Force input path of pad.
116 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
117 // Select iomux modes to be used for pad.
118 // ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS0
119 // ALT1 (1) - Select instance: enet signal: ENET_COL
120 // ALT2 (2) - Select instance: audmux signal: AUD5_RXD
121 // ALT3 (3) - Select instance: kpp signal: KEY_ROW1
122 // ALT4 (4) - Select instance: uart5 signal: UART5_RX_DATA
123 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO09
124 // ALT6 (6) - Select instance: usdhc2 signal: SD2_VSELECT
125 HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_WR(
126 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION_V(DISABLED) |
127 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE_V(ALT5));
128 // Pad Control Register:
129 // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1(0x020E0644)
130 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
131 // DISABLED (0) - CMOS input
132 // ENABLED (1) - Schmitt trigger input
133 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
134 // 100K_OHM_PD (0) - 100K Ohm Pull Down
135 // 47K_OHM_PU (1) - 47K Ohm Pull Up
136 // 100K_OHM_PU (2) - 100K Ohm Pull Up
137 // 22K_OHM_PU (3) - 22K Ohm Pull Up
138 // PUE [13] - Pull / Keep Select Field Reset: PULL
139 // KEEP (0) - Keeper Enabled
140 // PULL (1) - Pull Enabled
141 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
142 // DISABLED (0) - Pull/Keeper Disabled
143 // ENABLED (1) - Pull/Keeper Enabled
144 // ODE [11] - Open Drain Enable Field Reset: DISABLED
145 // Enables open drain of the pin.
146 // DISABLED (0) - Output is CMOS.
147 // ENABLED (1) - Output is Open Drain.
148 // SPEED [7:6] - Speed Field Reset: 100MHZ
149 // RESERVED0 (0) - Reserved
150 // 50MHZ (1) - Low (50 MHz)
151 // 100MHZ (2) - Medium (100 MHz)
152 // 200MHZ (3) - Maximum (200 MHz)
153 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
154 // HIZ (0) - HI-Z
155 // 240_OHM (1) - 240 Ohm
156 // 120_OHM (2) - 120 Ohm
157 // 80_OHM (3) - 80 Ohm
158 // 60_OHM (4) - 60 Ohm
159 // 48_OHM (5) - 48 Ohm
160 // 40_OHM (6) - 40 Ohm
161 // 34_OHM (7) - 34 Ohm
162 // SRE [0] - Slew Rate Field Reset: SLOW
163 // Slew rate control.
164 // SLOW (0) - Slow Slew Rate
165 // FAST (1) - Fast Slew Rate
166 HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR(
167 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS_V(ENABLED) |
168 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS_V(100K_OHM_PU) |
169 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE_V(PULL) |
170 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE_V(ENABLED) |
171 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE_V(DISABLED) |
172 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED_V(100MHZ) |
173 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE_V(40_OHM) |
174 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE_V(SLOW));
175 }
176