1 /** 2 * @file gpio_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 4 */ 5 6 /* **************************************************************************** 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included 17 * in all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Except as contained in this notice, the name of Maxim Integrated 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated 29 * Products, Inc. Branding Policy. 30 * 31 * The mere transfer of this software does not imply any licenses 32 * of trade secrets, proprietary technology, copyrights, patents, 33 * trademarks, maskwork rights, or any other form of intellectual 34 * property whatsoever. Maxim Integrated Products, Inc. retains all 35 * ownership rights. 36 * 37 * 38 *************************************************************************** */ 39 40 #ifndef _GPIO_REGS_H_ 41 #define _GPIO_REGS_H_ 42 43 /* **** Includes **** */ 44 #include <stdint.h> 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 #if defined (__ICCARM__) 51 #pragma system_include 52 #endif 53 54 #if defined (__CC_ARM) 55 #pragma anon_unions 56 #endif 57 /// @cond 58 /* 59 If types are not defined elsewhere (CMSIS) define them here 60 */ 61 #ifndef __IO 62 #define __IO volatile 63 #endif 64 #ifndef __I 65 #define __I volatile const 66 #endif 67 #ifndef __O 68 #define __O volatile 69 #endif 70 #ifndef __R 71 #define __R volatile const 72 #endif 73 /// @endcond 74 75 /* **** Definitions **** */ 76 77 /** 78 * @ingroup gpio 79 * @defgroup gpio_registers GPIO_Registers 80 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. 81 * @details Individual I/O for each GPIO 82 */ 83 84 /** 85 * @ingroup gpio_registers 86 * Structure type to access the GPIO Registers. 87 */ 88 typedef struct { 89 __IO uint32_t en; /**< <tt>\b 0x00:</tt> GPIO EN Register */ 90 __IO uint32_t en_set; /**< <tt>\b 0x04:</tt> GPIO EN_SET Register */ 91 __IO uint32_t en_clr; /**< <tt>\b 0x08:</tt> GPIO EN_CLR Register */ 92 __IO uint32_t out_en; /**< <tt>\b 0x0C:</tt> GPIO OUT_EN Register */ 93 __IO uint32_t out_en_set; /**< <tt>\b 0x10:</tt> GPIO OUT_EN_SET Register */ 94 __IO uint32_t out_en_clr; /**< <tt>\b 0x14:</tt> GPIO OUT_EN_CLR Register */ 95 __IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO OUT Register */ 96 __O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */ 97 __O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */ 98 __I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */ 99 __IO uint32_t int_mod; /**< <tt>\b 0x28:</tt> GPIO INT_MOD Register */ 100 __IO uint32_t int_pol; /**< <tt>\b 0x2C:</tt> GPIO INT_POL Register */ 101 __R uint32_t rsv_0x30; 102 __IO uint32_t int_en; /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */ 103 __IO uint32_t int_en_set; /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */ 104 __IO uint32_t int_en_clr; /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */ 105 __I uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */ 106 __R uint32_t rsv_0x44; 107 __IO uint32_t int_clr; /**< <tt>\b 0x48:</tt> GPIO INT_CLR Register */ 108 __IO uint32_t wake_en; /**< <tt>\b 0x4C:</tt> GPIO WAKE_EN Register */ 109 __IO uint32_t wake_en_set; /**< <tt>\b 0x50:</tt> GPIO WAKE_EN_SET Register */ 110 __IO uint32_t wake_en_clr; /**< <tt>\b 0x54:</tt> GPIO WAKE_EN_CLR Register */ 111 __R uint32_t rsv_0x58; 112 __IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:</tt> GPIO INT_DUAL_EDGE Register */ 113 __IO uint32_t pad_cfg1; /**< <tt>\b 0x60:</tt> GPIO PAD_CFG1 Register */ 114 __IO uint32_t pad_cfg2; /**< <tt>\b 0x64:</tt> GPIO PAD_CFG2 Register */ 115 __IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */ 116 __IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */ 117 __IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */ 118 __IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */ 119 __IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */ 120 __IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */ 121 __R uint32_t rsv_0x80_0xa7[10]; 122 __IO uint32_t is; /**< <tt>\b 0xA8:</tt> GPIO IS Register */ 123 __IO uint32_t sr; /**< <tt>\b 0xAC:</tt> GPIO SR Register */ 124 __IO uint32_t ds; /**< <tt>\b 0xB0:</tt> GPIO DS Register */ 125 __IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */ 126 __IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */ 127 __R uint32_t rsv_0xbc; 128 __IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */ 129 } mxc_gpio_regs_t; 130 131 /* Register offsets for module GPIO */ 132 /** 133 * @ingroup gpio_registers 134 * @defgroup GPIO_Register_Offsets Register Offsets 135 * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. 136 * @{ 137 */ 138 #define MXC_R_GPIO_EN ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */ 139 #define MXC_R_GPIO_EN_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */ 140 #define MXC_R_GPIO_EN_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */ 141 #define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */ 142 #define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */ 143 #define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */ 144 #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */ 145 #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */ 146 #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */ 147 #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */ 148 #define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */ 149 #define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */ 150 #define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */ 151 #define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */ 152 #define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */ 153 #define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */ 154 #define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */ 155 #define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */ 156 #define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */ 157 #define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */ 158 #define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */ 159 #define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */ 160 #define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */ 161 #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */ 162 #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */ 163 #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */ 164 #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */ 165 #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */ 166 #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */ 167 #define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */ 168 #define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */ 169 #define MXC_R_GPIO_DS ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */ 170 #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */ 171 #define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */ 172 #define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */ 173 /**@} end of group gpio_registers */ 174 175 /** 176 * @ingroup gpio_registers 177 * @defgroup GPIO_EN GPIO_EN 178 * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one 179 * GPIO pin on the associated port. 180 * @{ 181 */ 182 #define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */ 183 #define MXC_F_GPIO_EN_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */ 184 #define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */ 185 #define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */ 186 #define MXC_V_GPIO_EN_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */ 187 #define MXC_S_GPIO_EN_GPIO_EN_GPIO (MXC_V_GPIO_EN_GPIO_EN_GPIO << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */ 188 189 /**@} end of group GPIO_EN_Register */ 190 191 /** 192 * @ingroup gpio_registers 193 * @defgroup GPIO_EN_SET GPIO_EN_SET 194 * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this 195 * register sets the bits in the same positions in GPIO_EN to 1, without affecting 196 * other bits in that register. 197 * @{ 198 */ 199 #define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */ 200 #define MXC_F_GPIO_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */ 201 202 /**@} end of group GPIO_EN_SET_Register */ 203 204 /** 205 * @ingroup gpio_registers 206 * @defgroup GPIO_EN_CLR GPIO_EN_CLR 207 * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this 208 * register clears the bits in the same positions in GPIO_EN to 0, without 209 * affecting other bits in that register. 210 * @{ 211 */ 212 #define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */ 213 #define MXC_F_GPIO_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */ 214 215 /**@} end of group GPIO_EN_CLR_Register */ 216 217 /** 218 * @ingroup gpio_registers 219 * @defgroup GPIO_OUT_EN GPIO_OUT_EN 220 * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one 221 * GPIO pin in the associated port. 222 * @{ 223 */ 224 #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */ 225 #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */ 226 #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ 227 #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */ 228 #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ 229 #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */ 230 231 /**@} end of group GPIO_OUT_EN_Register */ 232 233 /** 234 * @ingroup gpio_registers 235 * @defgroup GPIO_OUT_EN_SET GPIO_OUT_EN_SET 236 * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits 237 * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, 238 * without affecting other bits in that register. 239 * @{ 240 */ 241 #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ 242 #define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */ 243 244 /**@} end of group GPIO_OUT_EN_SET_Register */ 245 246 /** 247 * @ingroup gpio_registers 248 * @defgroup GPIO_OUT_EN_CLR GPIO_OUT_EN_CLR 249 * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more 250 * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, 251 * without affecting other bits in that register. 252 * @{ 253 */ 254 #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ 255 #define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */ 256 257 /**@} end of group GPIO_OUT_EN_CLR_Register */ 258 259 /** 260 * @ingroup gpio_registers 261 * @defgroup GPIO_OUT GPIO_OUT 262 * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the 263 * associated port. This register can be written either directly, or by using the 264 * GPIO_OUT_SET and GPIO_OUT_CLR registers. 265 * @{ 266 */ 267 #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ 268 #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ 269 #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ 270 #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ 271 #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ 272 #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ 273 274 /**@} end of group GPIO_OUT_Register */ 275 276 /** 277 * @ingroup gpio_registers 278 * @defgroup GPIO_OUT_SET GPIO_OUT_SET 279 * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits 280 * in the same positions in GPIO_OUT to 1, without affecting other bits in that 281 * register. 282 * @{ 283 */ 284 #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ 285 #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ 286 #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ 287 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ 288 #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ 289 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ 290 291 /**@} end of group GPIO_OUT_SET_Register */ 292 293 /** 294 * @ingroup gpio_registers 295 * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR 296 * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the 297 * bits in the same positions in GPIO_OUT to 0, without affecting other bits in 298 * that register. 299 * @{ 300 */ 301 #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ 302 #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ 303 304 /**@} end of group GPIO_OUT_CLR_Register */ 305 306 /** 307 * @ingroup gpio_registers 308 * @defgroup GPIO_IN GPIO_IN 309 * @brief GPIO Input Register. Read-only register to read from the logic states of the 310 * GPIO pins on this port. 311 * @{ 312 */ 313 #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ 314 #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ 315 316 /**@} end of group GPIO_IN_Register */ 317 318 /** 319 * @ingroup gpio_registers 320 * @defgroup GPIO_INT_MOD GPIO_INT_MOD 321 * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt 322 * mode setting for the associated GPIO pin on this port. 323 * @{ 324 */ 325 #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */ 326 #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */ 327 #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */ 328 #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */ 329 #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */ 330 #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */ 331 332 /**@} end of group GPIO_INT_MOD_Register */ 333 334 /** 335 * @ingroup gpio_registers 336 * @defgroup GPIO_INT_POL GPIO_INT_POL 337 * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the 338 * interrupt polarity setting for one GPIO pin in the associated port. 339 * @{ 340 */ 341 #define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */ 342 #define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */ 343 #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ 344 #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */ 345 #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ 346 #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */ 347 348 /**@} end of group GPIO_INT_POL_Register */ 349 350 /** 351 * @ingroup gpio_registers 352 * @defgroup GPIO_INT_EN GPIO_INT_EN 353 * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO 354 * interrupt enable for the associated pin on the GPIO port. 355 * @{ 356 */ 357 #define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */ 358 #define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */ 359 #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ 360 #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */ 361 #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ 362 #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */ 363 364 /**@} end of group GPIO_INT_EN_Register */ 365 366 /** 367 * @ingroup gpio_registers 368 * @defgroup GPIO_INT_EN_SET GPIO_INT_EN_SET 369 * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets 370 * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits 371 * in that register. 372 * @{ 373 */ 374 #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ 375 #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */ 376 #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ 377 #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */ 378 #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ 379 #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */ 380 381 /**@} end of group GPIO_INT_EN_SET_Register */ 382 383 /** 384 * @ingroup gpio_registers 385 * @defgroup GPIO_INT_EN_CLR GPIO_INT_EN_CLR 386 * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register 387 * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting 388 * other bits in that register. 389 * @{ 390 */ 391 #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ 392 #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */ 393 #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ 394 #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */ 395 #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ 396 #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */ 397 398 /**@} end of group GPIO_INT_EN_CLR_Register */ 399 400 /** 401 * @ingroup gpio_registers 402 * @defgroup GPIO_INT_STAT GPIO_INT_STAT 403 * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending 404 * interrupt status for the associated GPIO pin in this port. 405 * @{ 406 */ 407 #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */ 408 #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */ 409 #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ 410 #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */ 411 #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ 412 #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */ 413 414 /**@} end of group GPIO_INT_STAT_Register */ 415 416 /** 417 * @ingroup gpio_registers 418 * @defgroup GPIO_INT_CLR GPIO_INT_CLR 419 * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the 420 * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits 421 * in that register. 422 * @{ 423 */ 424 #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ 425 #define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */ 426 427 /**@} end of group GPIO_INT_CLR_Register */ 428 429 /** 430 * @ingroup gpio_registers 431 * @defgroup GPIO_WAKE_EN GPIO_WAKE_EN 432 * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup 433 * enable for the associated GPIO pin in this port. 434 * @{ 435 */ 436 #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ 437 #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */ 438 #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ 439 #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */ 440 #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ 441 #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */ 442 443 /**@} end of group GPIO_WAKE_EN_Register */ 444 445 /** 446 * @ingroup gpio_registers 447 * @defgroup GPIO_WAKE_EN_SET GPIO_WAKE_EN_SET 448 * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the 449 * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in 450 * that register. 451 * @{ 452 */ 453 #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */ 454 #define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */ 455 456 /**@} end of group GPIO_WAKE_EN_SET_Register */ 457 458 /** 459 * @ingroup gpio_registers 460 * @defgroup GPIO_WAKE_EN_CLR GPIO_WAKE_EN_CLR 461 * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears 462 * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other 463 * bits in that register. 464 * @{ 465 */ 466 #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */ 467 #define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */ 468 469 /**@} end of group GPIO_WAKE_EN_CLR_Register */ 470 471 /** 472 * @ingroup gpio_registers 473 * @defgroup GPIO_INT_DUAL_EDGE GPIO_INT_DUAL_EDGE 474 * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual 475 * edge mode for the associated GPIO pin in this port. 476 * @{ 477 */ 478 #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ 479 #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */ 480 #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ 481 #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */ 482 #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ 483 #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */ 484 485 /**@} end of group GPIO_INT_DUAL_EDGE_Register */ 486 487 /** 488 * @ingroup gpio_registers 489 * @defgroup GPIO_PAD_CFG1 GPIO_PAD_CFG1 490 * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for 491 * the associated GPIO pin in this port. 492 * @{ 493 */ 494 #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */ 495 #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */ 496 #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */ 497 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */ 498 #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */ 499 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */ 500 #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */ 501 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */ 502 503 /**@} end of group GPIO_PAD_CFG1_Register */ 504 505 /** 506 * @ingroup gpio_registers 507 * @defgroup GPIO_PAD_CFG2 GPIO_PAD_CFG2 508 * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for 509 * the associated GPIO pin in this port. 510 * @{ 511 */ 512 #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */ 513 #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */ 514 #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */ 515 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */ 516 #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */ 517 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */ 518 #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */ 519 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */ 520 521 /**@} end of group GPIO_PAD_CFG2_Register */ 522 523 /** 524 * @ingroup gpio_registers 525 * @defgroup GPIO_EN1 GPIO_EN1 526 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 527 * between primary/secondary functions for the associated GPIO pin in this port. 528 * @{ 529 */ 530 #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ 531 #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ 532 #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ 533 #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ 534 #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ 535 #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ 536 537 /**@} end of group GPIO_EN1_Register */ 538 539 /** 540 * @ingroup gpio_registers 541 * @defgroup GPIO_EN1_SET GPIO_EN1_SET 542 * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register 543 * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other 544 * bits in that register. 545 * @{ 546 */ 547 #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ 548 #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ 549 550 /**@} end of group GPIO_EN1_SET_Register */ 551 552 /** 553 * @ingroup gpio_registers 554 * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR 555 * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register 556 * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other 557 * bits in that register. 558 * @{ 559 */ 560 #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ 561 #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ 562 563 /**@} end of group GPIO_EN1_CLR_Register */ 564 565 /** 566 * @ingroup gpio_registers 567 * @defgroup GPIO_EN2 GPIO_EN2 568 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects 569 * between primary/secondary functions for the associated GPIO pin in this port. 570 * @{ 571 */ 572 #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ 573 #define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ 574 #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ 575 #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ 576 #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ 577 #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ 578 579 /**@} end of group GPIO_EN2_Register */ 580 581 /** 582 * @ingroup gpio_registers 583 * @defgroup GPIO_EN2_SET GPIO_EN2_SET 584 * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register 585 * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other 586 * bits in that register. 587 * @{ 588 */ 589 #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ 590 #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ 591 592 /**@} end of group GPIO_EN2_SET_Register */ 593 594 /** 595 * @ingroup gpio_registers 596 * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR 597 * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this 598 * register clears the bits in the same positions in GPIO_EN2 to 0, without 599 * affecting other bits in that register. 600 * @{ 601 */ 602 #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ 603 #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ 604 605 /**@} end of group GPIO_EN2_CLR_Register */ 606 607 /** 608 * @ingroup gpio_registers 609 * @defgroup GPIO_DS GPIO_DS 610 * @brief GPIO Drive Strength Register. Each bit in this register selects the drive 611 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 612 * sink/source current of GPIO pins in each mode. 613 * @{ 614 */ 615 #define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */ 616 #define MXC_F_GPIO_DS_DS ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */ 617 #define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */ 618 #define MXC_S_GPIO_DS_DS_LD (MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */ 619 #define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */ 620 #define MXC_S_GPIO_DS_DS_HD (MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */ 621 622 /**@} end of group GPIO_DS_Register */ 623 624 /** 625 * @ingroup gpio_registers 626 * @defgroup GPIO_DS1 GPIO_DS1 627 * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive 628 * strength for the associated GPIO pin in this port. Refer to the Datasheet for 629 * sink/source current of GPIO pins in each mode. 630 * @{ 631 */ 632 #define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ 633 #define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ 634 635 /**@} end of group GPIO_DS1_Register */ 636 637 /** 638 * @ingroup gpio_registers 639 * @defgroup GPIO_PS GPIO_PS 640 * @brief GPIO Pull Select Mode. 641 * @{ 642 */ 643 #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ 644 #define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ 645 646 /**@} end of group GPIO_PS_Register */ 647 648 /** 649 * @ingroup gpio_registers 650 * @defgroup GPIO_VSSEL GPIO_VSSEL 651 * @brief GPIO Voltage Select. 652 * @{ 653 */ 654 #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ 655 #define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ 656 657 /**@} end of group GPIO_VSSEL_Register */ 658 659 #ifdef __cplusplus 660 } 661 #endif 662 663 #endif /* _GPIO_REGS_H_ */ 664