1 /*
2 * This is a generated file
3 *
4 * Copyright 2021 QuickLogic
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 *
18 * SPDX-License-Identifier: Apache-2.0
19 */
20
21 #ifndef __SOC_CTRL_H_
22 #define __SOC_CTRL_H_
23
24 //---------------------------------//
25 //
26 // Module: SOC_CTRL
27 //
28 //---------------------------------//
29
30 #ifndef __IO
31 #define __IO volatile
32 #endif
33
34 #ifndef __I
35 #define __I volatile
36 #endif
37
38 #ifndef __O
39 #define __O volatile
40 #endif
41
42 #include "stdint.h"
43
44 typedef struct {
45
46 // Offset = 0x0000
47 union {
48 __IO uint32_t info;
49 struct {
50 __IO uint32_t n_clusters : 16;
51 __IO uint32_t n_cores : 16;
52 } info_b;
53 };
54 __I uint32_t unused0[2];
55
56 // Offset = 0x000c
57 union {
58 __IO uint32_t build_date;
59 struct {
60 __IO uint32_t day : 8;
61 __IO uint32_t month : 8;
62 __IO uint32_t year : 16;
63 } build_date_b;
64 };
65
66 // Offset = 0x0010
67 union {
68 __IO uint32_t build_time;
69 struct {
70 __IO uint32_t seconds : 8;
71 __IO uint32_t minutes : 8;
72 __IO uint32_t hour : 8;
73 } build_time_b;
74 };
75
76 // Offset = 0x0014
77 union {
78 __IO uint32_t io_cfg0;
79 struct {
80 __IO uint32_t n_io : 8;
81 __IO uint32_t n_sysio : 8;
82 __IO uint32_t n_gpio : 8;
83 } io_cfg0_b;
84 };
85
86 // Offset = 0x0018
87 union {
88 __IO uint32_t io_cfg1;
89 struct {
90 __IO uint32_t nbit_padcfg : 8;
91 __IO uint32_t nbit_padmux : 8;
92 } io_cfg1_b;
93 };
94 __I uint32_t unused1[1];
95
96 // Offset = 0x0020
97 union {
98 __IO uint32_t per_cfg0;
99 struct {
100 __IO uint32_t n_uart : 8;
101 __IO uint32_t n_qspim : 8;
102 __IO uint32_t n_i2cm : 8;
103 __IO uint32_t n_i2sc : 8;
104 } per_cfg0_b;
105 };
106
107 // Offset = 0x0024
108 union {
109 __IO uint32_t per_cfg1;
110 struct {
111 __IO uint32_t n_sdio : 8;
112 __IO uint32_t n_cam : 8;
113 } per_cfg1_b;
114 };
115 __I uint32_t unused2[19];
116
117 // Offset = 0x0074
118 union {
119 __IO uint32_t jtagreg;
120 };
121 __I uint32_t unused3[10];
122
123 // Offset = 0x00a0
124 union {
125 __IO uint32_t corestatus;
126 struct {
127 __IO uint32_t status : 31;
128 __IO uint32_t eoc : 1;
129 } corestatus_b;
130 };
131 __I uint32_t unused4[7];
132
133 // Offset = 0x00c0
134 union {
135 __IO uint32_t cs_ro;
136 struct {
137 __IO uint32_t status : 31;
138 __IO uint32_t eoc : 1;
139 } cs_ro_b;
140 };
141
142 // Offset = 0x00c4
143 union {
144 __IO uint32_t bootsel;
145 };
146
147 // Offset = 0x00c8
148 union {
149 __IO uint32_t clksel;
150 };
151 __I uint32_t unused5[3];
152
153 // Offset = 0x00d8
154 union {
155 __IO uint32_t clk_div_clu;
156 };
157 __I uint32_t unused6[1];
158
159 // Offset = 0x00e0
160 union {
161 __IO uint32_t rto_peripheral_error;
162 struct {
163 __IO uint32_t fll_rto : 1;
164 __IO uint32_t gpio_rto : 1;
165 __IO uint32_t udma_rto : 1;
166 __IO uint32_t soc_control_rto : 1;
167 __IO uint32_t adv_timer_rto : 1;
168 __IO uint32_t event_gen_rto : 1;
169 __IO uint32_t i2cs_rto : 1;
170 __IO uint32_t timer_rto : 1;
171 __IO uint32_t fcb_rto : 1;
172 } rto_peripheral_error_b;
173 };
174
175 // Offset = 0x00e4
176 union {
177 __IO uint32_t ready_timeout_count;
178 struct {
179 __IO uint32_t count : 20;
180 } ready_timeout_count_b;
181 };
182
183 // Offset = 0x00e8
184 union {
185 __IO uint32_t reset_type1_efpga;
186 struct {
187 __IO uint32_t reset_lt : 1;
188 __IO uint32_t reset_rt : 1;
189 __IO uint32_t reset_rb : 1;
190 __IO uint32_t reset_lb : 1;
191 } reset_type1_efpga_b;
192 };
193
194 // Offset = 0x00ec
195 union {
196 __IO uint32_t enable_in_out_efpga;
197 struct {
198 __IO uint32_t enable_tcdm_p0 : 1;
199 __IO uint32_t enable_tcdm_p1 : 1;
200 __IO uint32_t enable_tcdm_p2 : 1;
201 __IO uint32_t enable_tcdm_p3 : 1;
202 __IO uint32_t enable_soc_access : 1;
203 __IO uint32_t enable_events : 1;
204 } enable_in_out_efpga_b;
205 };
206
207 // Offset = 0x00f0
208 union {
209 __IO uint32_t efpga_control_in;
210 };
211
212 // Offset = 0x00f4
213 union {
214 __IO uint32_t efpga_status_out;
215 };
216
217 // Offset = 0x00f8
218 union {
219 __IO uint32_t efpga_version;
220 };
221
222 // Offset = 0x00fc
223 union {
224 __IO uint32_t soft_reset;
225 };
226 __I uint32_t unused7[192];
227
228 // Offset = 0x0400
229 union {
230 __IO uint32_t io_ctrl[48];
231 struct {
232 __IO uint32_t mux : 2;
233 __IO uint32_t : 6;
234 __IO uint32_t cfg : 6;
235 } io_ctrl_b[48];
236 };
237 } SocCtrl_t;
238
239
240 #define REG_INFO 0x0000
241 #define REG_INFO_N_CORES_LSB 16
242 #define REG_INFO_N_CORES_MASK 0xffff
243 #define REG_INFO_N_CLUSTERS_LSB 0
244 #define REG_INFO_N_CLUSTERS_MASK 0xffff
245 #define REG_BUILD_DATE 0x000C
246 #define REG_BUILD_DATE_YEAR_LSB 16
247 #define REG_BUILD_DATE_YEAR_MASK 0xffff
248 #define REG_BUILD_DATE_MONTH_LSB 8
249 #define REG_BUILD_DATE_MONTH_MASK 0xff
250 #define REG_BUILD_DATE_DAY_LSB 0
251 #define REG_BUILD_DATE_DAY_MASK 0xff
252 #define REG_BUILD_TIME 0x0010
253 #define REG_BUILD_TIME_HOUR_LSB 16
254 #define REG_BUILD_TIME_HOUR_MASK 0xff
255 #define REG_BUILD_TIME_MINUTES_LSB 8
256 #define REG_BUILD_TIME_MINUTES_MASK 0xff
257 #define REG_BUILD_TIME_SECONDS_LSB 0
258 #define REG_BUILD_TIME_SECONDS_MASK 0xff
259 #define REG_IO_CFG0 0x0014
260 #define REG_IO_CFG0_N_GPIO_LSB 16
261 #define REG_IO_CFG0_N_GPIO_MASK 0xff
262 #define REG_IO_CFG0_N_SYSIO_LSB 8
263 #define REG_IO_CFG0_N_SYSIO_MASK 0xff
264 #define REG_IO_CFG0_N_IO_LSB 0
265 #define REG_IO_CFG0_N_IO_MASK 0xff
266 #define REG_IO_CFG1 0x0018
267 #define REG_IO_CFG1_NBIT_PADMUX_LSB 8
268 #define REG_IO_CFG1_NBIT_PADMUX_MASK 0xff
269 #define REG_IO_CFG1_NBIT_PADCFG_LSB 0
270 #define REG_IO_CFG1_NBIT_PADCFG_MASK 0xff
271 #define REG_PER_CFG0 0x0020
272 #define REG_PER_CFG0_N_I2SC_LSB 24
273 #define REG_PER_CFG0_N_I2SC_MASK 0xff
274 #define REG_PER_CFG0_N_I2CM_LSB 16
275 #define REG_PER_CFG0_N_I2CM_MASK 0xff
276 #define REG_PER_CFG0_N_QSPIM_LSB 8
277 #define REG_PER_CFG0_N_QSPIM_MASK 0xff
278 #define REG_PER_CFG0_N_UART_LSB 0
279 #define REG_PER_CFG0_N_UART_MASK 0xff
280 #define REG_PER_CFG1 0x0024
281 #define REG_PER_CFG1_N_CAM_LSB 8
282 #define REG_PER_CFG1_N_CAM_MASK 0xff
283 #define REG_PER_CFG1_N_SDIO_LSB 0
284 #define REG_PER_CFG1_N_SDIO_MASK 0xff
285 #define REG_JTAGREG 0x0074
286 #define REG_CORESTATUS 0x00A0
287 #define REG_CORESTATUS_EOC_LSB 31
288 #define REG_CORESTATUS_EOC_MASK 0x1
289 #define REG_CORESTATUS_STATUS_LSB 0
290 #define REG_CORESTATUS_STATUS_MASK 0x7fffffff
291 #define REG_CS_RO 0x00C0
292 #define REG_CS_RO_EOC_LSB 31
293 #define REG_CS_RO_EOC_MASK 0x1
294 #define REG_CS_RO_STATUS_LSB 0
295 #define REG_CS_RO_STATUS_MASK 0x7fffffff
296 #define REG_BOOTSEL 0x00C4
297 #define REG_CLKSEL 0x00C8
298 #define REG_CLK_DIV_CLU 0x00D8
299 #define REG_RTO_PERIPHERAL_ERROR 0x00E0
300 #define REG_RTO_PERIPHERAL_ERROR_FCB_RTO_LSB 8
301 #define REG_RTO_PERIPHERAL_ERROR_FCB_RTO_MASK 0x1
302 #define REG_RTO_PERIPHERAL_ERROR_TIMER_RTO_LSB 7
303 #define REG_RTO_PERIPHERAL_ERROR_TIMER_RTO_MASK 0x1
304 #define REG_RTO_PERIPHERAL_ERROR_I2CS_RTO_LSB 6
305 #define REG_RTO_PERIPHERAL_ERROR_I2CS_RTO_MASK 0x1
306 #define REG_RTO_PERIPHERAL_ERROR_EVENT_GEN_RTO_LSB 5
307 #define REG_RTO_PERIPHERAL_ERROR_EVENT_GEN_RTO_MASK 0x1
308 #define REG_RTO_PERIPHERAL_ERROR_ADV_TIMER_RTO_LSB 4
309 #define REG_RTO_PERIPHERAL_ERROR_ADV_TIMER_RTO_MASK 0x1
310 #define REG_RTO_PERIPHERAL_ERROR_SOC_CONTROL_RTO_LSB 3
311 #define REG_RTO_PERIPHERAL_ERROR_SOC_CONTROL_RTO_MASK 0x1
312 #define REG_RTO_PERIPHERAL_ERROR_UDMA_RTO_LSB 2
313 #define REG_RTO_PERIPHERAL_ERROR_UDMA_RTO_MASK 0x1
314 #define REG_RTO_PERIPHERAL_ERROR_GPIO_RTO_LSB 1
315 #define REG_RTO_PERIPHERAL_ERROR_GPIO_RTO_MASK 0x1
316 #define REG_RTO_PERIPHERAL_ERROR_FLL_RTO_LSB 0
317 #define REG_RTO_PERIPHERAL_ERROR_FLL_RTO_MASK 0x1
318 #define REG_READY_TIMEOUT_COUNT 0x00E4
319 #define REG_READY_TIMEOUT_COUNT_COUNT_LSB 0
320 #define REG_READY_TIMEOUT_COUNT_COUNT_MASK 0xfffff
321 #define REG_RESET_TYPE1_EFPGA 0x00E8
322 #define REG_RESET_TYPE1_EFPGA_RESET_LB_LSB 3
323 #define REG_RESET_TYPE1_EFPGA_RESET_LB_MASK 0x1
324 #define REG_RESET_TYPE1_EFPGA_RESET_RB_LSB 2
325 #define REG_RESET_TYPE1_EFPGA_RESET_RB_MASK 0x1
326 #define REG_RESET_TYPE1_EFPGA_RESET_RT_LSB 1
327 #define REG_RESET_TYPE1_EFPGA_RESET_RT_MASK 0x1
328 #define REG_RESET_TYPE1_EFPGA_RESET_LT_LSB 0
329 #define REG_RESET_TYPE1_EFPGA_RESET_LT_MASK 0x1
330 #define REG_ENABLE_IN_OUT_EFPGA 0x00EC
331 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_EVENTS_LSB 5
332 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_EVENTS_MASK 0x1
333 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_SOC_ACCESS_LSB 4
334 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_SOC_ACCESS_MASK 0x1
335 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P3_LSB 3
336 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P3_MASK 0x1
337 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P2_LSB 2
338 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P2_MASK 0x1
339 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P1_LSB 1
340 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P1_MASK 0x1
341 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P0_LSB 0
342 #define REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P0_MASK 0x1
343 #define REG_EFPGA_CONTROL_IN 0x00F0
344 #define REG_EFPGA_STATUS_OUT 0x00F4
345 #define REG_EFPGA_VERSION 0x00F8
346 #define REG_SOFT_RESET 0x00FC
347 #define REG_IO_CTRL 0x0400
348 #define REG_IO_CTRL_CFG_LSB 8
349 #define REG_IO_CTRL_CFG_MASK 0x3f
350 #define REG_IO_CTRL_MUX_LSB 0
351 #define REG_IO_CTRL_MUX_MASK 0x3
352
353 #ifndef __REGFIELD_OPS_
354 #define __REGFIELD_OPS_
regfield_read(uint32_t reg,uint32_t mask,uint32_t lsb)355 static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
356 return (reg >> lsb) & mask;
357 }
regfield_write(uint32_t reg,uint32_t mask,uint32_t lsb,uint32_t value)358 static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
359 reg &= ~(mask << lsb);
360 reg |= (value & mask) << lsb;
361 return reg;
362 }
363 #endif // __REGFIELD_OPS_
364
365 #endif // __SOC_CTRL_H_
366