1 /* 2 * Copyright (C) 2020 ETH Zurich and University of Bologna 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /* 18 * Copyright (c) 2019-2020 Nordic Semiconductor ASA 19 * Copyright (c) 2019 Piotr Mienkowski 20 * Copyright (c) 2017 ARM Ltd 21 * Copyright (c) 2015-2016 Intel Corporation. 22 * 23 * SPDX-License-Identifier: Apache-2.0 24 */ 25 26 /* Driver to control and configure the PULP GPIO pins */ 27 /* Author: Germain Haugou (germain.haugou@iis.ee.ethz.ch) 28 * Robert Balas (balasr@iis.ee.ethz.ch) 29 */ 30 31 #ifndef HAL_INCLUDE_HAL_GPIO_PULP_H_ 32 #define HAL_INCLUDE_HAL_GPIO_PULP_H_ 33 34 #include <stdint.h> 35 #include <assert.h> 36 #include "pulp_io.h" 37 #include "hal_pinmux1.h" 38 #include "core-v-mcu-pulp-mem-map.h" 39 40 /* TODO: static assert on expected register sequence */ 41 // 42 // REGISTERS 43 // 44 45 // GPIO pad direction configuration register. 46 #define GPIO_PADDIR_OFFSET 0x0 47 48 // GPIO enable register. 49 #define GPIO_GPIOEN_OFFSET 0x4 50 51 // GPIO pad input value register. 52 #define GPIO_PADIN_OFFSET 0x8 53 54 // GPIO pad output value register. 55 #define GPIO_PADOUT_OFFSET 0xc 56 57 // GPIO pad output set register. 58 #define GPIO_PADOUTSET_OFFSET 0x10 59 60 // GPIO pad output clear register. 61 #define GPIO_PADOUTCLR_OFFSET 0x14 62 63 // GPIO pad interrupt enable configuration register. 64 #define GPIO_INTEN_OFFSET 0x18 65 66 // GPIO pad interrupt type gpio 0 to 15 register. 67 #define GPIO_INTTYPE0_OFFSET 0x1c 68 69 // GPIO pad interrupt type gpio 16 to 31 register. 70 #define GPIO_INTTYPE1_OFFSET 0x20 71 72 // GPIO pad interrupt status register. 73 #define GPIO_INTSTATUS_OFFSET 0x24 74 75 // GPIO pad pin 0 to 7 configuration register. 76 #define GPIO_PADCFG0_OFFSET 0x28 77 78 // GPIO pad pin 8 to 15 configuration register. 79 #define GPIO_PADCFG1_OFFSET 0x2c 80 81 // GPIO pad pin 16 to 23 configuration register. 82 #define GPIO_PADCFG2_OFFSET 0x30 83 84 // GPIO pad pin 24 to 31 configuration register. 85 #define GPIO_PADCFG3_OFFSET 0x34 86 87 // GPIO pad direction configuration register. 88 #define GPIO_PADDIR_32_63_OFFSET 0x38 89 90 // GPIO enable register. 91 #define GPIO_GPIOEN_32_63_OFFSET 0x3c 92 93 // GPIO pad input value register. 94 #define GPIO_PADIN_32_63_OFFSET 0x40 95 96 // GPIO pad output value register. 97 #define GPIO_PADOUT_32_63_OFFSET 0x44 98 99 // GPIO pad output set register. 100 #define GPIO_PADOUTSET_32_63_OFFSET 0x48 101 102 // GPIO pad output clear register. 103 #define GPIO_PADOUTCLR_32_63_OFFSET 0x4c 104 105 // GPIO pad interrupt enable configuration register. 106 #define GPIO_INTEN_32_63_OFFSET 0x50 107 108 // GPIO pad interrupt type gpio 32 to 47 register. 109 #define GPIO_INTTYPE_32_47_OFFSET 0x54 110 111 // GPIO pad interrupt type gpio 48 to 63 register. 112 #define GPIO_INTTYPE_48_63_OFFSET 0x58 113 114 // GPIO pad interrupt status register. 115 #define GPIO_INTSTATUS_32_63_OFFSET 0x5c 116 117 // GPIO pad pin 32 to 39 configuration register. 118 #define GPIO_PADCFG_32_39_OFFSET 0x60 119 120 // GPIO pad pin 40 to 47 configuration register. 121 #define GPIO_PADCFG_40_47_OFFSET 0x64 122 123 // GPIO pad pin 48 to 55 configuration register. 124 #define GPIO_PADCFG_48_55_OFFSET 0x68 125 126 // GPIO pad pin 56 to 63 configuration register. 127 #define GPIO_PADCFG_56_63_OFFSET 0x6c 128 129 // 130 // REGISTERS FIELDS 131 // 132 133 // GPIO[31:0] direction configuration bitfield: - bit[i]=1'b0: Input mode for GPIO[i] - bit[i]=1'b1: Output mode for GPIO[i] (access: R/W) 134 #define GPIO_PADDIR_DIR_BIT 0 135 #define GPIO_PADDIR_DIR_WIDTH 32 136 #define GPIO_PADDIR_DIR_MASK 0xffffffff 137 138 // GPIO[31:0] clock enable configuration bitfield: - bit[i]=1'b0: disable clock for GPIO[i] - bit[i]=1'b1: enable clock for GPIO[i] GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled. Clock must be enabled for a GPIO if it's direction is configured in input mode. (access: R/W) 139 #define GPIO_GPIOEN_GPIOEN_BIT 0 140 #define GPIO_GPIOEN_GPIOEN_WIDTH 32 141 #define GPIO_GPIOEN_GPIOEN_MASK 0xffffffff 142 143 // GPIO[31:0] input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. (access: R) 144 #define GPIO_PADIN_DATA_IN_BIT 0 145 #define GPIO_PADIN_DATA_IN_WIDTH 32 146 #define GPIO_PADIN_DATA_IN_MASK 0xffffffff 147 148 // GPIO[31:0] output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. (access: R/W) 149 #define GPIO_PADOUT_DATA_OUT_BIT 0 150 #define GPIO_PADOUT_DATA_OUT_WIDTH 32 151 #define GPIO_PADOUT_DATA_OUT_MASK 0xffffffff 152 153 // GPIO[31:0] set bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Sets GPIO[i] to 1 (access: W) 154 #define GPIO_PADOUTSET_DATA_SET_BIT 0 155 #define GPIO_PADOUTSET_DATA_SET_WIDTH 32 156 #define GPIO_PADOUTSET_DATA_SET_MASK 0xffffffff 157 158 // GPIO[31:0] clear bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Clears GPIO[i] (access: W) 159 #define GPIO_PADOUTCLR_DATA_CLEAR_BIT 0 160 #define GPIO_PADOUTCLR_DATA_CLEAR_WIDTH 32 161 #define GPIO_PADOUTCLR_DATA_CLEAR_MASK 0xffffffff 162 163 // GPIO[31:0] interrupt enable configuration bitfield: - bit[i]=1'b0: disable interrupt for GPIO[i] - bit[i]=1'b1: enable interrupt for GPIO[i] (access: R/W) 164 #define GPIO_INTEN_INTEN_BIT 0 165 #define GPIO_INTEN_INTEN_WIDTH 32 166 #define GPIO_INTEN_INTEN_MASK 0xffffffff 167 168 // GPIO[15:0] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W) 169 #define GPIO_INTTYPE0_INTTYPE0_BIT 0 170 #define GPIO_INTTYPE0_INTTYPE0_WIDTH 32 171 #define GPIO_INTTYPE0_INTTYPE0_MASK 0xffffffff 172 173 // GPIO[31:16] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W) 174 #define GPIO_INTTYPE1_INTTYPE1_BIT 0 175 #define GPIO_INTTYPE1_INTTYPE1_WIDTH 32 176 #define GPIO_INTTYPE1_INTTYPE1_MASK 0xffffffff 177 178 // GPIO[31:0] Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. (access: R) 179 #define GPIO_INTSTATUS_INTSTATUS_BIT 0 180 #define GPIO_INTSTATUS_INTSTATUS_WIDTH 32 181 #define GPIO_INTSTATUS_INTSTATUS_MASK 0xffffffff 182 183 // GPIO[0] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) 184 #define GPIO_PADCFG0_GPIO0_CFG_BIT 0 185 #define GPIO_PADCFG0_GPIO0_CFG_WIDTH 4 186 #define GPIO_PADCFG0_GPIO0_CFG_MASK 0xf 187 188 // GPIO[0] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) 189 #define GPIO_PADCFG0_GPIO1_CFG_BIT 4 190 #define GPIO_PADCFG0_GPIO1_CFG_WIDTH 4 191 #define GPIO_PADCFG0_GPIO1_CFG_MASK 0xf0 192 193 // GPIO[1] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) 194 #define GPIO_PADCFG0_GPIO2_CFG_BIT 8 195 #define GPIO_PADCFG0_GPIO2_CFG_WIDTH 4 196 #define GPIO_PADCFG0_GPIO2_CFG_MASK 0xf00 197 198 // GPIO[1] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) 199 #define GPIO_PADCFG0_GPIO3_CFG_BIT 12 200 #define GPIO_PADCFG0_GPIO3_CFG_WIDTH 4 201 #define GPIO_PADCFG0_GPIO3_CFG_MASK 0xf000 202 203 // GPIO[2] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) 204 #define GPIO_PADCFG0_GPIO4_CFG_BIT 16 205 #define GPIO_PADCFG0_GPIO4_CFG_WIDTH 4 206 #define GPIO_PADCFG0_GPIO4_CFG_MASK 0xf0000 207 208 // GPIO[2] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) 209 #define GPIO_PADCFG0_GPIO5_CFG_BIT 20 210 #define GPIO_PADCFG0_GPIO5_CFG_WIDTH 4 211 #define GPIO_PADCFG0_GPIO5_CFG_MASK 0xf00000 212 213 // GPIO[3] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) 214 #define GPIO_PADCFG0_GPIO6_CFG_BIT 24 215 #define GPIO_PADCFG0_GPIO6_CFG_WIDTH 4 216 #define GPIO_PADCFG0_GPIO6_CFG_MASK 0xf000000 217 218 // GPIO[3] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) 219 #define GPIO_PADCFG0_GPIO7_CFG_BIT 28 220 #define GPIO_PADCFG0_GPIO7_CFG_WIDTH 4 221 #define GPIO_PADCFG0_GPIO7_CFG_MASK 0xf0000000 222 223 // GPIO[4] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W) 224 #define GPIO_PADCFG1_GPIO4_PE_BIT 0 225 #define GPIO_PADCFG1_GPIO4_PE_WIDTH 1 226 #define GPIO_PADCFG1_GPIO4_PE_MASK 0x1 227 228 // GPIO[4] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W) 229 #define GPIO_PADCFG1_GPIO4_DS_BIT 1 230 #define GPIO_PADCFG1_GPIO4_DS_WIDTH 1 231 #define GPIO_PADCFG1_GPIO4_DS_MASK 0x2 232 233 // GPIO[63:32] direction configuration bitfield: - bit[i]=1'b0: Input mode for GPIO[i] - bit[i]=1'b1: Output mode for GPIO[i] (access: R/W) 234 #define GPIO_PADDIR_32_63_DIR_BIT 0 235 #define GPIO_PADDIR_32_63_DIR_WIDTH 32 236 #define GPIO_PADDIR_32_63_DIR_MASK 0xffffffff 237 238 // GPIO[63:32] clock enable configuration bitfield: - bit[i]=1'b0: disable clock for GPIO[i] - bit[i]=1'b1: enable clock for GPIO[i] GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled. Clock must be enabled for a GPIO if it's direction is configured in input mode. (access: R/W) 239 #define GPIO_GPIOEN_32_63_GPIOEN_BIT 0 240 #define GPIO_GPIOEN_32_63_GPIOEN_WIDTH 32 241 #define GPIO_GPIOEN_32_63_GPIOEN_MASK 0xffffffff 242 243 // GPIO[63:32] input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. (access: R) 244 #define GPIO_PADIN_32_63_DATA_IN_BIT 0 245 #define GPIO_PADIN_32_63_DATA_IN_WIDTH 32 246 #define GPIO_PADIN_32_63_DATA_IN_MASK 0xffffffff 247 248 // GPIO[63:32] output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. (access: R/W) 249 #define GPIO_PADOUT_32_63_DATA_OUT_BIT 0 250 #define GPIO_PADOUT_32_63_DATA_OUT_WIDTH 32 251 #define GPIO_PADOUT_32_63_DATA_OUT_MASK 0xffffffff 252 253 // GPIO[63:32] set bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Sets GPIO[i] to 1 (access: W) 254 #define GPIO_PADOUTSET_32_63_DATA_SET_BIT 0 255 #define GPIO_PADOUTSET_32_63_DATA_SET_WIDTH 32 256 #define GPIO_PADOUTSET_32_63_DATA_SET_MASK 0xffffffff 257 258 // GPIO[63:32] clear bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Clears GPIO[i] (access: W) 259 #define GPIO_PADOUTCLR_32_63_DATA_CLEAR_BIT 0 260 #define GPIO_PADOUTCLR_32_63_DATA_CLEAR_WIDTH 32 261 #define GPIO_PADOUTCLR_32_63_DATA_CLEAR_MASK 0xffffffff 262 263 // GPIO[63:32] interrupt enable configuration bitfield: - bit[i]=1'b0: disable interrupt for GPIO[i] - bit[i]=1'b1: enable interrupt for GPIO[i] (access: R/W) 264 #define GPIO_INTEN_32_63_INTEN_BIT 0 265 #define GPIO_INTEN_32_63_INTEN_WIDTH 32 266 #define GPIO_INTEN_32_63_INTEN_MASK 0xffffffff 267 268 // GPIO[47:32] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W) 269 #define GPIO_INTTYPE_32_47_INTTYPE0_BIT 0 270 #define GPIO_INTTYPE_32_47_INTTYPE0_WIDTH 32 271 #define GPIO_INTTYPE_32_47_INTTYPE0_MASK 0xffffffff 272 273 // GPIO[63:48] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W) 274 #define GPIO_INTTYPE_48_63_INTTYPE1_BIT 0 275 #define GPIO_INTTYPE_48_63_INTTYPE1_WIDTH 32 276 #define GPIO_INTTYPE_48_63_INTTYPE1_MASK 0xffffffff 277 278 // GPIO[63:32] Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. (access: R) 279 #define GPIO_INTSTATUS_32_63_INTSTATUS_BIT 0 280 #define GPIO_INTSTATUS_32_63_INTSTATUS_WIDTH 32 281 #define GPIO_INTSTATUS_32_63_INTSTATUS_MASK 0xffffffff 282 283 /* required for gpio_pin_conf_pad() */ 284 static_assert((GPIO_PADCFG0_OFFSET + 0x4 == GPIO_PADCFG1_OFFSET) && 285 (GPIO_PADCFG1_OFFSET + 0x4 == GPIO_PADCFG2_OFFSET) && 286 (GPIO_PADCFG2_OFFSET + 0x4 == GPIO_PADCFG3_OFFSET), 287 "GPIO_PADCFG*_OFFSET has unexpected addresses (spacing)"); 288 289 /* this API is from gpio.h of zephyr */ 290 291 /* this is custom */ 292 /** Enables internal pull */ 293 #define GPIO_PULL_ENABLE (1U << 1) 294 295 /** Enables high drive strength */ 296 #define GPIO_DRIVE_STRENGTH_HIGH (1U << 1) 297 298 /* this is zephyr */ 299 /** Enables pin as input. */ 300 #define GPIO_INPUT (1U << 8) 301 302 /** Enables pin as output, no change to the output state. */ 303 #define GPIO_OUTPUT (1U << 9) 304 305 /** Disables pin for both input and output. */ 306 #define GPIO_DISCONNECTED 0 307 308 /** @cond INTERNAL_HIDDEN */ 309 310 /* Initializes output to a low state. */ 311 #define GPIO_OUTPUT_INIT_LOW (1U << 10) 312 313 /* Initializes output to a high state. */ 314 #define GPIO_OUTPUT_INIT_HIGH (1U << 11) 315 316 /* Initializes output based on logic level */ 317 #define GPIO_OUTPUT_INIT_LOGICAL (1U << 12) 318 319 /** @endcond */ 320 321 /** Configures GPIO pin as output and initializes it to a low state. */ 322 #define GPIO_OUTPUT_LOW (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW) 323 /** Configures GPIO pin as output and initializes it to a high state. */ 324 #define GPIO_OUTPUT_HIGH (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH) 325 /** Configures GPIO pin as output and initializes it to a logic 0. */ 326 #define GPIO_OUTPUT_INACTIVE \ 327 (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_LOGICAL) 328 /** Configures GPIO pin as output and initializes it to a logic 1. */ 329 #define GPIO_OUTPUT_ACTIVE \ 330 (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOGICAL) 331 332 int gpio_pin_conf_pad(int pin, uint32_t flags); 333 334 335 /* for now we only handle the gpio from 0-31 and ignore 32-63 */ 336 int gpio_pin_configure(int pin, uint32_t flags); 337 int gpio_port_get_raw(uint32_t *value); 338 int gpio_port_set_masked_raw(uint32_t mask, uint32_t value); 339 int gpio_port_set_bits_raw(uint32_t mask); 340 int gpio_port_clear_bits_raw(uint32_t mask); 341 int gpio_port_toggle_bits(uint32_t mask); 342 int gpio_pin_get_raw(int pin); 343 int gpio_pin_set_raw(int pin, int value); 344 int gpio_pin_toggle(int pin); 345 346 347 #endif /* HAL_INCLUDE_HAL_GPIO_PULP_H_ */ 348