1 /*
2  * Copyright (C) 2019 ETH Zurich and University of Bologna
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *     http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  *
16  * SPDX-License-Identifier: Apache-2.0
17  */
18 
19 /* Author: Robert Balas (balasr@iis.ee.ethz.ch)
20  *         Germain Haugou (germain.haugou@iis.ee.ethz.ch)
21  */
22 
23 
24 #ifndef HAL_INCLUDE_HAL_SOC_EU_H_
25 #define HAL_INCLUDE_HAL_SOC_EU_H_
26 
27 
28 /*
29  * SOC EVENTS
30  */
31 
32 /* Let's remove for the time being the SOC_EU* macros from the pulp-sdk and use
33  * the ones form pulp-runtime
34  */
35 
36 /*
37 #define SOC_EU_EVENT_PERIPH_EVT_NB 160
38 
39 #define SOC_EU_EVENT_SW_NB (8)
40 
41 #define SOC_EU_EVENT_NB_TOTAL 256
42 
43 #define SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT_LOG2 2
44 #define SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT                                       \
45 	(1 << SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT_LOG2)
46 #define SOC_EU_EVENT_UDMA_FIRST_EVT 0
47 #define SOC_EU_EVENT_UDMA_NB_EVT                                               \
48 	(SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT * EU_NB_PERIPH)
49 #define SOC_EU_EVENT_UDMA_NB_TGEN_EVT 6
50 
51 #define SOC_EU_EVENT_PERIPH_FIRST_EVT(x) ((x)*SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT)
52 
53 #define SOC_EU_EVENT_UART0_RX	   0
54 #define SOC_EU_EVENT_UART0_TX	   1
55 #define SOC_EU_EVENT_UART0_EOT	   2
56 #define SOC_EU_EVENT_UART0_RX_DATA 3
57 
58 #define SOC_EU_EVENT_SPIM0_RX  4
59 #define SOC_EU_EVENT_SPIM0_TX  5
60 #define SOC_EU_EVENT_SPIM0_CMD 6
61 #define SOC_EU_EVENT_SPIM0_EOT 7
62 
63 #define SOC_EU_EVENT_I2C0_RX 8
64 #define SOC_EU_EVENT_I2C0_TX 9
65 
66 #define SOC_EU_EVENT_I2C1_RX 12
67 #define SOC_EU_EVENT_I2C1_TX 13
68 
69 #define SOC_EU_EVENT_SDIO0_RX 16
70 #define SOC_EU_EVENT_SDIO0_TX 17
71 
72 #define SOC_EU_EVENT_I2S0_RX 20
73 #define SOC_EU_EVENT_I2S0_TX 21
74 
75 #define SOC_EU_EVENT_CPI0_RX 24
76 
77 #define SOC_EU_EVENT_FILTER0_RX 28
78 #define SOC_EU_EVENT_FILTER0_TX 29
79 
80 #define SOC_EU_EVENT_CLUSTER_ON_OFF   31
81 #define SOC_EU_EVENT_MSP	      37
82 #define SOC_EU_EVENT_ICU_MODE_CHANGED 37
83 #define SOC_EU_EVENT_ICU_OK	      37
84 #define SOC_EU_EVENT_ICU_DELAYED      37
85 #define SOC_EU_EVENT_CLUSTER_CG_OK    35
86 #define SOC_EU_EVENT_PICL_OK	      36
87 #define SOC_EU_EVENT_SCU_OK	      37
88 #define SOC_EU_EVENT_PMU_FIRST_EVENT  SOC_EU_EVENT_CLUSTER_ON_OFF
89 #define SOC_EU_EVENT_PMU_NB_EVENTS    7
90 
91 #define SOC_EU_EVENT_GPIO 42
92 
93 #define SOC_EU_EVENT_NB_I2S_CHANNELS  4
94 #define SOC_EU_EVENT_NB_UDMA_CHANNELS 19
95 
96 #define SOC_EU_EVENT_FCHWPE0 140
97 #define SOC_EU_EVENT_FCHWPE1 141
98 
99 #define SOC_EU_EVENT_SW_EVENT0 48
100 #define SOC_EU_EVENT_SW_EVENT1 49
101 #define SOC_EU_EVENT_SW_EVENT2 50
102 #define SOC_EU_EVENT_SW_EVENT3 51
103 #define SOC_EU_EVENT_SW_EVENT4 52
104 #define SOC_EU_EVENT_SW_EVENT5 53
105 #define SOC_EU_EVENT_SW_EVENT6 54
106 #define SOC_EU_EVENT_SW_EVENT7 55
107 
108 #define SOC_EU_EVENT_NB 8
109 
110 #define SOC_EU_EVENT_REF_CLK_RISE 56
111 */
112 
113 #define SOC_EU_EVENT	   0x00
114 #define SOC_FC_FIRST_MASK  0x04
115 #define SOC_CL_FIRST_MASK  0x24
116 #define SOC_PR_FIRST_MASK  0x44
117 #define SOC_ERR_FIRST_MASK 0x64
118 #define SOC_TIMER_SEL_HI   0x84
119 #define SOC_TIMER_SEL_LO   0x88
120 
121 #define SOC_EU_EVENT_0 0x1
122 #define SOC_EU_EVENT_1 0x2
123 #define SOC_EU_EVENT_2 0x4
124 #define SOC_EU_EVENT_3 0x8
125 #define SOC_EU_EVENT_4 0x10
126 #define SOC_EU_EVENT_5 0x20
127 #define SOC_EU_EVENT_6 0x40
128 #define SOC_EU_EVENT_7 0x80
129 
130 #define SOC_TIMER_SEL_ENABLE_SHIFT 31
131 #define SOC_TIMER_SEL_EVT_SHIFT	   0
132 #define SOC_TIMER_SEL_EVT_WIDTH	   8
133 #define SOC_TIMER_SEL_EVT_MASK	   ((~0U) >> (32 - SOC_TIMER_SEL_EVT_WIDTH))
134 // #define SOC_TIMER_SEL_EVT_MASK    0xff
135 
136 #define SOC_TIMER_SEL_ENABLE_DISABLED 0
137 #define SOC_TIMER_SEL_ENABLE_ENABLED  1
138 
139 #define SOC_TIMER_SEL_ENABLE_DIS   (0 << SOC_TIMER_SEL_ENABLE_SHIFT)
140 #define SOC_TIMER_SEL_ENABLE_ENA   (1 << SOC_TIMER_SEL_ENABLE_SHIFT)
141 #define SOC_TIMER_SEL_EVT_VAL(val) ((val) << SOC_TIMER_SEL_EVT_SHIFT)
142 
143 // related to XX_FIRST_MASK registers
144 #define SOC_NB_EVENT_REGS    8
145 #define SOC_NB_EVENT_TARGETS 3
146 
147 #define SOC_FC_MASK(x) (SOC_FC_FIRST_MASK + (x)*4)
148 #define SOC_CL_MASK(x) (SOC_CL_FIRST_MASK + (x)*4)
149 #define SOC_PR_MASK(x) (SOC_PR_FIRST_MASK + (x)*4)
150 
151 /* TODO: doc */
152 void soc_eu_mask_set(uint32_t offset, uint32_t mask);
153 uint32_t soc_eu_mask_get(uint32_t offset);
154 void pulp_soc_eu_event_init();
155 
156 
157 #endif /* HAL_INCLUDE_HAL_SOC_EU_H_ */
158