1 /*
2 * This is a generated file
3 *
4 * Copyright 2021 QuickLogic
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 *
18 * SPDX-License-Identifier: Apache-2.0
19 */
20
21 #ifndef __UDMA_CTRL_H_
22 #define __UDMA_CTRL_H_
23
24 //---------------------------------//
25 //
26 // Module: UDMA_CTRL
27 //
28 //---------------------------------//
29
30 #ifndef __IO
31 #define __IO volatile
32 #endif
33
34 #ifndef __I
35 #define __I volatile
36 #endif
37
38 #ifndef __O
39 #define __O volatile
40 #endif
41
42 #include "stdint.h"
43
44 typedef struct {
45
46 // Offset = 0x0000
47 union {
48 __IO uint32_t reg_cg;
49 struct {
50 __IO uint32_t periph_clk_enable : 32;
51 } reg_cg_b;
52 };
53
54 // Offset = 0x0004
55 union {
56 __IO uint32_t reg_cfg_evt;
57 struct {
58 __IO uint32_t cmp_event0 : 8;
59 __IO uint32_t cmp_event1 : 8;
60 __IO uint32_t cmp_event2 : 8;
61 __IO uint32_t cmp_event3 : 8;
62 } reg_cfg_evt_b;
63 };
64
65 // Offset = 0x0008
66 union {
67 __IO uint32_t reg_rst;
68 struct {
69 __IO uint32_t periph_reset : 32;
70 } reg_rst_b;
71 };
72 } UdmaCtrl_t;
73
74
75 #define REG_REG_CG 0x000
76 #define REG_REG_CG_PERIPH_CLK_ENABLE_LSB 0
77 #define REG_REG_CG_PERIPH_CLK_ENABLE_MASK 0xffffffff
78 #define REG_REG_CFG_EVT 0x004
79 #define REG_REG_CFG_EVT_CMP_EVENT3_LSB 24
80 #define REG_REG_CFG_EVT_CMP_EVENT3_MASK 0xff
81 #define REG_REG_CFG_EVT_CMP_EVENT2_LSB 16
82 #define REG_REG_CFG_EVT_CMP_EVENT2_MASK 0xff
83 #define REG_REG_CFG_EVT_CMP_EVENT1_LSB 8
84 #define REG_REG_CFG_EVT_CMP_EVENT1_MASK 0xff
85 #define REG_REG_CFG_EVT_CMP_EVENT0_LSB 0
86 #define REG_REG_CFG_EVT_CMP_EVENT0_MASK 0xff
87 #define REG_REG_RST 0x008
88 #define REG_REG_RST_PERIPH_RESET_LSB 0
89 #define REG_REG_RST_PERIPH_RESET_MASK 0xffffffff
90
91 #ifndef __REGFIELD_OPS_
92 #define __REGFIELD_OPS_
regfield_read(uint32_t reg,uint32_t mask,uint32_t lsb)93 static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
94 return (reg >> lsb) & mask;
95 }
regfield_write(uint32_t reg,uint32_t mask,uint32_t lsb,uint32_t value)96 static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
97 reg &= ~(mask << lsb);
98 reg |= (value & mask) << lsb;
99 return reg;
100 }
101 #endif // __REGFIELD_OPS_
102
103 #endif // __UDMA_CTRL_H_
104