1 /*
2 * This is a generated file
3 *
4 * Copyright 2021 QuickLogic
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 *
18 * SPDX-License-Identifier: Apache-2.0
19 */
20
21 #ifndef __UDMA_UART_H_
22 #define __UDMA_UART_H_
23
24 //---------------------------------//
25 //
26 // Module: UDMA_UART
27 //
28 //---------------------------------//
29
30 #ifndef __IO
31 #define __IO volatile
32 #endif
33
34 #ifndef __I
35 #define __I volatile
36 #endif
37
38 #ifndef __O
39 #define __O volatile
40 #endif
41
42 #include "stdint.h"
43
44 typedef struct {
45
46 // Offset = 0x0000
47 union {
48 __IO uint32_t rx_saddr;
49 struct {
50 __IO uint32_t saddr : 12;
51 } rx_saddr_b;
52 };
53
54 // Offset = 0x0004
55 union {
56 __IO uint32_t rx_size;
57 struct {
58 __IO uint32_t size : 16;
59 } rx_size_b;
60 };
61
62 // Offset = 0x0008
63 union {
64 __IO uint32_t rx_cfg;
65 struct {
66 __IO uint32_t continuous : 1;
67 __IO uint32_t : 3;
68 __IO uint32_t en : 1;
69 __IO uint32_t pending : 1;
70 __IO uint32_t clr : 1;
71 } rx_cfg_b;
72 };
73 __I uint32_t unused0[1];
74
75 // Offset = 0x0010
76 union {
77 __IO uint32_t tx_saddr;
78 struct {
79 __IO uint32_t saddr : 12;
80 } tx_saddr_b;
81 };
82
83 // Offset = 0x0014
84 union {
85 __IO uint32_t tx_size;
86 struct {
87 __IO uint32_t size : 16;
88 } tx_size_b;
89 };
90
91 // Offset = 0x0018
92 union {
93 __IO uint32_t tx_cfg;
94 struct {
95 __IO uint32_t continuous : 1;
96 __IO uint32_t : 3;
97 __IO uint32_t en : 1;
98 __IO uint32_t pending : 1;
99 __IO uint32_t clr : 1;
100 } tx_cfg_b;
101 };
102 __I uint32_t unused1[1];
103
104 // Offset = 0x0020
105 union {
106 __IO uint32_t status;
107 struct {
108 __IO uint32_t tx_busy : 1;
109 __IO uint32_t rx_busy : 1;
110 } status_b;
111 };
112
113 // Offset = 0x0024
114 union {
115 __IO uint32_t uart_setup;
116 struct {
117 __IO uint32_t parity_en : 1;
118 __IO uint32_t bits : 2;
119 __IO uint32_t stop_bits : 1;
120 __IO uint32_t rx_polling_en : 1;
121 __IO uint32_t rx_clean_fifo : 1;
122 __IO uint32_t : 2;
123 __IO uint32_t en_tx : 1;
124 __IO uint32_t en_rx : 1;
125 __IO uint32_t : 6;
126 __IO uint32_t div : 16;
127 } uart_setup_b;
128 };
129
130 // Offset = 0x0028
131 union {
132 __IO uint32_t error;
133 struct {
134 __IO uint32_t overflow_err : 1;
135 __IO uint32_t parity_err : 1;
136 } error_b;
137 };
138
139 // Offset = 0x002c
140 union {
141 __IO uint32_t irq_en;
142 struct {
143 __IO uint32_t rx_irq_en : 1;
144 __IO uint32_t err_irq_en : 1;
145 } irq_en_b;
146 };
147
148 // Offset = 0x0030
149 union {
150 __IO uint32_t valid;
151 struct {
152 __IO uint32_t rx_data_valid : 1;
153 } valid_b;
154 };
155
156 // Offset = 0x0034
157 union {
158 __IO uint32_t data;
159 struct {
160 __IO uint32_t rx_data : 8;
161 } data_b;
162 };
163 } UdmaUart_t;
164
165
166 #define REG_RX_SADDR 0x00
167 #define REG_RX_SADDR_SADDR_LSB 0
168 #define REG_RX_SADDR_SADDR_MASK 0xfff
169 #define REG_RX_SIZE 0x04
170 #define REG_RX_SIZE_SIZE_LSB 0
171 #define REG_RX_SIZE_SIZE_MASK 0xffff
172 #define REG_RX_CFG 0x08
173 #define REG_RX_CFG_CLR_LSB 6
174 #define REG_RX_CFG_CLR_MASK 0x1
175 #define REG_RX_CFG_PENDING_LSB 5
176 #define REG_RX_CFG_PENDING_MASK 0x1
177 #define REG_RX_CFG_EN_LSB 4
178 #define REG_RX_CFG_EN_MASK 0x1
179 #define REG_RX_CFG_CONTINUOUS_LSB 0
180 #define REG_RX_CFG_CONTINUOUS_MASK 0x1
181 #define REG_TX_SADDR 0x10
182 #define REG_TX_SADDR_SADDR_LSB 0
183 #define REG_TX_SADDR_SADDR_MASK 0xfff
184 #define REG_TX_SIZE 0x14
185 #define REG_TX_SIZE_SIZE_LSB 0
186 #define REG_TX_SIZE_SIZE_MASK 0xffff
187 #define REG_TX_CFG 0x18
188 #define REG_TX_CFG_CLR_LSB 6
189 #define REG_TX_CFG_CLR_MASK 0x1
190 #define REG_TX_CFG_PENDING_LSB 5
191 #define REG_TX_CFG_PENDING_MASK 0x1
192 #define REG_TX_CFG_EN_LSB 4
193 #define REG_TX_CFG_EN_MASK 0x1
194 #define REG_TX_CFG_CONTINUOUS_LSB 0
195 #define REG_TX_CFG_CONTINUOUS_MASK 0x1
196 #define REG_STATUS 0x20
197 #define REG_STATUS_RX_BUSY_LSB 1
198 #define REG_STATUS_RX_BUSY_MASK 0x1
199 #define REG_STATUS_TX_BUSY_LSB 0
200 #define REG_STATUS_TX_BUSY_MASK 0x1
201 #define REG_UART_SETUP 0x24
202 #define REG_UART_SETUP_DIV_LSB 16
203 #define REG_UART_SETUP_DIV_MASK 0xffff
204 #define REG_UART_SETUP_EN_RX_LSB 9
205 #define REG_UART_SETUP_EN_RX_MASK 0x1
206 #define REG_UART_SETUP_EN_TX_LSB 8
207 #define REG_UART_SETUP_EN_TX_MASK 0x1
208 #define REG_UART_SETUP_RX_CLEAN_FIFO_LSB 5
209 #define REG_UART_SETUP_RX_CLEAN_FIFO_MASK 0x1
210 #define REG_UART_SETUP_RX_POLLING_EN_LSB 4
211 #define REG_UART_SETUP_RX_POLLING_EN_MASK 0x1
212 #define REG_UART_SETUP_STOP_BITS_LSB 3
213 #define REG_UART_SETUP_STOP_BITS_MASK 0x1
214 #define REG_UART_SETUP_BITS_LSB 1
215 #define REG_UART_SETUP_BITS_MASK 0x3
216 #define REG_UART_SETUP_PARITY_EN_LSB 0
217 #define REG_UART_SETUP_PARITY_EN_MASK 0x1
218 #define REG_ERROR 0x28
219 #define REG_ERROR_PARITY_ERR_LSB 1
220 #define REG_ERROR_PARITY_ERR_MASK 0x1
221 #define REG_ERROR_OVERFLOW_ERR_LSB 0
222 #define REG_ERROR_OVERFLOW_ERR_MASK 0x1
223 #define REG_IRQ_EN 0x2C
224 #define REG_IRQ_EN_ERR_IRQ_EN_LSB 1
225 #define REG_IRQ_EN_ERR_IRQ_EN_MASK 0x1
226 #define REG_IRQ_EN_RX_IRQ_EN_LSB 0
227 #define REG_IRQ_EN_RX_IRQ_EN_MASK 0x1
228 #define REG_VALID 0x30
229 #define REG_VALID_RX_DATA_VALID_LSB 0
230 #define REG_VALID_RX_DATA_VALID_MASK 0x1
231 #define REG_DATA 0x34
232 #define REG_DATA_RX_DATA_LSB 0
233 #define REG_DATA_RX_DATA_MASK 0xff
234
235 #ifndef __REGFIELD_OPS_
236 #define __REGFIELD_OPS_
regfield_read(uint32_t reg,uint32_t mask,uint32_t lsb)237 static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
238 return (reg >> lsb) & mask;
239 }
regfield_write(uint32_t reg,uint32_t mask,uint32_t lsb,uint32_t value)240 static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
241 reg &= ~(mask << lsb);
242 reg |= (value & mask) << lsb;
243 return reg;
244 }
245 #endif // __REGFIELD_OPS_
246
247 #endif // __UDMA_UART_H_
248