1 /** 2 ****************************************************************************** 3 * @file adc_reg.h 4 * @version V1.0 5 * @date 2022-08-05 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_ADC_H__ 37 #define __HARDWARE_ADC_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 /* gpip base */ 46 #define GPIP_GPADC_CONFIG_OFFSET (0x0) /* gpadc_config */ 47 #define GPIP_GPADC_DMA_RDATA_OFFSET (0x4) /* gpadc_dma_rdata */ 48 #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 49 #define GPIP_GPADC_PIR_TRAIN_OFFSET (0x20) /* gpadc_pir_train */ 50 #endif 51 /* aon base */ 52 #define AON_GPADC_REG_CMD_OFFSET (0x90C) /* gpadc_reg_cmd */ 53 #define AON_GPADC_REG_CONFIG1_OFFSET (0x910) /* gpadc_reg_config1 */ 54 #define AON_GPADC_REG_CONFIG2_OFFSET (0x914) /* gpadc_reg_config2 */ 55 #define AON_GPADC_REG_SCN_POS1_OFFSET (0x918) /* adc converation sequence 1 */ 56 #define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C) /* adc converation sequence 2 */ 57 #define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920) /* adc converation sequence 3 */ 58 #define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924) /* adc converation sequence 4 */ 59 #define AON_GPADC_REG_STATUS_OFFSET (0x928) /* gpadc_reg_status */ 60 #define AON_GPADC_REG_ISR_OFFSET (0x92C) /* gpadc_reg_isr */ 61 #define AON_GPADC_REG_RESULT_OFFSET (0x930) /* gpadc_reg_result */ 62 #define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934) /* gpadc_reg_raw_result */ 63 #define AON_GPADC_REG_DEFINE_OFFSET (0x938) /* gpadc_reg_define */ 64 65 /* Register Bitfield definitions *****************************************************/ 66 67 /* 0x0 : gpadc_config */ 68 #define GPIP_GPADC_DMA_EN (1 << 0U) 69 #define GPIP_GPADC_FIFO_CLR (1 << 1U) 70 #define GPIP_GPADC_FIFO_NE (1 << 2U) 71 #define GPIP_GPADC_FIFO_FULL (1 << 3U) 72 #define GPIP_GPADC_RDY (1 << 4U) 73 #define GPIP_GPADC_FIFO_OVERRUN (1 << 5U) 74 #define GPIP_GPADC_FIFO_UNDERRUN (1 << 6U) 75 #if defined(BL702) || defined(BL702L) 76 #define GPIP_GPADC_FIFO_RDY (1 << 7U) 77 #endif 78 #define GPIP_GPADC_RDY_CLR (1 << 8U) 79 #define GPIP_GPADC_FIFO_OVERRUN_CLR (1 << 9U) 80 #define GPIP_GPADC_FIFO_UNDERRUN_CLR (1 << 10U) 81 #define GPIP_GPADC_RDY_MASK (1 << 12U) 82 #define GPIP_GPADC_FIFO_OVERRUN_MASK (1 << 13U) 83 #define GPIP_GPADC_FIFO_UNDERRUN_MASK (1 << 14U) 84 #if defined(BL702) || defined(BL702L) 85 #define GPIP_GPADC_FIFO_RDY_MASK (1 << 15U) 86 #endif 87 #define GPIP_GPADC_FIFO_DATA_COUNT_SHIFT (16U) 88 #define GPIP_GPADC_FIFO_DATA_COUNT_MASK (0x3f << GPIP_GPADC_FIFO_DATA_COUNT_SHIFT) 89 #define GPIP_GPADC_FIFO_THL_SHIFT (22U) 90 #define GPIP_GPADC_FIFO_THL_MASK (0x3 << GPIP_GPADC_FIFO_THL_SHIFT) 91 92 /* 0x4 : gpadc_dma_rdata */ 93 #define GPIP_GPADC_DMA_RDATA_SHIFT (0U) 94 #define GPIP_GPADC_DMA_RDATA_MASK (0x3ffffff << GPIP_GPADC_DMA_RDATA_SHIFT) 95 96 /* 0x20 : gpadc_pir_train */ 97 #define GPIP_PIR_EXTEND_SHIFT (0U) 98 #define GPIP_PIR_EXTEND_MASK (0x1f << GPIP_PIR_EXTEND_SHIFT) 99 #define GPIP_PIR_CNT_V_SHIFT (8U) 100 #define GPIP_PIR_CNT_V_MASK (0x1f << GPIP_PIR_CNT_V_SHIFT) 101 #define GPIP_PIR_TRAIN (1 << 16U) 102 #define GPIP_PIR_STOP (1 << 17U) 103 104 /* 0x90C : gpadc_reg_cmd */ 105 #define AON_GPADC_GLOBAL_EN (1 << 0U) 106 #define AON_GPADC_CONV_START (1 << 1U) 107 #define AON_GPADC_SOFT_RST (1 << 2U) 108 #define AON_GPADC_NEG_SEL_SHIFT (3U) 109 #define AON_GPADC_NEG_SEL_MASK (0x1f << AON_GPADC_NEG_SEL_SHIFT) 110 #define AON_GPADC_POS_SEL_SHIFT (8U) 111 #define AON_GPADC_POS_SEL_MASK (0x1f << AON_GPADC_POS_SEL_SHIFT) 112 #define AON_GPADC_NEG_GND (1 << 13U) 113 #define AON_GPADC_MICBIAS_EN (1 << 14U) 114 #define AON_GPADC_MICPGA_EN (1 << 15U) 115 #define AON_GPADC_BYP_MICBOOST (1 << 16U) 116 #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 117 #define AON_GPADC_RCAL_EN (1 << 17U) 118 #endif 119 #define AON_GPADC_DWA_EN (1 << 18U) 120 #define AON_GPADC_MIC2_DIFF (1 << 19U) 121 #define AON_GPADC_MIC1_DIFF (1 << 20U) 122 #define AON_GPADC_MIC_PGA2_GAIN_SHIFT (21U) 123 #define AON_GPADC_MIC_PGA2_GAIN_MASK (0x3 << AON_GPADC_MIC_PGA2_GAIN_SHIFT) 124 #define AON_GPADC_MICBOOST_32DB_EN (1 << 23U) 125 #define AON_GPADC_CHIP_SEN_PU (1 << 27U) 126 #define AON_GPADC_SEN_SEL_SHIFT (28U) 127 #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 128 #define AON_GPADC_SEN_SEL_MASK (0x7 << AON_GPADC_SEN_SEL_SHIFT) 129 #define AON_GPADC_SEN_TEST_EN (1 << 31U) 130 #elif defined(BL702) || defined(BL602) || defined(BL702L) 131 #define AON_GPADC_SEN_SEL_MASK (0x3 << AON_GPADC_SEN_SEL_SHIFT) 132 #define AON_GPADC_SEN_TEST_EN (1 << 30U) 133 #endif 134 135 /* 0x910 : gpadc_reg_config1 */ 136 #define AON_GPADC_CAL_OS_EN (1 << 0U) 137 #define AON_GPADC_CONT_CONV_EN (1 << 1U) 138 #define AON_GPADC_RES_SEL_SHIFT (2U) 139 #define AON_GPADC_RES_SEL_MASK (0x7 << AON_GPADC_RES_SEL_SHIFT) 140 #define AON_GPADC_VCM_SEL_EN (1 << 8U) 141 #define AON_GPADC_VCM_HYST_SEL (1 << 9U) 142 #define AON_GPADC_LOWV_DET_EN (1 << 10U) 143 #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 144 #define AON_GPADC_PWM_TRG_EN (1 << 11U) 145 #define AON_GPADC_CLK_ANA_DLY_SHIFT (12U) 146 #define AON_GPADC_CLK_ANA_DLY_MASK (0xf << AON_GPADC_CLK_ANA_DLY_SHIFT) 147 #define AON_GPADC_CLK_ANA_DLY_EN (1 << 16U) 148 #endif 149 #define AON_GPADC_CLK_ANA_INV (1 << 17U) 150 #define AON_GPADC_CLK_DIV_RATIO_SHIFT (18U) 151 #define AON_GPADC_CLK_DIV_RATIO_MASK (0x7 << AON_GPADC_CLK_DIV_RATIO_SHIFT) 152 #define AON_GPADC_SCAN_LENGTH_SHIFT (21U) 153 #define AON_GPADC_SCAN_LENGTH_MASK (0xf << AON_GPADC_SCAN_LENGTH_SHIFT) 154 #define AON_GPADC_SCAN_EN (1 << 25U) 155 #define AON_GPADC_DITHER_EN (1 << 26U) 156 #define AON_GPADC_V11_SEL_SHIFT (27U) 157 #define AON_GPADC_V11_SEL_MASK (0x3 << AON_GPADC_V11_SEL_SHIFT) 158 #define AON_GPADC_V18_SEL_SHIFT (29U) 159 #define AON_GPADC_V18_SEL_MASK (0x3 << AON_GPADC_V18_SEL_SHIFT) 160 161 /* 0x914 : gpadc_reg_config2 */ 162 #define AON_GPADC_DIFF_MODE (1 << 2U) 163 #define AON_GPADC_VREF_SEL (1 << 3U) 164 #define AON_GPADC_VBAT_EN (1 << 4U) 165 #define AON_GPADC_TSEXT_SEL (1 << 5U) 166 #define AON_GPADC_TS_EN (1 << 6U) 167 #define AON_GPADC_PGA_VCM_SHIFT (7U) 168 #define AON_GPADC_PGA_VCM_MASK (0x3 << AON_GPADC_PGA_VCM_SHIFT) 169 #define AON_GPADC_PGA_OS_CAL_SHIFT (9U) 170 #define AON_GPADC_PGA_OS_CAL_MASK (0xf << AON_GPADC_PGA_OS_CAL_SHIFT) 171 #define AON_GPADC_PGA_EN (1 << 13U) 172 #define AON_GPADC_PGA_VCMI_EN (1 << 14U) 173 #define AON_GPADC_CHOP_MODE_SHIFT (15U) 174 #define AON_GPADC_CHOP_MODE_MASK (0x3 << AON_GPADC_CHOP_MODE_SHIFT) 175 #define AON_GPADC_BIAS_SEL (1 << 17U) 176 #define AON_GPADC_TEST_EN (1 << 18U) 177 #define AON_GPADC_TEST_SEL_SHIFT (19U) 178 #define AON_GPADC_TEST_SEL_MASK (0x7 << AON_GPADC_TEST_SEL_SHIFT) 179 #define AON_GPADC_PGA2_GAIN_SHIFT (22U) 180 #define AON_GPADC_PGA2_GAIN_MASK (0x7 << AON_GPADC_PGA2_GAIN_SHIFT) 181 #define AON_GPADC_PGA1_GAIN_SHIFT (25U) 182 #define AON_GPADC_PGA1_GAIN_MASK (0x7 << AON_GPADC_PGA1_GAIN_SHIFT) 183 #define AON_GPADC_DLY_SEL_SHIFT (28U) 184 #define AON_GPADC_DLY_SEL_MASK (0x7 << AON_GPADC_DLY_SEL_SHIFT) 185 #define AON_GPADC_TSVBE_LOW (1 << 31U) 186 187 /* 0x918 : adc converation sequence 1 */ 188 #define AON_GPADC_SCAN_POS_0_SHIFT (0U) 189 #define AON_GPADC_SCAN_POS_0_MASK (0x1f << AON_GPADC_SCAN_POS_0_SHIFT) 190 #define AON_GPADC_SCAN_POS_1_SHIFT (5U) 191 #define AON_GPADC_SCAN_POS_1_MASK (0x1f << AON_GPADC_SCAN_POS_1_SHIFT) 192 #define AON_GPADC_SCAN_POS_2_SHIFT (10U) 193 #define AON_GPADC_SCAN_POS_2_MASK (0x1f << AON_GPADC_SCAN_POS_2_SHIFT) 194 #define AON_GPADC_SCAN_POS_3_SHIFT (15U) 195 #define AON_GPADC_SCAN_POS_3_MASK (0x1f << AON_GPADC_SCAN_POS_3_SHIFT) 196 #define AON_GPADC_SCAN_POS_4_SHIFT (20U) 197 #define AON_GPADC_SCAN_POS_4_MASK (0x1f << AON_GPADC_SCAN_POS_4_SHIFT) 198 #define AON_GPADC_SCAN_POS_5_SHIFT (25U) 199 #define AON_GPADC_SCAN_POS_5_MASK (0x1f << AON_GPADC_SCAN_POS_5_SHIFT) 200 201 /* 0x91C : adc converation sequence 2 */ 202 #define AON_GPADC_SCAN_POS_6_SHIFT (0U) 203 #define AON_GPADC_SCAN_POS_6_MASK (0x1f << AON_GPADC_SCAN_POS_6_SHIFT) 204 #define AON_GPADC_SCAN_POS_7_SHIFT (5U) 205 #define AON_GPADC_SCAN_POS_7_MASK (0x1f << AON_GPADC_SCAN_POS_7_SHIFT) 206 #define AON_GPADC_SCAN_POS_8_SHIFT (10U) 207 #define AON_GPADC_SCAN_POS_8_MASK (0x1f << AON_GPADC_SCAN_POS_8_SHIFT) 208 #define AON_GPADC_SCAN_POS_9_SHIFT (15U) 209 #define AON_GPADC_SCAN_POS_9_MASK (0x1f << AON_GPADC_SCAN_POS_9_SHIFT) 210 #define AON_GPADC_SCAN_POS_10_SHIFT (20U) 211 #define AON_GPADC_SCAN_POS_10_MASK (0x1f << AON_GPADC_SCAN_POS_10_SHIFT) 212 #define AON_GPADC_SCAN_POS_11_SHIFT (25U) 213 #define AON_GPADC_SCAN_POS_11_MASK (0x1f << AON_GPADC_SCAN_POS_11_SHIFT) 214 215 /* 0x920 : adc converation sequence 3 */ 216 #define AON_GPADC_SCAN_NEG_0_SHIFT (0U) 217 #define AON_GPADC_SCAN_NEG_0_MASK (0x1f << AON_GPADC_SCAN_NEG_0_SHIFT) 218 #define AON_GPADC_SCAN_NEG_1_SHIFT (5U) 219 #define AON_GPADC_SCAN_NEG_1_MASK (0x1f << AON_GPADC_SCAN_NEG_1_SHIFT) 220 #define AON_GPADC_SCAN_NEG_2_SHIFT (10U) 221 #define AON_GPADC_SCAN_NEG_2_MASK (0x1f << AON_GPADC_SCAN_NEG_2_SHIFT) 222 #define AON_GPADC_SCAN_NEG_3_SHIFT (15U) 223 #define AON_GPADC_SCAN_NEG_3_MASK (0x1f << AON_GPADC_SCAN_NEG_3_SHIFT) 224 #define AON_GPADC_SCAN_NEG_4_SHIFT (20U) 225 #define AON_GPADC_SCAN_NEG_4_MASK (0x1f << AON_GPADC_SCAN_NEG_4_SHIFT) 226 #define AON_GPADC_SCAN_NEG_5_SHIFT (25U) 227 #define AON_GPADC_SCAN_NEG_5_MASK (0x1f << AON_GPADC_SCAN_NEG_5_SHIFT) 228 229 /* 0x924 : adc converation sequence 4 */ 230 #define AON_GPADC_SCAN_NEG_6_SHIFT (0U) 231 #define AON_GPADC_SCAN_NEG_6_MASK (0x1f << AON_GPADC_SCAN_NEG_6_SHIFT) 232 #define AON_GPADC_SCAN_NEG_7_SHIFT (5U) 233 #define AON_GPADC_SCAN_NEG_7_MASK (0x1f << AON_GPADC_SCAN_NEG_7_SHIFT) 234 #define AON_GPADC_SCAN_NEG_8_SHIFT (10U) 235 #define AON_GPADC_SCAN_NEG_8_MASK (0x1f << AON_GPADC_SCAN_NEG_8_SHIFT) 236 #define AON_GPADC_SCAN_NEG_9_SHIFT (15U) 237 #define AON_GPADC_SCAN_NEG_9_MASK (0x1f << AON_GPADC_SCAN_NEG_9_SHIFT) 238 #define AON_GPADC_SCAN_NEG_10_SHIFT (20U) 239 #define AON_GPADC_SCAN_NEG_10_MASK (0x1f << AON_GPADC_SCAN_NEG_10_SHIFT) 240 #define AON_GPADC_SCAN_NEG_11_SHIFT (25U) 241 #define AON_GPADC_SCAN_NEG_11_MASK (0x1f << AON_GPADC_SCAN_NEG_11_SHIFT) 242 243 /* 0x928 : gpadc_reg_status */ 244 #define AON_GPADC_DATA_RDY (1 << 0U) 245 #define AON_GPADC_RESERVED_SHIFT (16U) 246 #define AON_GPADC_RESERVED_MASK (0xffff << AON_GPADC_RESERVED_SHIFT) 247 248 /* 0x92C : gpadc_reg_isr */ 249 #define AON_GPADC_NEG_SATUR (1 << 0U) 250 #define AON_GPADC_POS_SATUR (1 << 1U) 251 #define AON_GPADC_NEG_SATUR_CLR (1 << 4U) 252 #define AON_GPADC_POS_SATUR_CLR (1 << 5U) 253 #define AON_GPADC_NEG_SATUR_MASK (1 << 8U) 254 #define AON_GPADC_POS_SATUR_MASK (1 << 9U) 255 256 /* 0x930 : gpadc_reg_result */ 257 #define AON_GPADC_DATA_OUT_SHIFT (0U) 258 #define AON_GPADC_DATA_OUT_MASK (0x3ffffff << AON_GPADC_DATA_OUT_SHIFT) 259 260 /* 0x934 : gpadc_reg_raw_result */ 261 #define AON_GPADC_RAW_DATA_SHIFT (0U) 262 #define AON_GPADC_RAW_DATA_MASK (0xfff << AON_GPADC_RAW_DATA_SHIFT) 263 264 /* 0x938 : gpadc_reg_define */ 265 #define AON_GPADC_OS_CAL_DATA_SHIFT (0U) 266 #define AON_GPADC_OS_CAL_DATA_MASK (0xffff << AON_GPADC_OS_CAL_DATA_SHIFT) 267 268 #endif /* __HARDWARE_ADC_H__ */ 269