1 /** 2 ****************************************************************************** 3 * @file auadc_reg.h 4 * @version V1.0 5 * @date 2022-12-03 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __AUADC_REG_H__ 37 #define __AUADC_REG_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define AUADC_AUDPDM_TOP_OFFSET (0x00) /* audpdm_top */ 46 #define AUADC_AUDPDM_ITF_OFFSET (0x04) /* audpdm_itf */ 47 #define AUADC_PDM_ADC_0_OFFSET (0x08) /* pdm_adc_0 */ 48 #define AUADC_PDM_ADC_1_OFFSET (0x0C) /* pdm_adc_1 */ 49 #define AUADC_PDM_DAC_0_OFFSET (0x10) /* pdm_dac_0 */ 50 #define AUADC_PDM_PDM_0_OFFSET (0x1C) /* pdm_pdm_0 */ 51 #define AUADC_PDM_ADC_S0_OFFSET (0x38) /* pdm_adc_s0 */ 52 #define AUADC_AUDADC_ANA_CFG1_OFFSET (0x60) /* audadc_ana_cfg1 */ 53 #define AUADC_AUDADC_ANA_CFG2_OFFSET (0x64) /* audadc_ana_cfg2 */ 54 #define AUADC_AUDADC_CMD_OFFSET (0x68) /* audadc_cmd */ 55 #define AUADC_AUDADC_DATA_OFFSET (0x6C) /* audadc_data */ 56 #define AUADC_AUDADC_RX_FIFO_CTRL_OFFSET (0x80) /* audadc_rx_fifo_ctrl */ 57 #define AUADC_AUDADC_RX_FIFO_STATUS_OFFSET (0x84) /* audadc_rx_fifo_status */ 58 #define AUADC_AUDADC_RX_FIFO_DATA_OFFSET (0x88) /* audadc_rx_fifo_data */ 59 60 /* Register Bitfield definitions *****************************************************/ 61 62 /* 0xC00 : audpdm_top */ 63 #define AUADC_AUDIO_CKG_EN (1 << 0U) 64 #define AUADC_ADC_ITF_INV_SEL (1 << 2U) 65 #define AUADC_PDM_ITF_INV_SEL (1 << 3U) 66 #define AUADC_ADC_RATE_SHIFT (28U) 67 #define AUADC_ADC_RATE_MASK (0xf << AUADC_ADC_RATE_SHIFT) 68 69 /* 0xC04 : audpdm_itf */ 70 #define AUADC_ADC_0_EN (1 << 0U) 71 #define AUADC_ADC_ITF_EN (1 << 30U) 72 73 /* 0xC08 : pdm_adc_0 */ 74 #define AUADC_ADC_0_FIR_MODE (1 << 0U) 75 76 /* 0xC0C : pdm_adc_1 */ 77 #define AUADC_ADC_0_K1_SHIFT (0U) 78 #define AUADC_ADC_0_K1_MASK (0xf << AUADC_ADC_0_K1_SHIFT) 79 #define AUADC_ADC_0_K1_EN (1 << 4U) 80 #define AUADC_ADC_0_K2_SHIFT (5U) 81 #define AUADC_ADC_0_K2_MASK (0xf << AUADC_ADC_0_K2_SHIFT) 82 #define AUADC_ADC_0_K2_EN (1 << 9U) 83 84 /* 0xC10 : pdm_dac_0 */ 85 #define AUADC_ADC_PDM_H_SHIFT (0U) 86 #define AUADC_ADC_PDM_H_MASK (0xf << AUADC_ADC_PDM_H_SHIFT) 87 #define AUADC_ADC_PDM_L_SHIFT (6U) 88 #define AUADC_ADC_PDM_L_MASK (0xf << AUADC_ADC_PDM_L_SHIFT) 89 #define AUADC_ADC_0_SRC (1 << 12U) 90 91 /* 0xC1C : pdm_pdm_0 */ 92 #define AUADC_PDM_0_EN (1 << 0U) 93 #define AUADC_ADC_0_PDM_SEL_SHIFT (3U) 94 #define AUADC_ADC_0_PDM_SEL_MASK (0x7 << AUADC_ADC_0_PDM_SEL_SHIFT) 95 96 /* 0xC38 : pdm_adc_s0 */ 97 #define AUADC_ADC_S0_VOLUME_SHIFT (0U) 98 #define AUADC_ADC_S0_VOLUME_MASK (0x1ff << AUADC_ADC_S0_VOLUME_SHIFT) 99 100 /* 0xC60 : audadc_ana_cfg1 */ 101 #define AUADC_AUDADC_PGA_CHOP_CKSEL (1 << 0U) 102 #define AUADC_AUDADC_PGA_CHOP_FREQ_SHIFT (1U) 103 #define AUADC_AUDADC_PGA_CHOP_FREQ_MASK (0x7 << AUADC_AUDADC_PGA_CHOP_FREQ_SHIFT) 104 #define AUADC_AUDADC_PGA_CHOP_EN (1 << 4U) 105 #define AUADC_AUDADC_PGA_CHOP_CFG_SHIFT (5U) 106 #define AUADC_AUDADC_PGA_CHOP_CFG_MASK (0x3 << AUADC_AUDADC_PGA_CHOP_CFG_SHIFT) 107 #define AUADC_AUDADC_PGA_RHPAS_SEL_SHIFT (8U) 108 #define AUADC_AUDADC_PGA_RHPAS_SEL_MASK (0x3 << AUADC_AUDADC_PGA_RHPAS_SEL_SHIFT) 109 #define AUADC_AUDADC_PGA_NOIS_CTRL_SHIFT (12U) 110 #define AUADC_AUDADC_PGA_NOIS_CTRL_MASK (0x3 << AUADC_AUDADC_PGA_NOIS_CTRL_SHIFT) 111 #define AUADC_AUDADC_ICTRL_PGA_AAF_SHIFT (16U) 112 #define AUADC_AUDADC_ICTRL_PGA_AAF_MASK (0x3 << AUADC_AUDADC_ICTRL_PGA_AAF_SHIFT) 113 #define AUADC_AUDADC_ICTRL_PGA_MIC_SHIFT (20U) 114 #define AUADC_AUDADC_ICTRL_PGA_MIC_MASK (0x3 << AUADC_AUDADC_ICTRL_PGA_MIC_SHIFT) 115 #define AUADC_AUDADC_PGA_LP_EN (1 << 24U) 116 #define AUADC_AUDADC_CKB_EN (1 << 28U) 117 #define AUADC_AUDADC_SEL_EDGE (1 << 29U) 118 119 /* 0xC64 : audadc_ana_cfg2 */ 120 #define AUADC_AUDADC_DITHER_ORDER (1 << 0U) 121 #define AUADC_AUDADC_DITHER_SEL_SHIFT (1U) 122 #define AUADC_AUDADC_DITHER_SEL_MASK (0x3 << AUADC_AUDADC_DITHER_SEL_SHIFT) 123 #define AUADC_AUDADC_DITHER_ENA (1 << 3U) 124 #define AUADC_AUDADC_QUAN_GAIN_SHIFT (4U) 125 #define AUADC_AUDADC_QUAN_GAIN_MASK (0x3 << AUADC_AUDADC_QUAN_GAIN_SHIFT) 126 #define AUADC_AUDADC_DEM_EN (1 << 8U) 127 #define AUADC_AUDADC_NCTRL_ADC2_SHIFT (12U) 128 #define AUADC_AUDADC_NCTRL_ADC2_MASK (0x3 << AUADC_AUDADC_NCTRL_ADC2_SHIFT) 129 #define AUADC_AUDADC_NCTRL_ADC1_SHIFT (16U) 130 #define AUADC_AUDADC_NCTRL_ADC1_MASK (0x7 << AUADC_AUDADC_NCTRL_ADC1_SHIFT) 131 #define AUADC_AUDADC_ICTRL_ADC_SHIFT (20U) 132 #define AUADC_AUDADC_ICTRL_ADC_MASK (0x3 << AUADC_AUDADC_ICTRL_ADC_SHIFT) 133 #define AUADC_AUDADC_SDM_LP_EN (1 << 24U) 134 #define AUADC_AUDADC_RESERVED_SHIFT (28U) 135 #define AUADC_AUDADC_RESERVED_MASK (0x3 << AUADC_AUDADC_RESERVED_SHIFT) 136 137 /* 0xC68 : audadc_cmd */ 138 #define AUADC_AUDADC_MEAS_ODR_SEL_SHIFT (0U) 139 #define AUADC_AUDADC_MEAS_ODR_SEL_MASK (0xf << AUADC_AUDADC_MEAS_ODR_SEL_SHIFT) 140 #define AUADC_AUDADC_MEAS_FILTER_TYPE (1 << 4U) 141 #define AUADC_AUDADC_MEAS_FILTER_EN (1 << 5U) 142 #define AUADC_AUDADC_AUDIO_OSR_SEL (1 << 6U) 143 #define AUADC_AUDADC_PGA_GAIN_SHIFT (8U) 144 #define AUADC_AUDADC_PGA_GAIN_MASK (0xf << AUADC_AUDADC_PGA_GAIN_SHIFT) 145 #define AUADC_AUDADC_PGA_MODE_SHIFT (12U) 146 #define AUADC_AUDADC_PGA_MODE_MASK (0x3 << AUADC_AUDADC_PGA_MODE_SHIFT) 147 #define AUADC_AUDADC_CHANNEL_SELN_SHIFT (16U) 148 #define AUADC_AUDADC_CHANNEL_SELN_MASK (0x7 << AUADC_AUDADC_CHANNEL_SELN_SHIFT) 149 #define AUADC_AUDADC_CHANNEL_SELP_SHIFT (20U) 150 #define AUADC_AUDADC_CHANNEL_SELP_MASK (0x7 << AUADC_AUDADC_CHANNEL_SELP_SHIFT) 151 #define AUADC_AUDADC_CHANNEL_EN_SHIFT (24U) 152 #define AUADC_AUDADC_CHANNEL_EN_MASK (0x3 << AUADC_AUDADC_CHANNEL_EN_SHIFT) 153 #define AUADC_AUDADC_CONV (1 << 28U) 154 #define AUADC_AUDADC_SDM_PU (1 << 29U) 155 #define AUADC_AUDADC_PGA_PU (1 << 30U) 156 157 /* 0xC6C : audadc_data */ 158 #define AUADC_AUDADC_RAW_DATA_SHIFT (0U) 159 #define AUADC_AUDADC_RAW_DATA_MASK (0xffffff << AUADC_AUDADC_RAW_DATA_SHIFT) 160 #define AUADC_AUDADC_DATA_RDY (1 << 24U) 161 #define AUADC_AUDADC_SOFT_RST (1 << 29U) 162 #define AUADC_AUDADC_VALID_4S_VAL (1 << 30U) 163 #define AUADC_AUDADC_VALID_4S_EN (1 << 31U) 164 165 /* 0xC80 : audadc_rx_fifo_ctrl */ 166 #define AUADC_RX_FIFO_FLUSH (1 << 0U) 167 #define AUADC_RXO_INT_EN (1 << 1U) 168 #define AUADC_RXU_INT_EN (1 << 2U) 169 #define AUADC_RXA_INT_EN (1 << 3U) 170 #define AUADC_RX_DRQ_EN (1 << 4U) 171 #define AUADC_RX_DATA_RES_SHIFT (5U) 172 #define AUADC_RX_DATA_RES_MASK (0x3 << AUADC_RX_DATA_RES_SHIFT) 173 #define AUADC_RX_CH_EN (1 << 8U) 174 #define AUADC_RX_DRQ_CNT_SHIFT (14U) 175 #define AUADC_RX_DRQ_CNT_MASK (0x3 << AUADC_RX_DRQ_CNT_SHIFT) 176 #define AUADC_RX_TRG_LEVEL_SHIFT (16U) 177 #define AUADC_RX_TRG_LEVEL_MASK (0xf << AUADC_RX_TRG_LEVEL_SHIFT) 178 #define AUADC_RX_DATA_MODE_SHIFT (24U) 179 #define AUADC_RX_DATA_MODE_MASK (0x3 << AUADC_RX_DATA_MODE_SHIFT) 180 181 /* 0xC84 : audadc_rx_fifo_status */ 182 #define AUADC_RXO_INT (1 << 1U) 183 #define AUADC_RXU_INT (1 << 2U) 184 #define AUADC_RXA_INT (1 << 4U) 185 #define AUADC_RXA_CNT_SHIFT (16U) 186 #define AUADC_RXA_CNT_MASK (0xf << AUADC_RXA_CNT_SHIFT) 187 #define AUADC_RXA (1 << 24U) 188 189 /* 0xC88 : audadc_rx_fifo_data */ 190 #define AUADC_RX_DATA_SHIFT (0U) 191 #define AUADC_RX_DATA_MASK (0xffffffff << AUADC_RX_DATA_SHIFT) 192 193 #endif /* __AUADC_REG_H__ */ 194