1 /** 2 ****************************************************************************** 3 * @file cam_reg.h 4 * @version V1.0 5 * @date 2022-11-30 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_CAM_H__ 37 #define __HARDWARE_CAM_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define CAM_DVP2AXI_CONFIGUE_OFFSET (0x0)/* dvp2axi_configue */ 46 #define CAM_DVP2AXI_ADDR_START_OFFSET (0x4)/* dvp2axi_addr_start */ 47 #define CAM_DVP2AXI_MEM_BCNT_OFFSET (0x8)/* dvp2axi_mem_bcnt */ 48 #define CAM_DVP2AXI_HSYNC_CROP_OFFSET (0x30)/* dvp2axi_hsync_crop */ 49 #define CAM_DVP2AXI_VSYNC_CROP_OFFSET (0x34)/* dvp2axi_vsync_crop */ 50 #define CAM_DVP2AXI_FRAM_EXM_OFFSET (0x38)/* dvp2axi_fram_exm */ 51 #define CAM_FRAME_START_ADDR0_OFFSET (0x40)/* frame_start_addr0 */ 52 #define CAM_FRAME_START_ADDR1_OFFSET (0x48)/* frame_start_addr1 */ 53 #define CAM_FRAME_START_ADDR2_OFFSET (0x50)/* frame_start_addr2 */ 54 #define CAM_FRAME_START_ADDR3_OFFSET (0x58)/* frame_start_addr3 */ 55 #if defined(BL702) 56 #define CAM_DVP2AXI_FRAME_BCNT_0_OFFSET (0xC)/* dvp2axi_frame_bcnt_0 */ 57 #define CAM_DVP2AXI_ADDR_START_1_OFFSET (0x10)/* dvp2axi_addr_start_1 */ 58 #define CAM_DVP2AXI_MEM_BCNT_1_OFFSET (0x14)/* dvp2axi_mem_bcnt_1 */ 59 #define CAM_DVP2AXI_FRAME_BCNT_1_OFFSET (0x18)/* dvp2axi_frame_bcnt_1 */ 60 #define CAM_DVP_STATUS_AND_ERROR_OFFSET (0x1C)/* dvp_status_and_error */ 61 #define CAM_DVP_FRAME_FIFO_POP_OFFSET (0x20)/* dvp_frame_fifo_pop */ 62 #define CAM_SNSR_CONTROL_OFFSET (0x24)/* snsr_control */ 63 #define CAM_INT_CONTROL_OFFSET (0x28)/* int_control */ 64 #define CAM_FRAME_BYTE_CNT0_0_OFFSET (0x44)/* frame_byte_cnt0_0 */ 65 #define CAM_FRAME_BYTE_CNT0_1_OFFSET (0x4C)/* frame_byte_cnt0_1 */ 66 #define CAM_FRAME_BYTE_CNT0_2_OFFSET (0x54)/* frame_byte_cnt0_2 */ 67 #define CAM_FRAME_BYTE_CNT0_3_OFFSET (0x5C)/* frame_byte_cnt0_3 */ 68 #define CAM_FRAME_START_ADDR0_4_OFFSET (0x60)/* frame_start_addr0_4 */ 69 #define CAM_FRAME_BYTE_CNT0_4_OFFSET (0x64)/* frame_byte_cnt0_4 */ 70 #define CAM_FRAME_START_ADDR0_5_OFFSET (0x68)/* frame_start_addr0_5 */ 71 #define CAM_FRAME_BYTE_CNT0_5_OFFSET (0x6C)/* frame_byte_cnt0_5 */ 72 #define CAM_FRAME_START_ADDR0_6_OFFSET (0x70)/* frame_start_addr0_6 */ 73 #define CAM_FRAME_BYTE_CNT0_6_OFFSET (0x74)/* frame_byte_cnt0_6 */ 74 #define CAM_FRAME_START_ADDR0_7_OFFSET (0x78)/* frame_start_addr0_7 */ 75 #define CAM_FRAME_BYTE_CNT0_7_OFFSET (0x7C)/* frame_byte_cnt0_7 */ 76 #define CAM_FRAME_START_ADDR1_0_OFFSET (0x80)/* frame_start_addr1_0 */ 77 #define CAM_FRAME_BYTE_CNT1_0_OFFSET (0x84)/* frame_byte_cnt1_0 */ 78 #define CAM_FRAME_START_ADDR1_1_OFFSET (0x88)/* frame_start_addr1_1 */ 79 #define CAM_FRAME_BYTE_CNT1_1_OFFSET (0x8C)/* frame_byte_cnt1_1 */ 80 #define CAM_FRAME_START_ADDR1_2_OFFSET (0x90)/* frame_start_addr1_2 */ 81 #define CAM_FRAME_BYTE_CNT1_2_OFFSET (0x94)/* frame_byte_cnt1_2 */ 82 #define CAM_FRAME_START_ADDR1_3_OFFSET (0x98)/* frame_start_addr1_3 */ 83 #define CAM_FRAME_BYTE_CNT1_3_OFFSET (0x9C)/* frame_byte_cnt1_3 */ 84 #define CAM_FRAME_START_ADDR1_4_OFFSET (0xA0)/* frame_start_addr1_4 */ 85 #define CAM_FRAME_BYTE_CNT1_4_OFFSET (0xA4)/* frame_byte_cnt1_4 */ 86 #define CAM_FRAME_START_ADDR1_5_OFFSET (0xA8)/* frame_start_addr1_5 */ 87 #define CAM_FRAME_BYTE_CNT1_5_OFFSET (0xAC)/* frame_byte_cnt1_5 */ 88 #define CAM_FRAME_START_ADDR1_6_OFFSET (0xB0)/* frame_start_addr1_6 */ 89 #define CAM_FRAME_BYTE_CNT1_6_OFFSET (0xB4)/* frame_byte_cnt1_6 */ 90 #define CAM_FRAME_START_ADDR1_7_OFFSET (0xB8)/* frame_start_addr1_7 */ 91 #define CAM_FRAME_BYTE_CNT1_7_OFFSET (0xBC)/* frame_byte_cnt1_7 */ 92 #define CAM_DVP_DEBUG_OFFSET (0xFF0)/* dvp_debug */ 93 #define CAM_DVP_DUMMY_REG_OFFSET (0xFFC)/* dvp_dummy_reg */ 94 #else 95 #define CAM_DVP_STATUS_AND_ERROR_OFFSET (0xC)/* dvp_status_and_error */ 96 #define CAM_DVP2AXI_FRAME_BCNT_OFFSET (0x10)/* dvp2axi_frame_bcnt */ 97 #define CAM_DVP_FRAME_FIFO_POP_OFFSET (0x14)/* dvp_frame_fifo_pop */ 98 #define CAM_DVP2AXI_FRAME_VLD_OFFSET (0x18)/* dvp2axi_frame_vld */ 99 #define CAM_DVP2AXI_FRAME_PERIOD_OFFSET (0x1C)/* dvp2axi_frame_period */ 100 #define CAM_DVP2AXI_MISC_OFFSET (0x20)/* dvp2axi_misc */ 101 #define CAM_FRAME_ID_STS01_OFFSET (0x60)/* frame_id_sts01 */ 102 #define CAM_FRAME_ID_STS23_OFFSET (0x64)/* frame_id_sts23 */ 103 #define CAM_DVP_DEBUG_OFFSET (0xF0)/* dvp_debug */ 104 #define CAM_DVP_DUMMY_REG_OFFSET (0xFC)/* dvp_dummy_reg */ 105 #endif 106 107 /* Register Bitfield definitions *****************************************************/ 108 109 /* 0x0 : dvp2axi_configue */ 110 #define CAM_REG_DVP_ENABLE (1<<0U) 111 #define CAM_REG_SW_MODE (1<<1U) 112 #define CAM_REG_FRAM_VLD_POL (1<<2U) 113 #define CAM_REG_LINE_VLD_POL (1<<3U) 114 #define CAM_REG_XLEN_SHIFT (4U) 115 #if defined(BL702) 116 #define CAM_REG_XLEN_MASK (0x3<<CAM_REG_XLEN_SHIFT) 117 #else 118 #define CAM_REG_XLEN_MASK (0x7<<CAM_REG_XLEN_SHIFT) 119 #endif 120 #define CAM_REG_DVP_MODE_SHIFT (8U) 121 #define CAM_REG_DVP_MODE_MASK (0x7<<CAM_REG_DVP_MODE_SHIFT) 122 #define CAM_REG_HW_MODE_FWRAP (1<<11U) 123 #define CAM_REG_DROP_EN (1<<12U) 124 #define CAM_REG_DROP_EVEN (1<<13U) 125 #if defined(BL702) 126 #define CAM_REG_SUBSAMPLE_EN (1<<14U) 127 #define CAM_REG_SUBSAMPLE_EVEN (1<<15U) 128 #define CAM_REG_INTERLV_MODE (1<<16U) 129 #else 130 #define CAM_REG_QOS_SW_MODE (1<<14U) 131 #define CAM_REG_QOS_SW (1<<15U) 132 #define CAM_REG_DVP_DATA_MODE_SHIFT (16U) 133 #define CAM_REG_DVP_DATA_MODE_MASK (0x7<<CAM_REG_DVP_DATA_MODE_SHIFT) 134 #define CAM_REG_DVP_DATA_BSEL (1<<19U) 135 #endif 136 #define CAM_REG_DVP_PIX_CLK_CG (1<<20U) 137 #if !defined(BL702) 138 #define CAM_REG_V_SUBSAMPLE_EN (1<<22U) 139 #define CAM_REG_V_SUBSAMPLE_POL (1<<23U) 140 #endif 141 #define CAM_REG_DVP_WAIT_CYCLE_SHIFT (24U) 142 #define CAM_REG_DVP_WAIT_CYCLE_MASK (0xff<<CAM_REG_DVP_WAIT_CYCLE_SHIFT) 143 144 /* 0x4 : dvp2axi_addr_start */ 145 #define CAM_REG_ADDR_START_SHIFT (0U) 146 #define CAM_REG_ADDR_START_MASK (0xffffffff<<CAM_REG_ADDR_START_SHIFT) 147 148 /* 0x8 : dvp2axi_mem_bcnt */ 149 #define CAM_REG_MEM_BURST_CNT_SHIFT (0U) 150 #define CAM_REG_MEM_BURST_CNT_MASK (0xffffffff<<CAM_REG_MEM_BURST_CNT_SHIFT) 151 152 #if defined(BL702) 153 /* 0xC : dvp2ahb_frame_bcnt_0 */ 154 #define CAM_REG_FRAME_BURST_CNT_0_SHIFT (0U) 155 #define CAM_REG_FRAME_BURST_CNT_0_MASK (0xffffffff<<CAM_REG_FRAME_BURST_CNT_0_SHIFT) 156 157 /* 0x10 : dvp2ahb_addr_start_1 */ 158 #define CAM_REG_ADDR_START_1_SHIFT (0U) 159 #define CAM_REG_ADDR_START_1_MASK (0xffffffff<<CAM_REG_ADDR_START_1_SHIFT) 160 161 /* 0x14 : dvp2ahb_mem_bcnt_1 */ 162 #define CAM_REG_MEM_BURST_CNT_1_SHIFT (0U) 163 #define CAM_REG_MEM_BURST_CNT_1_MASK (0xffffffff<<CAM_REG_MEM_BURST_CNT_1_SHIFT) 164 165 /* 0x18 : dvp2ahb_frame_bcnt_1 */ 166 #define CAM_REG_FRAME_BURST_CNT_1_SHIFT (0U) 167 #define CAM_REG_FRAME_BURST_CNT_1_MASK (0xffffffff<<CAM_REG_FRAME_BURST_CNT_1_SHIFT) 168 169 /* 0x1C : dvp_status_and_error */ 170 #define CAM_STS_NORMAL_INT (1<<0U) 171 #define CAM_STS_NORMAL_INT_1 (1<<1U) 172 #define CAM_STS_MEM_INT (1<<2U) 173 #define CAM_STS_MEM_INT_1 (1<<3U) 174 #define CAM_STS_FRAME_INT (1<<4U) 175 #define CAM_STS_FRAME_INT_1 (1<<5U) 176 #define CAM_STS_FIFO_INT (1<<6U) 177 #define CAM_STS_FIFO_INT_1 (1<<7U) 178 #define CAM_STS_HCNT_INT (1<<8U) 179 #define CAM_STS_VCNT_INT (1<<9U) 180 #define CAM_AHB_IDLE_0 (1<<16U) 181 #define CAM_AHB_IDLE_1 (1<<17U) 182 #define CAM_ST_DVP_IDLE (1<<19U) 183 #define CAM_FRAME_VALID_CNT_SHIFT (20U) 184 #define CAM_FRAME_VALID_CNT_MASK (0xf<<CAM_FRAME_VALID_CNT_SHIFT) 185 #define CAM_FRAME_VALID_CNT_1_SHIFT (24U) 186 #define CAM_FRAME_VALID_CNT_1_MASK (0xf<<CAM_FRAME_VALID_CNT_1_SHIFT) 187 #define CAM_ST_BUS_IDLE (1<<28U) 188 #define CAM_ST_BUS_FUNC (1<<29U) 189 #define CAM_ST_BUS_WAIT (1<<30U) 190 #define CAM_ST_BUS_FLSH (1<<31U) 191 #else 192 /* 0xC : dvp_status_and_error */ 193 #define CAM_REG_FRAME_CNT_TRGR_INT_SHIFT (0U) 194 #define CAM_REG_FRAME_CNT_TRGR_INT_MASK (0x1f<<CAM_REG_FRAME_CNT_TRGR_INT_SHIFT) 195 #define CAM_REG_INT_HCNT_EN (1<<6U) 196 #define CAM_REG_INT_VCNT_EN (1<<7U) 197 #define CAM_REG_INT_NORMAL_EN (1<<8U) 198 #define CAM_REG_INT_MEM_EN (1<<9U) 199 #define CAM_REG_INT_FRAME_EN (1<<10U) 200 #define CAM_REG_INT_FIFO_EN (1<<11U) 201 #define CAM_STS_NORMAL_INT (1<<12U) 202 #define CAM_STS_MEM_INT (1<<13U) 203 #define CAM_STS_FRAME_INT (1<<14U) 204 #define CAM_STS_FIFO_INT (1<<15U) 205 #define CAM_FRAME_VALID_CNT_SHIFT (16U) 206 #define CAM_FRAME_VALID_CNT_MASK (0x1f<<CAM_FRAME_VALID_CNT_SHIFT) 207 #define CAM_STS_HCNT_INT (1<<21U) 208 #define CAM_STS_VCNT_INT (1<<22U) 209 #define CAM_ST_BUS_IDLE (1<<24U) 210 #define CAM_ST_BUS_FUNC (1<<25U) 211 #define CAM_ST_BUS_WAIT (1<<26U) 212 #define CAM_ST_BUS_FLSH (1<<27U) 213 #define CAM_AXI_IDLE (1<<28U) 214 #define CAM_ST_DVP_IDLE (1<<29U) 215 216 /* 0x10 : dvp2axi_frame_bcnt */ 217 #define CAM_REG_FRAME_BYTE_CNT_SHIFT (0U) 218 #define CAM_REG_FRAME_BYTE_CNT_MASK (0xffffffff<<CAM_REG_FRAME_BYTE_CNT_SHIFT) 219 #endif 220 221 /* 0x14 : dvp_frame_fifo_pop */ 222 #define CAM_RFIFO_POP (1<<0U) 223 #if defined(BL702) 224 #define CAM_RFIFO_POP_1 (1<<1U) 225 #endif 226 #define CAM_REG_INT_NORMAL_CLR (1<<4U) 227 #define CAM_REG_INT_MEM_CLR (1<<5U) 228 #define CAM_REG_INT_FRAME_CLR (1<<6U) 229 #define CAM_REG_INT_FIFO_CLR (1<<7U) 230 #define CAM_REG_INT_HCNT_CLR (1<<8U) 231 #define CAM_REG_INT_VCNT_CLR (1<<9U) 232 #if defined(BL702) 233 #define CAM_REG_INT_NORMAL_CLR_1 (1<<16U) 234 #define CAM_REG_INT_MEM_CLR_1 (1<<17U) 235 #define CAM_REG_INT_FRAME_CLR_1 (1<<18U) 236 #define CAM_REG_INT_FIFO_CLR_1 (1<<19U) 237 #endif 238 239 #if defined(BL702) 240 /* 0x24 : snsr_control */ 241 #define CAM_REG_CAM_RST (1<<0U) 242 #define CAM_REG_CAM_PWDN (1<<1U) 243 244 /* 0x28 : int_control */ 245 #define CAM_REG_INT_NORMAL_EN (1<<0U) 246 #define CAM_REG_INT_NORMAL_1_EN (1<<1U) 247 #define CAM_REG_INT_MEM_EN (1<<2U) 248 #define CAM_REG_INT_FRAME_EN (1<<3U) 249 #define CAM_REG_INT_FIFO_EN (1<<4U) 250 #define CAM_REG_INT_HCNT_EN (1<<5U) 251 #define CAM_REG_INT_VCNT_EN (1<<6U) 252 #define CAM_REG_FRAME_CNT_TRGR_INT_SHIFT (28U) 253 #define CAM_REG_FRAME_CNT_TRGR_INT_MASK (0xf<<CAM_REG_FRAME_CNT_TRGR_INT_SHIFT) 254 #else 255 /* 0x18 : dvp2axi_frame_vld */ 256 #define CAM_REG_FRAME_N_VLD_SHIFT (0U) 257 #define CAM_REG_FRAME_N_VLD_MASK (0xffffffff<<CAM_REG_FRAME_N_VLD_SHIFT) 258 259 /* 0x1C : dvp2axi_frame_period */ 260 #define CAM_REG_FRAME_PERIOD_SHIFT (0U) 261 #define CAM_REG_FRAME_PERIOD_MASK (0x1f<<CAM_REG_FRAME_PERIOD_SHIFT) 262 263 /* 0x20 : dvp2axi_misc */ 264 #define CAM_REG_ALPHA_SHIFT (0U) 265 #define CAM_REG_ALPHA_MASK (0xff<<CAM_REG_ALPHA_SHIFT) 266 #define CAM_REG_FORMAT_565_SHIFT (8U) 267 #define CAM_REG_FORMAT_565_MASK (0x7<<CAM_REG_FORMAT_565_SHIFT) 268 #endif 269 270 /* 0x30 : dvp2axi_hsync_crop */ 271 #define CAM_REG_HSYNC_ACT_END_SHIFT (0U) 272 #define CAM_REG_HSYNC_ACT_END_MASK (0xffff<<CAM_REG_HSYNC_ACT_END_SHIFT) 273 #define CAM_REG_HSYNC_ACT_START_SHIFT (16U) 274 #define CAM_REG_HSYNC_ACT_START_MASK (0xffff<<CAM_REG_HSYNC_ACT_START_SHIFT) 275 276 /* 0x34 : dvp2axi_vsync_crop */ 277 #define CAM_REG_VSYNC_ACT_END_SHIFT (0U) 278 #define CAM_REG_VSYNC_ACT_END_MASK (0xffff<<CAM_REG_VSYNC_ACT_END_SHIFT) 279 #define CAM_REG_VSYNC_ACT_START_SHIFT (16U) 280 #define CAM_REG_VSYNC_ACT_START_MASK (0xffff<<CAM_REG_VSYNC_ACT_START_SHIFT) 281 282 /* 0x38 : dvp2axi_fram_exm */ 283 #define CAM_REG_TOTAL_HCNT_SHIFT (0U) 284 #define CAM_REG_TOTAL_HCNT_MASK (0xffff<<CAM_REG_TOTAL_HCNT_SHIFT) 285 #define CAM_REG_TOTAL_VCNT_SHIFT (16U) 286 #define CAM_REG_TOTAL_VCNT_MASK (0xffff<<CAM_REG_TOTAL_VCNT_SHIFT) 287 288 /* 0x40 : frame_start_addr0 */ 289 #define CAM_FRAME_START_ADDR_0_SHIFT (0U) 290 #define CAM_FRAME_START_ADDR_0_MASK (0xffffffff<<CAM_FRAME_START_ADDR_0_SHIFT) 291 292 #if defined(BL702) 293 /* 0x44 : frame_byte_cnt0_0 */ 294 #define CAM_FRAME_BYTE_CNT_0_0_SHIFT (0U) 295 #define CAM_FRAME_BYTE_CNT_0_0_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_0_SHIFT) 296 #endif 297 298 /* 0x48 : frame_start_addr1 */ 299 #define CAM_FRAME_START_ADDR_1_SHIFT (0U) 300 #define CAM_FRAME_START_ADDR_1_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_SHIFT) 301 302 #if defined(BL702) 303 /* 0x4C : frame_byte_cnt0_1 */ 304 #define CAM_FRAME_BYTE_CNT_0_1_SHIFT (0U) 305 #define CAM_FRAME_BYTE_CNT_0_1_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_1_SHIFT) 306 #endif 307 308 /* 0x50 : frame_start_addr2 */ 309 #define CAM_FRAME_START_ADDR_2_SHIFT (0U) 310 #define CAM_FRAME_START_ADDR_2_MASK (0xffffffff<<CAM_FRAME_START_ADDR_2_SHIFT) 311 312 #if defined(BL702) 313 /* 0x54 : frame_byte_cnt0_2 */ 314 #define CAM_FRAME_BYTE_CNT_0_2_SHIFT (0U) 315 #define CAM_FRAME_BYTE_CNT_0_2_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_2_SHIFT) 316 #endif 317 318 /* 0x58 : frame_start_addr3 */ 319 #define CAM_FRAME_START_ADDR_3_SHIFT (0U) 320 #define CAM_FRAME_START_ADDR_3_MASK (0xffffffff<<CAM_FRAME_START_ADDR_3_SHIFT) 321 322 #if defined(BL702) 323 /* 0x5C : frame_byte_cnt0_3 */ 324 #define CAM_FRAME_BYTE_CNT_0_3_SHIFT (0U) 325 #define CAM_FRAME_BYTE_CNT_0_3_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_3_SHIFT) 326 327 /* 0x60 : frame_start_addr0_4 */ 328 #define CAM_FRAME_START_ADDR_0_4_SHIFT (0U) 329 #define CAM_FRAME_START_ADDR_0_4_MASK (0xffffffff<<CAM_FRAME_START_ADDR_0_4_SHIFT) 330 331 /* 0x64 : frame_byte_cnt0_4 */ 332 #define CAM_FRAME_BYTE_CNT_0_4_SHIFT (0U) 333 #define CAM_FRAME_BYTE_CNT_0_4_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_4_SHIFT) 334 335 /* 0x68 : frame_start_addr0_5 */ 336 #define CAM_FRAME_START_ADDR_0_5_SHIFT (0U) 337 #define CAM_FRAME_START_ADDR_0_5_MASK (0xffffffff<<CAM_FRAME_START_ADDR_0_5_SHIFT) 338 339 /* 0x6C : frame_byte_cnt0_5 */ 340 #define CAM_FRAME_BYTE_CNT_0_5_SHIFT (0U) 341 #define CAM_FRAME_BYTE_CNT_0_5_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_5_SHIFT) 342 343 /* 0x70 : frame_start_addr0_6 */ 344 #define CAM_FRAME_START_ADDR_0_6_SHIFT (0U) 345 #define CAM_FRAME_START_ADDR_0_6_MASK (0xffffffff<<CAM_FRAME_START_ADDR_0_6_SHIFT) 346 347 /* 0x74 : frame_byte_cnt0_6 */ 348 #define CAM_FRAME_BYTE_CNT_0_6_SHIFT (0U) 349 #define CAM_FRAME_BYTE_CNT_0_6_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_6_SHIFT) 350 351 /* 0x78 : frame_start_addr0_7 */ 352 #define CAM_FRAME_START_ADDR_0_7_SHIFT (0U) 353 #define CAM_FRAME_START_ADDR_0_7_MASK (0xffffffff<<CAM_FRAME_START_ADDR_0_7_SHIFT) 354 355 /* 0x7C : frame_byte_cnt0_7 */ 356 #define CAM_FRAME_BYTE_CNT_0_7_SHIFT (0U) 357 #define CAM_FRAME_BYTE_CNT_0_7_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_7_SHIFT) 358 359 /* 0x80 : frame_start_addr1_0 */ 360 #define CAM_FRAME_START_ADDR_1_0_SHIFT (0U) 361 #define CAM_FRAME_START_ADDR_1_0_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_0_SHIFT) 362 363 /* 0x84 : frame_byte_cnt1_0 */ 364 #define CAM_FRAME_BYTE_CNT_1_0_SHIFT (0U) 365 #define CAM_FRAME_BYTE_CNT_1_0_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_0_SHIFT) 366 367 /* 0x88 : frame_start_addr1_1 */ 368 #define CAM_FRAME_START_ADDR_1_1_SHIFT (0U) 369 #define CAM_FRAME_START_ADDR_1_1_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_1_SHIFT) 370 371 /* 0x8C : frame_byte_cnt1_1 */ 372 #define CAM_FRAME_BYTE_CNT_1_1_SHIFT (0U) 373 #define CAM_FRAME_BYTE_CNT_1_1_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_1_SHIFT) 374 375 /* 0x90 : frame_start_addr1_2 */ 376 #define CAM_FRAME_START_ADDR_1_2_SHIFT (0U) 377 #define CAM_FRAME_START_ADDR_1_2_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_2_SHIFT) 378 379 /* 0x94 : frame_byte_cnt1_2 */ 380 #define CAM_FRAME_BYTE_CNT_1_2_SHIFT (0U) 381 #define CAM_FRAME_BYTE_CNT_1_2_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_2_SHIFT) 382 383 /* 0x98 : frame_start_addr1_3 */ 384 #define CAM_FRAME_START_ADDR_1_3_SHIFT (0U) 385 #define CAM_FRAME_START_ADDR_1_3_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_3_SHIFT) 386 387 /* 0x9C : frame_byte_cnt1_3 */ 388 #define CAM_FRAME_BYTE_CNT_1_3_SHIFT (0U) 389 #define CAM_FRAME_BYTE_CNT_1_3_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_3_SHIFT) 390 391 /* 0xA0 : frame_start_addr1_4 */ 392 #define CAM_FRAME_START_ADDR_1_4_SHIFT (0U) 393 #define CAM_FRAME_START_ADDR_1_4_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_4_SHIFT) 394 395 /* 0xA4 : frame_byte_cnt1_4 */ 396 #define CAM_FRAME_BYTE_CNT_1_4_SHIFT (0U) 397 #define CAM_FRAME_BYTE_CNT_1_4_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_4_SHIFT) 398 399 /* 0xA8 : frame_start_addr1_5 */ 400 #define CAM_FRAME_START_ADDR_1_5_SHIFT (0U) 401 #define CAM_FRAME_START_ADDR_1_5_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_5_SHIFT) 402 403 /* 0xAC : frame_byte_cnt1_5 */ 404 #define CAM_FRAME_BYTE_CNT_1_5_SHIFT (0U) 405 #define CAM_FRAME_BYTE_CNT_1_5_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_5_SHIFT) 406 407 /* 0xB0 : frame_start_addr1_6 */ 408 #define CAM_FRAME_START_ADDR_1_6_SHIFT (0U) 409 #define CAM_FRAME_START_ADDR_1_6_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_6_SHIFT) 410 411 /* 0xB4 : frame_byte_cnt1_6 */ 412 #define CAM_FRAME_BYTE_CNT_1_6_SHIFT (0U) 413 #define CAM_FRAME_BYTE_CNT_1_6_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_6_SHIFT) 414 415 /* 0xB8 : frame_start_addr1_7 */ 416 #define CAM_FRAME_START_ADDR_1_7_SHIFT (0U) 417 #define CAM_FRAME_START_ADDR_1_7_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_7_SHIFT) 418 419 /* 0xBC : frame_byte_cnt1_7 */ 420 #define CAM_FRAME_BYTE_CNT_1_7_SHIFT (0U) 421 #define CAM_FRAME_BYTE_CNT_1_7_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_7_SHIFT) 422 #else 423 424 /* 0x60 : frame_id_sts01 */ 425 #define CAM_FRAME_ID_0_SHIFT (0U) 426 #define CAM_FRAME_ID_0_MASK (0xffff<<CAM_FRAME_ID_0_SHIFT) 427 #define CAM_FRAME_ID_1_SHIFT (16U) 428 #define CAM_FRAME_ID_1_MASK (0xffff<<CAM_FRAME_ID_1_SHIFT) 429 430 /* 0x64 : frame_id_sts23 */ 431 #define CAM_FRAME_ID_2_SHIFT (0U) 432 #define CAM_FRAME_ID_2_MASK (0xffff<<CAM_FRAME_ID_2_SHIFT) 433 #define CAM_FRAME_ID_3_SHIFT (16U) 434 #define CAM_FRAME_ID_3_MASK (0xffff<<CAM_FRAME_ID_3_SHIFT) 435 #endif 436 437 /* 0xF0 : dvp_debug */ 438 #define CAM_REG_DVP_DBG_EN (1<<0U) 439 #define CAM_REG_DVP_DBG_SEL_SHIFT (1U) 440 #define CAM_REG_DVP_DBG_SEL_MASK (0x7<<CAM_REG_DVP_DBG_SEL_SHIFT) 441 #if !defined(BL702) 442 #define CAM_REG_ID_LATCH_LINE_SHIFT (8U) 443 #define CAM_REG_ID_LATCH_LINE_MASK (0xf<<CAM_REG_ID_LATCH_LINE_SHIFT) 444 #endif 445 446 /* 0xFC : dvp_dummy_reg */ 447 448 449 #endif /* __HARDWARE_CAM_H__ */ 450