1 /** 2 ****************************************************************************** 3 * @file dbi_reg.h 4 * @version V1.0 5 * @date 2023-02-08 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __DBI_REG_H__ 37 #define __DBI_REG_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define DBI_CONFIG_OFFSET (0x0) /* dbi_config */ 46 #define DBI_QSPI_CONFIG_OFFSET (0x4) /* qspi_config */ 47 #define DBI_PIX_CNT_OFFSET (0x8) /* dbi_pix_cnt */ 48 #define DBI_PRD_OFFSET (0xC) /* dbi_prd */ 49 #define DBI_CMD_OFFSET (0x10) /* dbi_cmd */ 50 #define DBI_QSPI_ADR_OFFSET (0x14) /* dbi_qspi_adr */ 51 #define DBI_RDATA_0_OFFSET (0x18) /* dbi_rdata_0 */ 52 #define DBI_RDATA_1_OFFSET (0x1C) /* dbi_rdata_1 */ 53 #define DBI_INT_STS_OFFSET (0x30) /* dbi_int_sts */ 54 #define DBI_YUV_RGB_CONFIG_0_OFFSET (0x60) /* dbi_yuv_rgb_config_0 */ 55 #define DBI_YUV_RGB_CONFIG_1_OFFSET (0x64) /* dbi_yuv_rgb_config_1 */ 56 #define DBI_YUV_RGB_CONFIG_2_OFFSET (0x68) /* dbi_yuv_rgb_config_2 */ 57 #define DBI_YUV_RGB_CONFIG_3_OFFSET (0x6C) /* dbi_yuv_rgb_config_3 */ 58 #define DBI_YUV_RGB_CONFIG_4_OFFSET (0x70) /* dbi_yuv_rgb_config_4 */ 59 #define DBI_YUV_RGB_CONFIG_5_OFFSET (0x74) /* dbi_yuv_rgb_config_5 */ 60 #define DBI_FIFO_CONFIG_0_OFFSET (0x80) /* dbi_fifo_config_0 */ 61 #define DBI_FIFO_CONFIG_1_OFFSET (0x84) /* dbi_fifo_config_1 */ 62 #define DBI_FIFO_WDATA_OFFSET (0x88) /* dbi_fifo_wdata */ 63 64 /* Register Bitfield definitions *****************************************************/ 65 66 /* 0x0 : dbi_config */ 67 #define DBI_CR_DBI_EN (1 << 0U) 68 #define DBI_CR_DBI_SEL_SHIFT (1U) 69 #define DBI_CR_DBI_SEL_MASK (0x3 << DBI_CR_DBI_SEL_SHIFT) 70 #define DBI_CR_DBI_CMD_EN (1 << 4U) 71 #define DBI_CR_DBI_DAT_EN (1 << 5U) 72 #define DBI_CR_DBI_DAT_WR (1 << 6U) 73 #define DBI_CR_DBI_DAT_TP (1 << 7U) 74 #define DBI_CR_DBI_DAT_BC_SHIFT (8U) 75 #define DBI_CR_DBI_DAT_BC_MASK (0xff << DBI_CR_DBI_DAT_BC_SHIFT) 76 #define DBI_CR_DBI_SCL_POL (1 << 16U) 77 #define DBI_CR_DBI_SCL_PH (1 << 17U) 78 #define DBI_CR_DBI_CONT_EN (1 << 18U) 79 #define DBI_CR_DBI_DMY_EN (1 << 19U) 80 #define DBI_CR_DBI_DMY_CNT_SHIFT (20U) 81 #define DBI_CR_DBI_DMY_CNT_MASK (0xf << DBI_CR_DBI_DMY_CNT_SHIFT) 82 #define DBI_CR_DBI_CS_STRETCH (1 << 24U) 83 #define DBI_STS_DBI_BUS_BUSY (1 << 31U) 84 85 /* 0x4 : qspi_config */ 86 #define DBI_CR_QSPI_CMD_4B (1 << 0U) 87 #define DBI_CR_QSPI_ADR_4B (1 << 1U) 88 #define DBI_CR_QSPI_DAT_4B (1 << 2U) 89 #define DBI_CR_QSPI_ADR_BC_SHIFT (4U) 90 #define DBI_CR_QSPI_ADR_BC_MASK (0x3 << DBI_CR_QSPI_ADR_BC_SHIFT) 91 92 /* 0x8 : dbi_pix_cnt */ 93 #define DBI_CR_DBI_PIX_CNT_SHIFT (0U) 94 #define DBI_CR_DBI_PIX_CNT_MASK (0xffffff << DBI_CR_DBI_PIX_CNT_SHIFT) 95 #define DBI_CR_DBI_PIX_FORMAT (1 << 31U) 96 97 /* 0xC : dbi_prd */ 98 #define DBI_CR_DBI_PRD_S_SHIFT (0U) 99 #define DBI_CR_DBI_PRD_S_MASK (0xff << DBI_CR_DBI_PRD_S_SHIFT) 100 #define DBI_CR_DBI_PRD_I_SHIFT (8U) 101 #define DBI_CR_DBI_PRD_I_MASK (0xff << DBI_CR_DBI_PRD_I_SHIFT) 102 #define DBI_CR_DBI_PRD_D_PH_0_SHIFT (16U) 103 #define DBI_CR_DBI_PRD_D_PH_0_MASK (0xff << DBI_CR_DBI_PRD_D_PH_0_SHIFT) 104 #define DBI_CR_DBI_PRD_D_PH_1_SHIFT (24U) 105 #define DBI_CR_DBI_PRD_D_PH_1_MASK (0xff << DBI_CR_DBI_PRD_D_PH_1_SHIFT) 106 107 /* 0x10 : dbi_cmd */ 108 #define DBI_CR_DBI_CMD_SHIFT (0U) 109 #define DBI_CR_DBI_CMD_MASK (0xff << DBI_CR_DBI_CMD_SHIFT) 110 111 /* 0x14 : dbi_qspi_adr */ 112 #define DBI_CR_QSPI_ADR_SHIFT (0U) 113 #define DBI_CR_QSPI_ADR_MASK (0xffffffff << DBI_CR_QSPI_ADR_SHIFT) 114 115 /* 0x18 : dbi_rdata_0 */ 116 #define DBI_STS_DBI_RDATA_0_SHIFT (0U) 117 #define DBI_STS_DBI_RDATA_0_MASK (0xffffffff << DBI_STS_DBI_RDATA_0_SHIFT) 118 119 /* 0x1C : dbi_rdata_1 */ 120 #define DBI_STS_DBI_RDATA_1_SHIFT (0U) 121 #define DBI_STS_DBI_RDATA_1_MASK (0xffffffff << DBI_STS_DBI_RDATA_1_SHIFT) 122 123 /* 0x30 : dbi_int_sts */ 124 #define DBI_END_INT (1 << 0U) 125 #define DBI_TXF_INT (1 << 1U) 126 #define DBI_FER_INT (1 << 2U) 127 #define DBI_CR_DBI_END_MASK (1 << 8U) 128 #define DBI_CR_DBI_TXF_MASK (1 << 9U) 129 #define DBI_CR_DBI_FER_MASK (1 << 10U) 130 #define DBI_CR_DBI_END_CLR (1 << 16U) 131 #define DBI_CR_DBI_END_EN (1 << 24U) 132 #define DBI_CR_DBI_TXF_EN (1 << 25U) 133 #define DBI_CR_DBI_FER_EN (1 << 26U) 134 135 /* 0x60 : dbi_yuv_rgb_config_0 */ 136 #define DBI_CR_Y2R_PRE_0_SHIFT (0U) 137 #define DBI_CR_Y2R_PRE_0_MASK (0x1ff << DBI_CR_Y2R_PRE_0_SHIFT) 138 #define DBI_CR_Y2R_PRE_1_SHIFT (10U) 139 #define DBI_CR_Y2R_PRE_1_MASK (0x1ff << DBI_CR_Y2R_PRE_1_SHIFT) 140 #define DBI_CR_Y2R_PRE_2_SHIFT (20U) 141 #define DBI_CR_Y2R_PRE_2_MASK (0x1ff << DBI_CR_Y2R_PRE_2_SHIFT) 142 #define DBI_CR_Y2R_EN (1 << 31U) 143 144 /* 0x64 : dbi_yuv_rgb_config_1 */ 145 #define DBI_CR_Y2R_POS_0_SHIFT (0U) 146 #define DBI_CR_Y2R_POS_0_MASK (0x1ff << DBI_CR_Y2R_POS_0_SHIFT) 147 #define DBI_CR_Y2R_POS_1_SHIFT (10U) 148 #define DBI_CR_Y2R_POS_1_MASK (0x1ff << DBI_CR_Y2R_POS_1_SHIFT) 149 #define DBI_CR_Y2R_POS_2_SHIFT (20U) 150 #define DBI_CR_Y2R_POS_2_MASK (0x1ff << DBI_CR_Y2R_POS_2_SHIFT) 151 152 /* 0x68 : dbi_yuv_rgb_config_2 */ 153 #define DBI_CR_Y2R_MTX_00_SHIFT (0U) 154 #define DBI_CR_Y2R_MTX_00_MASK (0xfff << DBI_CR_Y2R_MTX_00_SHIFT) 155 #define DBI_CR_Y2R_MTX_01_SHIFT (12U) 156 #define DBI_CR_Y2R_MTX_01_MASK (0xfff << DBI_CR_Y2R_MTX_01_SHIFT) 157 #define DBI_CR_Y2R_MTX_02_L_SHIFT (24U) 158 #define DBI_CR_Y2R_MTX_02_L_MASK (0xff << DBI_CR_Y2R_MTX_02_L_SHIFT) 159 160 /* 0x6C : dbi_yuv_rgb_config_3 */ 161 #define DBI_CR_Y2R_MTX_02_U_SHIFT (0U) 162 #define DBI_CR_Y2R_MTX_02_U_MASK (0xf << DBI_CR_Y2R_MTX_02_U_SHIFT) 163 #define DBI_CR_Y2R_MTX_10_SHIFT (4U) 164 #define DBI_CR_Y2R_MTX_10_MASK (0xfff << DBI_CR_Y2R_MTX_10_SHIFT) 165 #define DBI_CR_Y2R_MTX_11_SHIFT (16U) 166 #define DBI_CR_Y2R_MTX_11_MASK (0xfff << DBI_CR_Y2R_MTX_11_SHIFT) 167 #define DBI_CR_Y2R_MTX_12_L_SHIFT (28U) 168 #define DBI_CR_Y2R_MTX_12_L_MASK (0xf << DBI_CR_Y2R_MTX_12_L_SHIFT) 169 170 /* 0x70 : dbi_yuv_rgb_config_4 */ 171 #define DBI_CR_Y2R_MTX_12_U_SHIFT (0U) 172 #define DBI_CR_Y2R_MTX_12_U_MASK (0xff << DBI_CR_Y2R_MTX_12_U_SHIFT) 173 #define DBI_CR_Y2R_MTX_20_SHIFT (8U) 174 #define DBI_CR_Y2R_MTX_20_MASK (0xfff << DBI_CR_Y2R_MTX_20_SHIFT) 175 #define DBI_CR_Y2R_MTX_21_SHIFT (20U) 176 #define DBI_CR_Y2R_MTX_21_MASK (0xfff << DBI_CR_Y2R_MTX_21_SHIFT) 177 178 /* 0x74 : dbi_yuv_rgb_config_5 */ 179 #define DBI_CR_Y2R_MTX_22_SHIFT (0U) 180 #define DBI_CR_Y2R_MTX_22_MASK (0xfff << DBI_CR_Y2R_MTX_22_SHIFT) 181 182 /* 0x80 : dbi_fifo_config_0 */ 183 #define DBI_DMA_TX_EN (1 << 0U) 184 #define DBI_TX_FIFO_CLR (1 << 2U) 185 #define DBI_TX_FIFO_OVERFLOW (1 << 4U) 186 #define DBI_TX_FIFO_UNDERFLOW (1 << 5U) 187 #define DBI_FIFO_YUV_MODE (1 << 28U) 188 #define DBI_FIFO_FORMAT_SHIFT (29U) 189 #define DBI_FIFO_FORMAT_MASK (0x7 << DBI_FIFO_FORMAT_SHIFT) 190 191 /* 0x84 : dbi_fifo_config_1 */ 192 #define DBI_TX_FIFO_CNT_SHIFT (0U) 193 #define DBI_TX_FIFO_CNT_MASK (0xf << DBI_TX_FIFO_CNT_SHIFT) 194 #define DBI_TX_FIFO_TH_SHIFT (16U) 195 #define DBI_TX_FIFO_TH_MASK (0x7 << DBI_TX_FIFO_TH_SHIFT) 196 197 /* 0x88 : dbi_fifo_wdata */ 198 #define DBI_FIFO_WDATA_SHIFT (0U) 199 #define DBI_FIFO_WDATA_MASK (0xffffffff << DBI_FIFO_WDATA_SHIFT) 200 201 #endif /* __DBI_REG_H__ */ 202