1 /** 2 ****************************************************************************** 3 * @file dtsrc_reg.h 4 * @version V1.0 5 * @date 2022-12-15 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_DTSRC_H__ 37 #define __HARDWARE_DTSRC_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define DTSRC_CONFIG_OFFSET (0x0)/* config */ 46 #define DTSRC_FRAME_SIZE_H_OFFSET (0x4)/* frame_size_h */ 47 #define DTSRC_FRAME_SIZE_V_OFFSET (0x8)/* frame_size_v */ 48 #define DTSRC_FRAME_SIZE_CEA_861_OFFSET (0xC)/* frame_size_cea_861 */ 49 #define DTSRC_PIX_DATA_RANGE_OFFSET (0x10)/* pix_data_range */ 50 #define DTSRC_PIX_DATA_STEP_OFFSET (0x14)/* pix_data_step */ 51 #define DTSRC_AXI2DVP_SETTING_OFFSET (0x20)/* axi2dvp_setting */ 52 #define DTSRC_AXI2DVP_START_ADDR_BY_OFFSET (0x24)/* axi2dvp_start_addr_by */ 53 #define DTSRC_AXI2DVP_BURST_CNT_OFFSET (0x28)/* axi2dvp_burst_cnt */ 54 #define DTSRC_AXI2DVP_STATUS_OFFSET (0x2C)/* axi2dvp_status */ 55 #define DTSRC_AXI2DVP_SWAP_ADDR_BY_OFFSET (0x30)/* axi2dvp_swap_addr_by */ 56 #define DTSRC_AXI2DVP_PREFETCH_OFFSET (0x34)/* axi2dvp_prefetch */ 57 #define DTSRC_SNSR2DVP_WAIT_POS_OFFSET (0x38)/* snsr2dvp_wait_pos */ 58 #define DTSRC_AXI2DVP_START_ADDR_UV_OFFSET (0x40)/* axi2dvp_start_addr_uv */ 59 #define DTSRC_AXI2DVP_SWAP_ADDR_UV_OFFSET (0x44)/* axi2dvp_swap_addr_uv */ 60 61 /* Register Bitfield definitions *****************************************************/ 62 63 /* 0x0 : config */ 64 #define DTSRC_CR_ENABLE (1<<0U) 65 #define DTSRC_CR_AXI_EN (1<<1U) 66 #define DTSRC_CR_MODE_CEA_861 (1<<2U) 67 #define DTSRC_CR_SNSR_EN (1<<3U) 68 #define DTSRC_CR_SNSR_HSYNC_INV (1<<4U) 69 #define DTSRC_CR_SNSR_VSYNC_INV (1<<5U) 70 #define DTSRC_CR_AXI_SWAP_MODE (1<<7U) 71 #define DTSRC_CR_AXI_SWAP_IDX_SEL_SHIFT (8U) 72 #define DTSRC_CR_AXI_SWAP_IDX_SEL_MASK (0xf<<DTSRC_CR_AXI_SWAP_IDX_SEL_SHIFT) 73 #define DTSRC_CR_AXI_SWAP_IDX_SWM (1<<12U) 74 #define DTSRC_CR_AXI_SWAP_IDX_SWV (1<<13U) 75 #define DTSRC_CR_AXI_DVP_DATA_MODE_SHIFT (16U) 76 #define DTSRC_CR_AXI_DVP_DATA_MODE_MASK (0x7<<DTSRC_CR_AXI_DVP_DATA_MODE_SHIFT) 77 #define DTSRC_CR_AXI_B0_SEL_SHIFT (20U) 78 #define DTSRC_CR_AXI_B0_SEL_MASK (0x3<<DTSRC_CR_AXI_B0_SEL_SHIFT) 79 #define DTSRC_CR_AXI_B1_SEL_SHIFT (22U) 80 #define DTSRC_CR_AXI_B1_SEL_MASK (0x3<<DTSRC_CR_AXI_B1_SEL_SHIFT) 81 #define DTSRC_CR_AXI_B2_SEL_SHIFT (24U) 82 #define DTSRC_CR_AXI_B2_SEL_MASK (0x3<<DTSRC_CR_AXI_B2_SEL_SHIFT) 83 84 /* 0x4 : frame_size_h */ 85 #define DTSRC_CR_TOTAL_H_SHIFT (0U) 86 #define DTSRC_CR_TOTAL_H_MASK (0xfff<<DTSRC_CR_TOTAL_H_SHIFT) 87 #define DTSRC_CR_BLANK_H_SHIFT (16U) 88 #define DTSRC_CR_BLANK_H_MASK (0xfff<<DTSRC_CR_BLANK_H_SHIFT) 89 90 /* 0x8 : frame_size_v */ 91 #define DTSRC_CR_TOTAL_V_SHIFT (0U) 92 #define DTSRC_CR_TOTAL_V_MASK (0xfff<<DTSRC_CR_TOTAL_V_SHIFT) 93 #define DTSRC_CR_BLANK_V_SHIFT (16U) 94 #define DTSRC_CR_BLANK_V_MASK (0xfff<<DTSRC_CR_BLANK_V_SHIFT) 95 96 /* 0xC : frame_size_cea_861 */ 97 #define DTSRC_CR_H_DURATION_SHIFT (0U) 98 #define DTSRC_CR_H_DURATION_MASK (0xff<<DTSRC_CR_H_DURATION_SHIFT) 99 #define DTSRC_CR_H_PLACEMENT_SHIFT (8U) 100 #define DTSRC_CR_H_PLACEMENT_MASK (0xff<<DTSRC_CR_H_PLACEMENT_SHIFT) 101 #define DTSRC_CR_V_DURATION_SHIFT (16U) 102 #define DTSRC_CR_V_DURATION_MASK (0xff<<DTSRC_CR_V_DURATION_SHIFT) 103 #define DTSRC_CR_V_PLACEMENT_SHIFT (24U) 104 #define DTSRC_CR_V_PLACEMENT_MASK (0xff<<DTSRC_CR_V_PLACEMENT_SHIFT) 105 106 /* 0x10 : pix_data_range */ 107 #define DTSRC_CR_DATA_MIN_SHIFT (0U) 108 #define DTSRC_CR_DATA_MIN_MASK (0xffff<<DTSRC_CR_DATA_MIN_SHIFT) 109 #define DTSRC_CR_DATA_MAX_SHIFT (16U) 110 #define DTSRC_CR_DATA_MAX_MASK (0xffff<<DTSRC_CR_DATA_MAX_SHIFT) 111 112 /* 0x14 : pix_data_step */ 113 #define DTSRC_CR_DATA_STEP_SHIFT (0U) 114 #define DTSRC_CR_DATA_STEP_MASK (0xff<<DTSRC_CR_DATA_STEP_SHIFT) 115 116 /* 0x20 : axi2dvp_setting */ 117 #define DTSRC_CR_AXI_XLEN_SHIFT (0U) 118 #define DTSRC_CR_AXI_XLEN_MASK (0x7<<DTSRC_CR_AXI_XLEN_SHIFT) 119 #define DTSRC_CR_AXI_DRAIN_ERR_CLR (1<<4U) 120 #define DTSRC_CR_AXI_420_MODE (1<<8U) 121 #define DTSRC_CR_AXI_420_UD_SEL (1<<9U) 122 #define DTSRC_CR_QOS_SW_MODE (1<<10U) 123 #define DTSRC_CR_QOS_SW (1<<11U) 124 125 /* 0x24 : axi2dvp_start_addr_by */ 126 #define DTSRC_CR_AXI_ADDR_START_BY_SHIFT (0U) 127 #define DTSRC_CR_AXI_ADDR_START_BY_MASK (0xffffffff<<DTSRC_CR_AXI_ADDR_START_BY_SHIFT) 128 129 /* 0x28 : axi2dvp_burst_cnt */ 130 #define DTSRC_CR_AXI_FRAME_BC_SHIFT (0U) 131 #define DTSRC_CR_AXI_FRAME_BC_MASK (0xffffffff<<DTSRC_CR_AXI_FRAME_BC_SHIFT) 132 133 /* 0x2C : axi2dvp_status */ 134 #define DTSRC_ST_AXI_FIFO_CNT_BY_SHIFT (0U) 135 #define DTSRC_ST_AXI_FIFO_CNT_BY_MASK (0x7f<<DTSRC_ST_AXI_FIFO_CNT_BY_SHIFT) 136 #define DTSRC_ST_AXI_DRAIN_ERROR_BY (1<<7U) 137 #define DTSRC_ST_AXI_STATE_IDLE_BY (1<<8U) 138 #define DTSRC_ST_AXI_STATE_FUNC_BY (1<<9U) 139 #define DTSRC_ST_AXI_STATE_FLSH_BY (1<<10U) 140 #define DTSRC_ST_AXI_FIFO_CNT_UV_SHIFT (16U) 141 #define DTSRC_ST_AXI_FIFO_CNT_UV_MASK (0x7f<<DTSRC_ST_AXI_FIFO_CNT_UV_SHIFT) 142 #define DTSRC_ST_AXI_DRAIN_ERROR_UV (1<<23U) 143 #define DTSRC_ST_AXI_STATE_IDLE_UV (1<<24U) 144 #define DTSRC_ST_AXI_STATE_FUNC_UV (1<<25U) 145 #define DTSRC_ST_AXI_STATE_FLSH_UV (1<<26U) 146 147 /* 0x30 : axi2dvp_swap_addr_by */ 148 #define DTSRC_CR_AXI_ADDR_SWAP_BY_SHIFT (0U) 149 #define DTSRC_CR_AXI_ADDR_SWAP_BY_MASK (0xffffffff<<DTSRC_CR_AXI_ADDR_SWAP_BY_SHIFT) 150 151 /* 0x34 : axi2dvp_prefetch */ 152 #define DTSRC_CR_PREFETCH_V_SHIFT (0U) 153 #define DTSRC_CR_PREFETCH_V_MASK (0xfff<<DTSRC_CR_PREFETCH_V_SHIFT) 154 155 /* 0x38 : snsr2dvp_wait_pos */ 156 #define DTSRC_CR_SNSR_FIFO_TH_SHIFT (0U) 157 #define DTSRC_CR_SNSR_FIFO_TH_MASK (0x7ff<<DTSRC_CR_SNSR_FIFO_TH_SHIFT) 158 159 /* 0x40 : axi2dvp_start_addr_uv */ 160 #define DTSRC_CR_AXI_ADDR_START_UV_SHIFT (0U) 161 #define DTSRC_CR_AXI_ADDR_START_UV_MASK (0xffffffff<<DTSRC_CR_AXI_ADDR_START_UV_SHIFT) 162 163 /* 0x44 : axi2dvp_swap_addr_uv */ 164 #define DTSRC_CR_AXI_ADDR_SWAP_UV_SHIFT (0U) 165 #define DTSRC_CR_AXI_ADDR_SWAP_UV_MASK (0xffffffff<<DTSRC_CR_AXI_ADDR_SWAP_UV_SHIFT) 166 167 168 #endif /* __HARDWARE_DTSRC_H__ */ 169