1 /** 2 ****************************************************************************** 3 * @file emac_reg.h 4 * @version V1.0 5 * @date 2022-09-27 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2022 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_EMAC_H__ 37 #define __HARDWARE_EMAC_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 #define EMAC_MODE_OFFSET (0x0) 45 #define EMAC_INT_SOURCE_OFFSET (0x4) 46 #define EMAC_INT_MASK_OFFSET (0x8) 47 #define EMAC_IPGT_OFFSET (0xC) 48 #define EMAC_PACKETLEN_OFFSET (0x18) 49 #define EMAC_COLLCONFIG_OFFSET (0x1C) 50 #define EMAC_TX_BD_NUM_OFFSET (0x20) 51 #define EMAC_MIIMODE_OFFSET (0x28) 52 #define EMAC_MIICOMMAND_OFFSET (0x2C) 53 #define EMAC_MIIADDRESS_OFFSET (0x30) 54 #define EMAC_MIITX_DATA_OFFSET (0x34) 55 #define EMAC_MIIRX_DATA_OFFSET (0x38) 56 #define EMAC_MIISTATUS_OFFSET (0x3C) 57 #define EMAC_MAC_ADDR0_OFFSET (0x40) 58 #define EMAC_MAC_ADDR1_OFFSET (0x44) 59 #define EMAC_HASH0_ADDR_OFFSET (0x48) 60 #define EMAC_HASH1_ADDR_OFFSET (0x4C) 61 #define EMAC_TXCTRL_OFFSET (0x50) 62 #define EMAC_DMA_DESC_OFFSET (0x400) 63 64 /* 0x0 : EMAC MODE config */ 65 #define EMAC_RX_EN (1 << 0U) 66 #define EMAC_TX_EN (1 << 1U) 67 #define EMAC_NOPRE (1 << 2U) 68 #define EMAC_BRO (1 << 3U) 69 #define EMAC_PRO (1 << 5U) 70 #define EMAC_IFG (1 << 6U) 71 #define EMAC_FULLD (1 << 10U) 72 #define EMAC_CRCEN (1 << 13U) 73 #define EMAC_HUGEN (1 << 14U) 74 #define EMAC_PAD (1 << 15U) 75 #define EMAC_RECSMALL (1 << 16U) 76 #define EMAC_RMII_EN (1 << 17U) 77 78 /* 0x4 : INT_SOURCE */ 79 #define EMAC_TXB (1 << 0U) 80 #define EMAC_TXE (1 << 1U) 81 #define EMAC_RXB (1 << 2U) 82 #define EMAC_RXE (1 << 3U) 83 #define EMAC_BUSY (1 << 4U) 84 #define EMAC_TXC (1 << 5U) 85 #define EMAC_RXC (1 << 6U) 86 87 /* 0x8 : INT_MASK */ 88 #define EMAC_TXB_M (1 << 0U) 89 #define EMAC_TXE_M (1 << 1U) 90 #define EMAC_RXB_M (1 << 2U) 91 #define EMAC_RXE_M (1 << 3U) 92 #define EMAC_BUSY_M (1 << 4U) 93 #define EMAC_TXC_M (1 << 5U) 94 #define EMAC_RXC_M (1 << 6U) 95 96 /* 0xC : IPGT */ 97 #define EMAC_IPGT_SHIFT (0U) 98 #define EMAC_IPGT_MASK (0x7f << EMAC_IPGT_SHIFT) 99 100 /* 0x18 : PACKETLEN */ 101 #define EMAC_MAXFL_SHIFT (0U) 102 #define EMAC_MAXFL_MASK (0xffff << EMAC_MAXFL_SHIFT) 103 #define EMAC_MINFL_SHIFT (16U) 104 #define EMAC_MINFL_MASK (0xffff << EMAC_MINFL_SHIFT) 105 106 /* 0x1C : COLLCONFIG */ 107 #define EMAC_COLLVALID_SHIFT (0U) 108 #define EMAC_COLLVALID_MASK (0x3F << EMAC_COLLVALID_SHIFT) 109 #define EMAC_MAXRET_SHIFT (16U) 110 #define EMAC_MAXRET_MASK (0xF << EMAC_MAXRET_SHIFT) 111 112 /* 0x20 : TX_BD_NUM */ 113 #define EMAC_TXBDNUM_SHIFT (0U) 114 #define EMAC_TXBDNUM_MASK (0xff << EMAC_TXBDNUM_SHIFT) 115 #define EMAC_TXBDPTR_SHIFT (16U) 116 #define EMAC_TXBDPTR_MASK (0x7f << EMAC_TXBDPTR_SHIFT) 117 #define EMAC_RXBDPTR_SHIFT (24U) 118 #define EMAC_RXBDPTR_MASK (0x7f << EMAC_RXBDPTR_SHIFT) 119 120 /* 0x28 : MIIMODE */ 121 #define EMAC_CLKDIV_SHIFT (0U) 122 #define EMAC_CLKDIV_MASK (0xff << EMAC_CLKDIV_SHIFT) 123 #define EMAC_MIINOPRE (1 << 8U) 124 125 /* 0x2C : MIICOMMAND */ 126 #define EMAC_SCANSTAT (1 << 0U) 127 #define EMAC_RSTAT (1 << 1U) 128 #define EMAC_WCTRLDATA (1 << 2U) 129 130 /* 0x30 : MIIADDRESS */ 131 #define EMAC_FIAD_SHIFT (0U) 132 #define EMAC_FIAD_MASK (0x1f << EMAC_FIAD_SHIFT) 133 #define EMAC_RGAD_SHIFT (8U) 134 #define EMAC_RGAD_MASK (0x1f << EMAC_RGAD_SHIFT) 135 136 /* 0x34 : MIITX_DATA */ 137 #define EMAC_CTRLDATA_SHIFT (0U) 138 #define EMAC_CTRLDATA_MASK (0xffff << EMAC_CTRLDATA_SHIFT) 139 140 /* 0x38 : MIIRX_DATA */ 141 #define EMAC_PRSD_SHIFT (0U) 142 #define EMAC_PRSD_MASK (0xffff << EMAC_PRSD_SHIFT) 143 144 /* 0x3C : MIISTATUS */ 145 #define EMAC_MIIM_LINKFAIL (1 << 0U) 146 #define EMAC_MIIM_BUSY (1 << 1U) 147 148 /* 0x40 : MAC_ADDR0 */ 149 #define EMAC_MAC_B5_SHIFT (0U) 150 #define EMAC_MAC_B5_MASK (0xff << EMAC_MAC_B5_SHIFT) 151 #define EMAC_MAC_B4_SHIFT (8U) 152 #define EMAC_MAC_B4_MASK (0xff << EMAC_MAC_B4_SHIFT) 153 #define EMAC_MAC_B3_SHIFT (16U) 154 #define EMAC_MAC_B3_MASK (0xff << EMAC_MAC_B3_SHIFT) 155 #define EMAC_MAC_B2_SHIFT (24U) 156 #define EMAC_MAC_B2_MASK (0xff << EMAC_MAC_B2_SHIFT) 157 158 /* 0x44 : MAC_ADDR1 */ 159 #define EMAC_MAC_B1_SHIFT (0U) 160 #define EMAC_MAC_B1_MASK (0xff << EMAC_MAC_B1_SHIFT) 161 #define EMAC_MAC_B0_SHIFT (8U) 162 #define EMAC_MAC_B0_MASK (0xff << EMAC_MAC_B0_SHIFT) 163 164 /* 0x48 : HASH0_ADDR */ 165 #define EMAC_HASH0_SHIFT (0U) 166 #define EMAC_HASH0_MASK (0xffffffff << EMAC_HASH0_SHIFT) 167 168 /* 0x4C : HASH1_ADDR */ 169 #define EMAC_HASH1_SHIFT (0U) 170 #define EMAC_HASH1_MASK (0xffffffff << EMAC_HASH1_SHIFT) 171 172 /* 0x50 : TXCTRL */ 173 #define EMAC_TXPAUSETV_SHIFT (0U) 174 #define EMAC_TXPAUSETV_MASK (0xffff << EMAC_TXPAUSETV_SHIFT) 175 #define EMAC_TXPAUSERQ_SHIFT (16U) 176 #define EMAC_TXPAUSERQ_MASK (0x1 << EMAC_TXPAUSETV_SHIFT) 177 178 /* 0x400 ：EAMC DMA BD DESC */ 179 /* EMAC TX BD DESC BASE: (TX_BD_NUM * 8) */ 180 #define EMAC_BD_TX_CS_SHIFT (0) /*!< Carrier Sense Lost */ 181 #define EMAC_BD_TX_CS_MASK (1 << EMAC_BD_TX_CS_SHIFT) 182 #define EMAC_BD_TX_DF_SHIFT (1) /*!< Defer Indication */ 183 #define EMAC_BD_TX_DF_MASK (1 << EMAC_BD_TX_DF_SHIFT) 184 #define EMAC_BD_TX_LC_SHIFT (2) /*!< Late Collision */ 185 #define EMAC_BD_TX_LC_MASK (1 << EMAC_BD_TX_LC_SHIFT) 186 #define EMAC_BD_TX_RL_SHIFT (3) /*!< Retransmission Limit */ 187 #define EMAC_BD_TX_RL_MASK (1 << EMAC_BD_TX_RL_SHIFT) 188 #define EMAC_BD_TX_RTRY_SHIFT (4) /*!< Retry Count */ 189 #define EMAC_BD_TX_RTRY_MASK (4 << EMAC_BD_TX_RTRY_SHIFT) 190 #define EMAC_BD_TX_UR_SHIFT (8) /*!< Underrun */ 191 #define EMAC_BD_TX_UR_MASK (1 << EMAC_BD_TX_UR_SHIFT) 192 #define EMAC_BD_TX_EOF_SHIFT (10) /*!< EOF */ 193 #define EMAC_BD_TX_EOF_MASK (1 << EMAC_BD_TX_EOF_SHIFT) 194 #define EMAC_BD_TX_CRC_SHIFT (11) /*!< CRC Enable */ 195 #define EMAC_BD_TX_CRC_MASK (1 << EMAC_BD_TX_CRC_SHIFT) 196 #define EMAC_BD_TX_PAD_SHIFT (12) /*!< PAD enable */ 197 #define EMAC_BD_TX_PAD_MASK (1 << EMAC_BD_TX_PAD_SHIFT) 198 #define EMAC_BD_TX_WR_SHIFT (13) /*!< Wrap */ 199 #define EMAC_BD_TX_WR_MASK (1 << EMAC_BD_TX_WR_SHIFT) 200 #define EMAC_BD_TX_IRQ_SHIFT (14) /*!< Interrupt Request Enable */ 201 #define EMAC_BD_TX_IRQ_MASK (1 << EMAC_BD_TX_IRQ_SHIFT) 202 #define EMAC_BD_TX_RD_SHIFT (15) /*!< The data buffer is ready for transmission or is currently being transmitted. You are not allowed to change it */ 203 #define EMAC_BD_TX_RD_MASK (1 << EMAC_BD_TX_RD_SHIFT) 204 #define EMAC_BD_TX_LEN_SHIFT (16) /*!< TX Data buffer length */ 205 #define EMAC_BD_TX_LEN_MASK (0xffff << EMAC_BD_TX_LEN_SHIFT) 206 207 /* RX BD DESC BASE: ((TX_BD_NUM + RX_BD_NUM) * 8) */ 208 #define EMAC_BD_RX_LC_SHIFT (0) /*!< Late Collision */ 209 #define EMAC_BD_RX_LC_MASK (1 << EMAC_BD_RX_LC_SHIFT) 210 #define EMAC_BD_RX_CRC_SHIFT (1) /*!< RX CRC Error */ 211 #define EMAC_BD_RX_CRC_MASK (1 << EMAC_BD_RX_CRC_SHIFT) 212 #define EMAC_BD_RX_SF_SHIFT (2) /*!< Short Frame */ 213 #define EMAC_BD_RX_SF_MASK (1 << EMAC_BD_RX_SF_SHIFT) 214 #define EMAC_BD_RX_TL_SHIFT (3) /*!< Too Long */ 215 #define EMAC_BD_RX_TL_MASK (1 << EMAC_BD_RX_TL_SHIFT) 216 #define EMAC_BD_RX_DN_SHIFT (4) /*!< Dribble Nibble */ 217 #define EMAC_BD_RX_DN_MASK (1 << EMAC_BD_RX_DN_SHIFT) 218 #define EMAC_BD_RX_RE_SHIFT (5) /*!< Receive Error */ 219 #define EMAC_BD_RX_RE_MASK (1 << EMAC_BD_RX_RE_SHIFT) 220 #define EMAC_BD_RX_OR_SHIFT (6) /*!< Overrun */ 221 #define EMAC_BD_RX_OR_MASK (1 << EMAC_BD_RX_OR_SHIFT) 222 #define EMAC_BD_RX_M_SHIFT (7) /*!< Miss */ 223 #define EMAC_BD_RX_M_MASK (1 << EMAC_BD_RX_M_SHIFT) 224 #define EMAC_BD_RX_CF_SHIFT (8) /*!< Control Frame Received */ 225 #define EMAC_BD_RX_CF_MASK (1 << EMAC_BD_RX_CF_SHIFT) 226 #define EMAC_BD_RX_WR_SHIFT (13) /*!< Wrap */ 227 #define EMAC_BD_RX_WR_MASK (1 << EMAC_BD_RX_WR_SHIFT) 228 #define EMAC_BD_RX_IRQ_SHIFT (14) /*!< Interrupt Request Enable */ 229 #define EMAC_BD_RX_IRQ_MASK (1 << EMAC_BD_RX_IRQ_SHIFT) 230 #define EMAC_BD_RX_E_SHIFT (15) /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */ 231 #define EMAC_BD_RX_E_MASK (1 << EMAC_BD_RX_E_SHIFT) 232 #define EMAC_BD_RX_LEN_SHIFT (16) /*!< RX Data buffer length */ 233 #define EMAC_BD_RX_LEN_MASK (0xffff << EMAC_BD_RX_LEN_SHIFT) 234 235 /* MAX BD DESC 0x7FF */ 236 237 #endif /* __HARDWARE_EMAC_H__ */