1 /** 2 ****************************************************************************** 3 * @file i2s_reg.h 4 * @version V1.0 5 * @date 2023-01-03 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __I2S_REG_H__ 37 #define __I2S_REG_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define I2S_CONFIG_OFFSET (0x0) /* i2s_config */ 46 #define I2S_INT_STS_OFFSET (0x4) /* i2s_int_sts */ 47 #define I2S_BCLK_CONFIG_OFFSET (0x10) /* i2s_bclk_config */ 48 #define I2S_FIFO_CONFIG_0_OFFSET (0x80) /* i2s_fifo_config_0 */ 49 #define I2S_FIFO_CONFIG_1_OFFSET (0x84) /* i2s_fifo_config_1 */ 50 #define I2S_FIFO_WDATA_OFFSET (0x88) /* i2s_fifo_wdata */ 51 #define I2S_FIFO_RDATA_OFFSET (0x8C) /* i2s_fifo_rdata */ 52 #define I2S_IO_CONFIG_OFFSET (0xFC) /* i2s_io_config */ 53 54 /* Register Bitfield definitions *****************************************************/ 55 56 /* 0x0 : i2s_config */ 57 #define I2S_CR_I2S_M_EN (1 << 0U) 58 #define I2S_CR_I2S_S_EN (1 << 1U) 59 #define I2S_CR_I2S_TXD_EN (1 << 2U) 60 #define I2S_CR_I2S_RXD_EN (1 << 3U) 61 #define I2S_CR_MONO_MODE (1 << 4U) 62 #define I2S_CR_MUTE_MODE (1 << 5U) 63 #define I2S_CR_FS_1T_MODE (1 << 6U) 64 #define I2S_CR_FS_CH_CNT_SHIFT (7U) 65 #define I2S_CR_FS_CH_CNT_MASK (0x3 << I2S_CR_FS_CH_CNT_SHIFT) 66 #define I2S_CR_FRAME_SIZE_SHIFT (12U) 67 #define I2S_CR_FRAME_SIZE_MASK (0x3 << I2S_CR_FRAME_SIZE_SHIFT) 68 #define I2S_CR_DATA_SIZE_SHIFT (14U) 69 #define I2S_CR_DATA_SIZE_MASK (0x3 << I2S_CR_DATA_SIZE_SHIFT) 70 #define I2S_CR_I2S_MODE_SHIFT (16U) 71 #define I2S_CR_I2S_MODE_MASK (0x3 << I2S_CR_I2S_MODE_SHIFT) 72 #define I2S_CR_ENDIAN (1 << 18U) 73 #define I2S_CR_MONO_RX_CH (1 << 19U) 74 #define I2S_CR_OFS_CNT_SHIFT (20U) 75 #define I2S_CR_OFS_CNT_MASK (0x1f << I2S_CR_OFS_CNT_SHIFT) 76 #define I2S_CR_OFS_EN (1 << 25U) 77 78 /* 0x4 : i2s_int_sts */ 79 #define I2S_TXF_INT (1 << 0U) 80 #define I2S_RXF_INT (1 << 1U) 81 #define I2S_FER_INT (1 << 2U) 82 #define I2S_CR_I2S_TXF_MASK (1 << 8U) 83 #define I2S_CR_I2S_RXF_MASK (1 << 9U) 84 #define I2S_CR_I2S_FER_MASK (1 << 10U) 85 #define I2S_CR_I2S_TXF_EN (1 << 24U) 86 #define I2S_CR_I2S_RXF_EN (1 << 25U) 87 #define I2S_CR_I2S_FER_EN (1 << 26U) 88 89 /* 0x10 : i2s_bclk_config */ 90 #define I2S_CR_BCLK_DIV_L_SHIFT (0U) 91 #define I2S_CR_BCLK_DIV_L_MASK (0xfff << I2S_CR_BCLK_DIV_L_SHIFT) 92 #define I2S_CR_BCLK_DIV_H_SHIFT (16U) 93 #define I2S_CR_BCLK_DIV_H_MASK (0xfff << I2S_CR_BCLK_DIV_H_SHIFT) 94 95 /* 0x80 : i2s_fifo_config_0 */ 96 #define I2S_DMA_TX_EN (1 << 0U) 97 #define I2S_DMA_RX_EN (1 << 1U) 98 #define I2S_TX_FIFO_CLR (1 << 2U) 99 #define I2S_RX_FIFO_CLR (1 << 3U) 100 #define I2S_TX_FIFO_OVERFLOW (1 << 4U) 101 #define I2S_TX_FIFO_UNDERFLOW (1 << 5U) 102 #define I2S_RX_FIFO_OVERFLOW (1 << 6U) 103 #define I2S_RX_FIFO_UNDERFLOW (1 << 7U) 104 #define I2S_CR_FIFO_LR_MERGE (1 << 8U) 105 #define I2S_CR_FIFO_LR_EXCHG (1 << 9U) 106 #define I2S_CR_FIFO_24B_LJ (1 << 10U) 107 108 /* 0x84 : i2s_fifo_config_1 */ 109 #define I2S_TX_FIFO_CNT_SHIFT (0U) 110 #define I2S_TX_FIFO_CNT_MASK (0x1f << I2S_TX_FIFO_CNT_SHIFT) 111 #define I2S_RX_FIFO_CNT_SHIFT (8U) 112 #define I2S_RX_FIFO_CNT_MASK (0x1f << I2S_RX_FIFO_CNT_SHIFT) 113 #define I2S_TX_FIFO_TH_SHIFT (16U) 114 #define I2S_TX_FIFO_TH_MASK (0xf << I2S_TX_FIFO_TH_SHIFT) 115 #define I2S_RX_FIFO_TH_SHIFT (24U) 116 #define I2S_RX_FIFO_TH_MASK (0xf << I2S_RX_FIFO_TH_SHIFT) 117 118 /* 0x88 : i2s_fifo_wdata */ 119 #define I2S_FIFO_WDATA_SHIFT (0U) 120 #define I2S_FIFO_WDATA_MASK (0xffffffff << I2S_FIFO_WDATA_SHIFT) 121 122 /* 0x8C : i2s_fifo_rdata */ 123 #define I2S_FIFO_RDATA_SHIFT (0U) 124 #define I2S_FIFO_RDATA_MASK (0xffffffff << I2S_FIFO_RDATA_SHIFT) 125 126 /* 0xFC : i2s_io_config */ 127 #define I2S_CR_I2S_TXD_INV (1 << 0U) 128 #define I2S_CR_I2S_RXD_INV (1 << 1U) 129 #define I2S_CR_I2S_FS_INV (1 << 2U) 130 #define I2S_CR_I2S_BCLK_INV (1 << 3U) 131 #define I2S_CR_DEG_CNT_SHIFT (4U) 132 #define I2S_CR_DEG_CNT_MASK (0x7 << I2S_CR_DEG_CNT_SHIFT) 133 #define I2S_CR_DEG_EN (1 << 7U) 134 135 #endif /* __I2S_REG_H__ */ 136