1 /** 2 ****************************************************************************** 3 * @file platform_dma_reg.h 4 * @version V1.0 5 * @date 2023-03-01 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_PLATFORM_DMA_H__ 37 #define __HARDWARE_PLATFORM_DMA_H__ 38 39 /** @brief Number of registers in the REG_DMA peripheral. 40 */ 41 #define REG_DMA_COUNT 49 42 43 /** @brief Decoding mask of the REG_DMA peripheral registers from the CPU point of view. 44 */ 45 #define REG_DMA_DECODING_MASK 0x000000FF 46 47 /** 48 * @name CH_LLI_ROOT register definitions 49 * 50 * @{ 51 */ 52 53 /// Address of the CH_LLI_ROOT register 54 //#define DMA_CH_LLI_ROOT_ADDR 0x24A00000 55 /// Offset of the CH_LLI_ROOT register from the base address 56 #define DMA_CH_LLI_ROOT_OFFSET 0x00000000 57 /// Index of the CH_LLI_ROOT register 58 #define DMA_CH_LLI_ROOT_INDEX 0x00000000 59 /// Reset value of the CH_LLI_ROOT register 60 #define DMA_CH_LLI_ROOT_RESET 0x00000000 61 /// Number of elements of the CH_LLI_ROOT register array 62 #define DMA_CH_LLI_ROOT_COUNT 4 63 64 /// @} 65 66 /** 67 * @name DMA_STATUS register definitions 68 * <table> 69 * <caption>DMA_STATUS bitfields</caption> 70 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 71 * <tr><td> 31 <td> CH4_STOPPED <td> W <td> R <td> 0 72 * <tr><td> 30 <td> MID_STREAM_BSY <td> W <td> R <td> 0 73 * <tr><td> 29 <td> DOWN_STREAM_BSY <td> W <td> R <td> 0 74 * <tr><td> 28 <td> UP_STREAM_BSY <td> W <td> R <td> 0 75 * <tr><td> 27 <td> ARB_Q4_VALID <td> W <td> R <td> 0 76 * <tr><td> 26 <td> ARB_Q3_VALID <td> W <td> R <td> 0 77 * <tr><td> 25 <td> ARB_Q2_VALID <td> W <td> R <td> 0 78 * <tr><td> 24 <td> ARB_Q1_VALID <td> W <td> R <td> 0 79 * <tr><td> 23 <td> ARB_Q0_VALID <td> W <td> R <td> 0 80 * <tr><td> 22:20 <td> REQUEST_STATE <td> W <td> R <td> 0x0 81 * <tr><td> 19 <td> CH3_STOPPED <td> W <td> R <td> 0 82 * <tr><td> 18 <td> CH2_STOPPED <td> W <td> R <td> 0 83 * <tr><td> 17 <td> CH1_STOPPED <td> W <td> R <td> 0 84 * <tr><td> 16 <td> CH0_STOPPED <td> W <td> R <td> 0 85 * <tr><td> 15:00 <td> OFT_FREE <td> W <td> R <td> 0x0 86 * </table> 87 * 88 * @{ 89 */ 90 91 /// Address of the DMA_STATUS register 92 //#define DMA_DMA_STATUS_ADDR 0x24A00010 93 /// Offset of the DMA_STATUS register from the base address 94 #define DMA_DMA_STATUS_OFFSET 0x00000010 95 /// Index of the DMA_STATUS register 96 #define DMA_DMA_STATUS_INDEX 0x00000004 97 /// Reset value of the DMA_STATUS register 98 #define DMA_DMA_STATUS_RESET 0x00000000 99 100 // field definitions 101 /// CH4_STOPPED field bit 102 #define DMA_CH4_STOPPED_BIT ((uint32_t)0x80000000) 103 /// CH4_STOPPED field position 104 #define DMA_CH4_STOPPED_POS 31 105 /// MID_STREAM_BSY field bit 106 #define DMA_MID_STREAM_BSY_BIT ((uint32_t)0x40000000) 107 /// MID_STREAM_BSY field position 108 #define DMA_MID_STREAM_BSY_POS 30 109 /// DOWN_STREAM_BSY field bit 110 #define DMA_DOWN_STREAM_BSY_BIT ((uint32_t)0x20000000) 111 /// DOWN_STREAM_BSY field position 112 #define DMA_DOWN_STREAM_BSY_POS 29 113 /// UP_STREAM_BSY field bit 114 #define DMA_UP_STREAM_BSY_BIT ((uint32_t)0x10000000) 115 /// UP_STREAM_BSY field position 116 #define DMA_UP_STREAM_BSY_POS 28 117 /// ARB_Q4_VALID field bit 118 #define DMA_ARB_Q4_VALID_BIT ((uint32_t)0x08000000) 119 /// ARB_Q4_VALID field position 120 #define DMA_ARB_Q4_VALID_POS 27 121 /// ARB_Q3_VALID field bit 122 #define DMA_ARB_Q3_VALID_BIT ((uint32_t)0x04000000) 123 /// ARB_Q3_VALID field position 124 #define DMA_ARB_Q3_VALID_POS 26 125 /// ARB_Q2_VALID field bit 126 #define DMA_ARB_Q2_VALID_BIT ((uint32_t)0x02000000) 127 /// ARB_Q2_VALID field position 128 #define DMA_ARB_Q2_VALID_POS 25 129 /// ARB_Q1_VALID field bit 130 #define DMA_ARB_Q1_VALID_BIT ((uint32_t)0x01000000) 131 /// ARB_Q1_VALID field position 132 #define DMA_ARB_Q1_VALID_POS 24 133 /// ARB_Q0_VALID field bit 134 #define DMA_ARB_Q0_VALID_BIT ((uint32_t)0x00800000) 135 /// ARB_Q0_VALID field position 136 #define DMA_ARB_Q0_VALID_POS 23 137 /// REQUEST_STATE field mask 138 #define DMA_REQUEST_STATE_MASK ((uint32_t)0x00700000) 139 /// REQUEST_STATE field LSB position 140 #define DMA_REQUEST_STATE_LSB 20 141 /// REQUEST_STATE field width 142 #define DMA_REQUEST_STATE_WIDTH ((uint32_t)0x00000003) 143 /// CH3_STOPPED field bit 144 #define DMA_CH3_STOPPED_BIT ((uint32_t)0x00080000) 145 /// CH3_STOPPED field position 146 #define DMA_CH3_STOPPED_POS 19 147 /// CH2_STOPPED field bit 148 #define DMA_CH2_STOPPED_BIT ((uint32_t)0x00040000) 149 /// CH2_STOPPED field position 150 #define DMA_CH2_STOPPED_POS 18 151 /// CH1_STOPPED field bit 152 #define DMA_CH1_STOPPED_BIT ((uint32_t)0x00020000) 153 /// CH1_STOPPED field position 154 #define DMA_CH1_STOPPED_POS 17 155 /// CH0_STOPPED field bit 156 #define DMA_CH0_STOPPED_BIT ((uint32_t)0x00010000) 157 /// CH0_STOPPED field position 158 #define DMA_CH0_STOPPED_POS 16 159 /// OFT_FREE field mask 160 #define DMA_OFT_FREE_MASK ((uint32_t)0x0000FFFF) 161 /// OFT_FREE field LSB position 162 #define DMA_OFT_FREE_LSB 0 163 /// OFT_FREE field width 164 #define DMA_OFT_FREE_WIDTH ((uint32_t)0x00000010) 165 166 /// CH4_STOPPED field reset value 167 #define DMA_CH4_STOPPED_RST 0x0 168 /// MID_STREAM_BSY field reset value 169 #define DMA_MID_STREAM_BSY_RST 0x0 170 /// DOWN_STREAM_BSY field reset value 171 #define DMA_DOWN_STREAM_BSY_RST 0x0 172 /// UP_STREAM_BSY field reset value 173 #define DMA_UP_STREAM_BSY_RST 0x0 174 /// ARB_Q4_VALID field reset value 175 #define DMA_ARB_Q4_VALID_RST 0x0 176 /// ARB_Q3_VALID field reset value 177 #define DMA_ARB_Q3_VALID_RST 0x0 178 /// ARB_Q2_VALID field reset value 179 #define DMA_ARB_Q2_VALID_RST 0x0 180 /// ARB_Q1_VALID field reset value 181 #define DMA_ARB_Q1_VALID_RST 0x0 182 /// ARB_Q0_VALID field reset value 183 #define DMA_ARB_Q0_VALID_RST 0x0 184 /// REQUEST_STATE field reset value 185 #define DMA_REQUEST_STATE_RST 0x0 186 /// CH3_STOPPED field reset value 187 #define DMA_CH3_STOPPED_RST 0x0 188 /// CH2_STOPPED field reset value 189 #define DMA_CH2_STOPPED_RST 0x0 190 /// CH1_STOPPED field reset value 191 #define DMA_CH1_STOPPED_RST 0x0 192 /// CH0_STOPPED field reset value 193 #define DMA_CH0_STOPPED_RST 0x0 194 /// OFT_FREE field reset value 195 #define DMA_OFT_FREE_RST 0x0 196 197 /// @} 198 199 /** 200 * @name INT_RAWSTATUS register definitions 201 * <table> 202 * <caption>INT_RAWSTATUS bitfields</caption> 203 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 204 * <tr><td> 24 <td> CH4_EOT <td> W <td> R <td> 0 205 * <tr><td> 23 <td> CH3_EOT <td> W <td> R <td> 0 206 * <tr><td> 22 <td> CH2_EOT <td> W <td> R <td> 0 207 * <tr><td> 21 <td> CH1_EOT <td> W <td> R <td> 0 208 * <tr><td> 20 <td> CH0_EOT <td> W <td> R <td> 0 209 * <tr><td> 16 <td> ERROR <td> W <td> R <td> 0 210 * <tr><td> 15:00 <td> LLI_IRQ <td> W <td> R <td> 0x0 211 * </table> 212 * 213 * @{ 214 */ 215 216 /// Address of the INT_RAWSTATUS register 217 //#define DMA_INT_RAWSTATUS_ADDR 0x24A00014 218 /// Offset of the INT_RAWSTATUS register from the base address 219 #define DMA_INT_RAWSTATUS_OFFSET 0x00000014 220 /// Index of the INT_RAWSTATUS register 221 #define DMA_INT_RAWSTATUS_INDEX 0x00000005 222 /// Reset value of the INT_RAWSTATUS register 223 #define DMA_INT_RAWSTATUS_RESET 0x00000000 224 225 // field definitions 226 /// CH4_EOT field bit 227 #define DMA_CH4_EOT_BIT ((uint32_t)0x01000000) 228 /// CH4_EOT field position 229 #define DMA_CH4_EOT_POS 24 230 /// CH3_EOT field bit 231 #define DMA_CH3_EOT_BIT ((uint32_t)0x00800000) 232 /// CH3_EOT field position 233 #define DMA_CH3_EOT_POS 23 234 /// CH2_EOT field bit 235 #define DMA_CH2_EOT_BIT ((uint32_t)0x00400000) 236 /// CH2_EOT field position 237 #define DMA_CH2_EOT_POS 22 238 /// CH1_EOT field bit 239 #define DMA_CH1_EOT_BIT ((uint32_t)0x00200000) 240 /// CH1_EOT field position 241 #define DMA_CH1_EOT_POS 21 242 /// CH0_EOT field bit 243 #define DMA_CH0_EOT_BIT ((uint32_t)0x00100000) 244 /// CH0_EOT field position 245 #define DMA_CH0_EOT_POS 20 246 /// ERROR field bit 247 #define DMA_ERROR_BIT ((uint32_t)0x00010000) 248 /// ERROR field position 249 #define DMA_ERROR_POS 16 250 /// LLI_IRQ field mask 251 #define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF) 252 /// LLI_IRQ field LSB position 253 #define DMA_LLI_IRQ_LSB 0 254 /// LLI_IRQ field width 255 #define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010) 256 257 /// CH4_EOT field reset value 258 #define DMA_CH4_EOT_RST 0x0 259 /// CH3_EOT field reset value 260 #define DMA_CH3_EOT_RST 0x0 261 /// CH2_EOT field reset value 262 #define DMA_CH2_EOT_RST 0x0 263 /// CH1_EOT field reset value 264 #define DMA_CH1_EOT_RST 0x0 265 /// CH0_EOT field reset value 266 #define DMA_CH0_EOT_RST 0x0 267 /// ERROR field reset value 268 #define DMA_ERROR_RST 0x0 269 /// LLI_IRQ field reset value 270 #define DMA_LLI_IRQ_RST 0x0 271 272 /// @} 273 274 /** 275 * @name INT_UNMASK_SET register definitions 276 * <table> 277 * <caption>INT_UNMASK_SET bitfields</caption> 278 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 279 * <tr><td> 24 <td> CH4_EOT <td> R/W <td> S <td> 0 280 * <tr><td> 23 <td> CH3_EOT <td> R/W <td> S <td> 0 281 * <tr><td> 22 <td> CH2_EOT <td> R/W <td> S <td> 0 282 * <tr><td> 21 <td> CH1_EOT <td> R/W <td> S <td> 0 283 * <tr><td> 20 <td> CH0_EOT <td> R/W <td> S <td> 0 284 * <tr><td> 16 <td> ERROR <td> R/W <td> S <td> 0 285 * <tr><td> 15:00 <td> LLI_IRQ <td> R/W <td> S <td> 0x0 286 * </table> 287 * 288 * @{ 289 */ 290 291 /// Address of the INT_UNMASK_SET register 292 //#define DMA_INT_UNMASK_SET_ADDR 0x24A00018 293 /// Offset of the INT_UNMASK_SET register from the base address 294 #define DMA_INT_UNMASK_SET_OFFSET 0x00000018 295 /// Index of the INT_UNMASK_SET register 296 #define DMA_INT_UNMASK_SET_INDEX 0x00000006 297 /// Reset value of the INT_UNMASK_SET register 298 #define DMA_INT_UNMASK_SET_RESET 0x00000000 299 300 // field definitions 301 /// CH4_EOT field bit 302 #define DMA_CH4_EOT_BIT ((uint32_t)0x01000000) 303 /// CH4_EOT field position 304 #define DMA_CH4_EOT_POS 24 305 /// CH3_EOT field bit 306 #define DMA_CH3_EOT_BIT ((uint32_t)0x00800000) 307 /// CH3_EOT field position 308 #define DMA_CH3_EOT_POS 23 309 /// CH2_EOT field bit 310 #define DMA_CH2_EOT_BIT ((uint32_t)0x00400000) 311 /// CH2_EOT field position 312 #define DMA_CH2_EOT_POS 22 313 /// CH1_EOT field bit 314 #define DMA_CH1_EOT_BIT ((uint32_t)0x00200000) 315 /// CH1_EOT field position 316 #define DMA_CH1_EOT_POS 21 317 /// CH0_EOT field bit 318 #define DMA_CH0_EOT_BIT ((uint32_t)0x00100000) 319 /// CH0_EOT field position 320 #define DMA_CH0_EOT_POS 20 321 /// ERROR field bit 322 #define DMA_ERROR_BIT ((uint32_t)0x00010000) 323 /// ERROR field position 324 #define DMA_ERROR_POS 16 325 /// LLI_IRQ field mask 326 #define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF) 327 /// LLI_IRQ field LSB position 328 #define DMA_LLI_IRQ_LSB 0 329 /// LLI_IRQ field width 330 #define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010) 331 332 /// CH4_EOT field reset value 333 #define DMA_CH4_EOT_RST 0x0 334 /// CH3_EOT field reset value 335 #define DMA_CH3_EOT_RST 0x0 336 /// CH2_EOT field reset value 337 #define DMA_CH2_EOT_RST 0x0 338 /// CH1_EOT field reset value 339 #define DMA_CH1_EOT_RST 0x0 340 /// CH0_EOT field reset value 341 #define DMA_CH0_EOT_RST 0x0 342 /// ERROR field reset value 343 #define DMA_ERROR_RST 0x0 344 /// LLI_IRQ field reset value 345 #define DMA_LLI_IRQ_RST 0x0 346 347 /// @} 348 349 /** 350 * @name INT_UNMASK_CLEAR register definitions 351 * <table> 352 * <caption>INT_UNMASK_CLEAR bitfields</caption> 353 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 354 * <tr><td> 24 <td> CH4_EOT <td> R/W <td> C <td> 0 355 * <tr><td> 23 <td> CH3_EOT <td> R/W <td> C <td> 0 356 * <tr><td> 22 <td> CH2_EOT <td> R/W <td> C <td> 0 357 * <tr><td> 21 <td> CH1_EOT <td> R/W <td> C <td> 0 358 * <tr><td> 20 <td> CH0_EOT <td> R/W <td> C <td> 0 359 * <tr><td> 16 <td> ERROR <td> R/W <td> C <td> 0 360 * <tr><td> 15:00 <td> LLI_IRQ <td> R/W <td> C <td> 0x0 361 * </table> 362 * 363 * @{ 364 */ 365 366 /// Address of the INT_UNMASK_CLEAR register 367 //#define DMA_INT_UNMASK_CLEAR_ADDR 0x24A0001C 368 /// Offset of the INT_UNMASK_CLEAR register from the base address 369 #define DMA_INT_UNMASK_CLEAR_OFFSET 0x0000001C 370 /// Index of the INT_UNMASK_CLEAR register 371 #define DMA_INT_UNMASK_CLEAR_INDEX 0x00000007 372 /// Reset value of the INT_UNMASK_CLEAR register 373 #define DMA_INT_UNMASK_CLEAR_RESET 0x00000000 374 375 /// @} 376 377 /** 378 * @name INT_ACK register definitions 379 * <table> 380 * <caption>INT_ACK bitfields</caption> 381 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 382 * <tr><td> 24 <td> CH4_EOT <td> R/W <td> C <td> 0 383 * <tr><td> 23 <td> CH3_EOT <td> R/W <td> C <td> 0 384 * <tr><td> 22 <td> CH2_EOT <td> R/W <td> C <td> 0 385 * <tr><td> 21 <td> CH1_EOT <td> R/W <td> C <td> 0 386 * <tr><td> 20 <td> CH0_EOT <td> R/W <td> C <td> 0 387 * <tr><td> 16 <td> ERROR <td> R/W <td> C <td> 0 388 * <tr><td> 15:00 <td> LLI_IRQ <td> R/W <td> C <td> 0x0 389 * </table> 390 * 391 * @{ 392 */ 393 394 /// Address of the INT_ACK register 395 //#define DMA_INT_ACK_ADDR 0x24A00020 396 /// Offset of the INT_ACK register from the base address 397 #define DMA_INT_ACK_OFFSET 0x00000020 398 /// Index of the INT_ACK register 399 #define DMA_INT_ACK_INDEX 0x00000008 400 /// Reset value of the INT_ACK register 401 #define DMA_INT_ACK_RESET 0x00000000 402 403 404 // field definitions 405 /// CH4_EOT field bit 406 #define DMA_CH4_EOT_BIT ((uint32_t)0x01000000) 407 /// CH4_EOT field position 408 #define DMA_CH4_EOT_POS 24 409 /// CH3_EOT field bit 410 #define DMA_CH3_EOT_BIT ((uint32_t)0x00800000) 411 /// CH3_EOT field position 412 #define DMA_CH3_EOT_POS 23 413 /// CH2_EOT field bit 414 #define DMA_CH2_EOT_BIT ((uint32_t)0x00400000) 415 /// CH2_EOT field position 416 #define DMA_CH2_EOT_POS 22 417 /// CH1_EOT field bit 418 #define DMA_CH1_EOT_BIT ((uint32_t)0x00200000) 419 /// CH1_EOT field position 420 #define DMA_CH1_EOT_POS 21 421 /// CH0_EOT field bit 422 #define DMA_CH0_EOT_BIT ((uint32_t)0x00100000) 423 /// CH0_EOT field position 424 #define DMA_CH0_EOT_POS 20 425 /// ERROR field bit 426 #define DMA_ERROR_BIT ((uint32_t)0x00010000) 427 /// ERROR field position 428 #define DMA_ERROR_POS 16 429 /// LLI_IRQ field mask 430 #define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF) 431 /// LLI_IRQ field LSB position 432 #define DMA_LLI_IRQ_LSB 0 433 /// LLI_IRQ field width 434 #define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010) 435 436 /// CH4_EOT field reset value 437 #define DMA_CH4_EOT_RST 0x0 438 /// CH3_EOT field reset value 439 #define DMA_CH3_EOT_RST 0x0 440 /// CH2_EOT field reset value 441 #define DMA_CH2_EOT_RST 0x0 442 /// CH1_EOT field reset value 443 #define DMA_CH1_EOT_RST 0x0 444 /// CH0_EOT field reset value 445 #define DMA_CH0_EOT_RST 0x0 446 /// ERROR field reset value 447 #define DMA_ERROR_RST 0x0 448 /// LLI_IRQ field reset value 449 #define DMA_LLI_IRQ_RST 0x0 450 451 /// @} 452 453 /** 454 * @name INT_STATUS register definitions 455 * <table> 456 * <caption>INT_STATUS bitfields</caption> 457 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 458 * <tr><td> 24 <td> CH4_EOT <td> W <td> R <td> 0 459 * <tr><td> 23 <td> CH3_EOT <td> W <td> R <td> 0 460 * <tr><td> 22 <td> CH2_EOT <td> W <td> R <td> 0 461 * <tr><td> 21 <td> CH1_EOT <td> W <td> R <td> 0 462 * <tr><td> 20 <td> CH0_EOT <td> W <td> R <td> 0 463 * <tr><td> 16 <td> ERROR <td> W <td> R <td> 0 464 * <tr><td> 15:00 <td> LLI_IRQ <td> W <td> R <td> 0x0 465 * </table> 466 * 467 * @{ 468 */ 469 470 /// Address of the INT_STATUS register 471 //#define DMA_INT_STATUS_ADDR 0x24A00024 472 /// Offset of the INT_STATUS register from the base address 473 #define DMA_INT_STATUS_OFFSET 0x00000024 474 /// Index of the INT_STATUS register 475 #define DMA_INT_STATUS_INDEX 0x00000009 476 /// Reset value of the INT_STATUS register 477 #define DMA_INT_STATUS_RESET 0x00000000 478 479 // field definitions 480 /// CH4_EOT field bit 481 #define DMA_CH4_EOT_BIT ((uint32_t)0x01000000) 482 /// CH4_EOT field position 483 #define DMA_CH4_EOT_POS 24 484 /// CH3_EOT field bit 485 #define DMA_CH3_EOT_BIT ((uint32_t)0x00800000) 486 /// CH3_EOT field position 487 #define DMA_CH3_EOT_POS 23 488 /// CH2_EOT field bit 489 #define DMA_CH2_EOT_BIT ((uint32_t)0x00400000) 490 /// CH2_EOT field position 491 #define DMA_CH2_EOT_POS 22 492 /// CH1_EOT field bit 493 #define DMA_CH1_EOT_BIT ((uint32_t)0x00200000) 494 /// CH1_EOT field position 495 #define DMA_CH1_EOT_POS 21 496 /// CH0_EOT field bit 497 #define DMA_CH0_EOT_BIT ((uint32_t)0x00100000) 498 /// CH0_EOT field position 499 #define DMA_CH0_EOT_POS 20 500 /// ERROR field bit 501 #define DMA_ERROR_BIT ((uint32_t)0x00010000) 502 /// ERROR field position 503 #define DMA_ERROR_POS 16 504 /// LLI_IRQ field mask 505 #define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF) 506 /// LLI_IRQ field LSB position 507 #define DMA_LLI_IRQ_LSB 0 508 /// LLI_IRQ field width 509 #define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010) 510 511 /// CH4_EOT field reset value 512 #define DMA_CH4_EOT_RST 0x0 513 /// CH3_EOT field reset value 514 #define DMA_CH3_EOT_RST 0x0 515 /// CH2_EOT field reset value 516 #define DMA_CH2_EOT_RST 0x0 517 /// CH1_EOT field reset value 518 #define DMA_CH1_EOT_RST 0x0 519 /// CH0_EOT field reset value 520 #define DMA_CH0_EOT_RST 0x0 521 /// ERROR field reset value 522 #define DMA_ERROR_RST 0x0 523 /// LLI_IRQ field reset value 524 #define DMA_LLI_IRQ_RST 0x0 525 526 /// @} 527 528 /** 529 * @name ARBITRATION register definitions 530 * <table> 531 * <caption>ARBITRATION bitfields</caption> 532 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 533 * <tr><td> 03:00 <td> DOWNSTREAM_TAG_USAGE <td> R <td> R/W <td> 0xC 534 * </table> 535 * 536 * @{ 537 */ 538 539 /// Address of the ARBITRATION register 540 //#define DMA_ARBITRATION_ADDR 0x24A00034 541 /// Offset of the ARBITRATION register from the base address 542 #define DMA_ARBITRATION_OFFSET 0x00000034 543 /// Index of the ARBITRATION register 544 #define DMA_ARBITRATION_INDEX 0x0000000D 545 /// Reset value of the ARBITRATION register 546 #define DMA_ARBITRATION_RESET 0x0000000C 547 548 // field definitions 549 /// DOWNSTREAM_TAG_USAGE field mask 550 #define DMA_DOWNSTREAM_TAG_USAGE_MASK ((uint32_t)0x0000000F) 551 /// DOWNSTREAM_TAG_USAGE field LSB position 552 #define DMA_DOWNSTREAM_TAG_USAGE_LSB 0 553 /// DOWNSTREAM_TAG_USAGE field width 554 #define DMA_DOWNSTREAM_TAG_USAGE_WIDTH ((uint32_t)0x00000004) 555 556 /// DOWNSTREAM_TAG_USAGE field reset value 557 #define DMA_DOWNSTREAM_TAG_USAGE_RST 0xC 558 559 /// @} 560 561 /** 562 * @name CHANNEL_MUTEX_SET register definitions 563 * <table> 564 * <caption>CHANNEL_MUTEX_SET bitfields</caption> 565 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 566 * <tr><td> 04 <td> CH4_MUTEX <td> R/W <td> S <td> 0 567 * <tr><td> 03 <td> CH3_MUTEX <td> R/W <td> S <td> 0 568 * <tr><td> 02 <td> CH2_MUTEX <td> R/W <td> S <td> 0 569 * <tr><td> 01 <td> CH1_MUTEX <td> R/W <td> S <td> 0 570 * <tr><td> 00 <td> CH0_MUTEX <td> R/W <td> S <td> 0 571 * </table> 572 * 573 * @{ 574 */ 575 576 /// Address of the CHANNEL_MUTEX_SET register 577 //#define DMA_CHANNEL_MUTEX_SET_ADDR 0x24A00038 578 /// Offset of the CHANNEL_MUTEX_SET register from the base address 579 #define DMA_CHANNEL_MUTEX_SET_OFFSET 0x00000038 580 /// Index of the CHANNEL_MUTEX_SET register 581 #define DMA_CHANNEL_MUTEX_SET_INDEX 0x0000000E 582 /// Reset value of the CHANNEL_MUTEX_SET register 583 #define DMA_CHANNEL_MUTEX_SET_RESET 0x00000000 584 585 // field definitions 586 /// CH4_MUTEX field bit 587 #define DMA_CH4_MUTEX_BIT ((uint32_t)0x00000010) 588 /// CH4_MUTEX field position 589 #define DMA_CH4_MUTEX_POS 4 590 /// CH3_MUTEX field bit 591 #define DMA_CH3_MUTEX_BIT ((uint32_t)0x00000008) 592 /// CH3_MUTEX field position 593 #define DMA_CH3_MUTEX_POS 3 594 /// CH2_MUTEX field bit 595 #define DMA_CH2_MUTEX_BIT ((uint32_t)0x00000004) 596 /// CH2_MUTEX field position 597 #define DMA_CH2_MUTEX_POS 2 598 /// CH1_MUTEX field bit 599 #define DMA_CH1_MUTEX_BIT ((uint32_t)0x00000002) 600 /// CH1_MUTEX field position 601 #define DMA_CH1_MUTEX_POS 1 602 /// CH0_MUTEX field bit 603 #define DMA_CH0_MUTEX_BIT ((uint32_t)0x00000001) 604 /// CH0_MUTEX field position 605 #define DMA_CH0_MUTEX_POS 0 606 607 /// CH4_MUTEX field reset value 608 #define DMA_CH4_MUTEX_RST 0x0 609 /// CH3_MUTEX field reset value 610 #define DMA_CH3_MUTEX_RST 0x0 611 /// CH2_MUTEX field reset value 612 #define DMA_CH2_MUTEX_RST 0x0 613 /// CH1_MUTEX field reset value 614 #define DMA_CH1_MUTEX_RST 0x0 615 /// CH0_MUTEX field reset value 616 #define DMA_CH0_MUTEX_RST 0x0 617 618 /// @} 619 620 /** 621 * @name CHANNEL_MUTEX_CLEAR register definitions 622 * <table> 623 * <caption>CHANNEL_MUTEX_CLEAR bitfields</caption> 624 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 625 * <tr><td> 04 <td> CH4_MUTEX <td> R/W <td> C <td> 0 626 * <tr><td> 03 <td> CH3_MUTEX <td> R/W <td> C <td> 0 627 * <tr><td> 02 <td> CH2_MUTEX <td> R/W <td> C <td> 0 628 * <tr><td> 01 <td> CH1_MUTEX <td> R/W <td> C <td> 0 629 * <tr><td> 00 <td> CH0_MUTEX <td> R/W <td> C <td> 0 630 * </table> 631 * 632 * @{ 633 */ 634 635 /// Address of the CHANNEL_MUTEX_CLEAR register 636 //#define DMA_CHANNEL_MUTEX_CLEAR_ADDR 0x24A0003C 637 /// Offset of the CHANNEL_MUTEX_CLEAR register from the base address 638 #define DMA_CHANNEL_MUTEX_CLEAR_OFFSET 0x0000003C 639 /// Index of the CHANNEL_MUTEX_CLEAR register 640 #define DMA_CHANNEL_MUTEX_CLEAR_INDEX 0x0000000F 641 /// Reset value of the CHANNEL_MUTEX_CLEAR register 642 #define DMA_CHANNEL_MUTEX_CLEAR_RESET 0x00000000 643 644 /// @} 645 646 /** 647 * @name CH4_LLI_ROOT register definitions 648 * <table> 649 * <caption>CH4_LLI_ROOT bitfields</caption> 650 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 651 * <tr><td> 31:00 <td> CH4_LLI_ROOT <td> R <td> R/W <td> 0x0 652 * </table> 653 * 654 * @{ 655 */ 656 657 /// Address of the CH4_LLI_ROOT register 658 //#define DMA_CH4_LLI_ROOT_ADDR 0x24A00040 659 /// Offset of the CH4_LLI_ROOT register from the base address 660 #define DMA_CH4_LLI_ROOT_OFFSET 0x00000040 661 /// Index of the CH4_LLI_ROOT register 662 #define DMA_CH4_LLI_ROOT_INDEX 0x00000010 663 /// Reset value of the CH4_LLI_ROOT register 664 #define DMA_CH4_LLI_ROOT_RESET 0x00000000 665 666 // field definitions 667 /// CH4_LLI_ROOT field mask 668 #define DMA_CH4_LLI_ROOT_MASK ((uint32_t)0xFFFFFFFF) 669 /// CH4_LLI_ROOT field LSB position 670 #define DMA_CH4_LLI_ROOT_LSB 0 671 /// CH4_LLI_ROOT field width 672 #define DMA_CH4_LLI_ROOT_WIDTH ((uint32_t)0x00000020) 673 674 /// CH4_LLI_ROOT field reset value 675 #define DMA_CH4_LLI_ROOT_RST 0x0 676 677 /// @} 678 679 /** 680 * @name LLI_COUNTER register definitions 681 * <table> 682 * <caption>LLI_COUNTER bitfields</caption> 683 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 684 * <tr><td> 15:00 <td> COUNTER <td> W <td> R <td> 0x0 685 * </table> 686 * 687 * @{ 688 */ 689 690 /// Address of the LLI_COUNTER register 691 //#define DMA_LLI_COUNTER_ADDR 0x24A00080 692 /// Offset of the LLI_COUNTER register from the base address 693 #define DMA_LLI_COUNTER_OFFSET 0x00000080 694 /// Index of the LLI_COUNTER register 695 #define DMA_LLI_COUNTER_INDEX 0x00000020 696 /// Reset value of the LLI_COUNTER register 697 #define DMA_LLI_COUNTER_RESET 0x00000000 698 /// Number of elements of the LLI_COUNTER register array 699 #define DMA_LLI_COUNTER_COUNT 16 700 701 // field definitions 702 /// COUNTER field mask 703 #define DMA_COUNTER_MASK ((uint32_t)0x0000FFFF) 704 /// COUNTER field LSB position 705 #define DMA_COUNTER_LSB 0 706 /// COUNTER field width 707 #define DMA_COUNTER_WIDTH ((uint32_t)0x00000010) 708 709 /// COUNTER field reset value 710 #define DMA_COUNTER_RST 0x0 711 712 /// @} 713 714 /** 715 * @name DUMMY register definitions 716 * <table> 717 * <caption>DUMMY bitfields</caption> 718 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value 719 * <tr><td> 00 <td> DUMMY <td> R <td> R/W <td> 0 720 * </table> 721 * 722 * @{ 723 */ 724 725 /// Address of the DUMMY register 726 //#define DMA_DUMMY_ADDR 0x24A000C0 727 /// Offset of the DUMMY register from the base address 728 #define DMA_DUMMY_OFFSET 0x000000C0 729 /// Index of the DUMMY register 730 #define DMA_DUMMY_INDEX 0x00000030 731 /// Reset value of the DUMMY register 732 #define DMA_DUMMY_RESET 0x00000000 733 734 // field definitions 735 /// DUMMY field bit 736 #define DMA_DUMMY_BIT ((uint32_t)0x00000001) 737 /// DUMMY field position 738 #define DMA_DUMMY_POS 0 739 740 /// DUMMY field reset value 741 #define DMA_DUMMY_RST 0x0 742 743 744 /// @} 745 746 #endif /* __HARDWARE_PLATFORM_DMA_H__ */ 747