1 /** 2 ****************************************************************************** 3 * @file pwm_reg.h 4 * @version V1.0 5 * @date 2022-10-10 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __PWM_REG_H__ 37 #define __PWM_REG_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 #if defined(BL702L) 45 #define PWM_INT_CONFIG_OFFSET (-0x20) /* pwm_int_config */ 46 #else 47 #define PWM_INT_CONFIG_OFFSET (0x0) /* pwm_int_config */ 48 #endif 49 #define PWM0_CLKDIV_OFFSET (0x20) /* pwm0_clkdiv */ 50 #define PWM0_THRE1_OFFSET (0x24) /* pwm0_thre1 */ 51 #define PWM0_THRE2_OFFSET (0x28) /* pwm0_thre2 */ 52 #define PWM0_PERIOD_OFFSET (0x2C) /* pwm0_period */ 53 #define PWM0_CONFIG_OFFSET (0x30) /* pwm0_config */ 54 #define PWM0_INTERRUPT_OFFSET (0x34) /* pwm0_interrupt */ 55 #define PWM1_CLKDIV_OFFSET (0x40) /* pwm1_clkdiv */ 56 #define PWM1_THRE1_OFFSET (0x44) /* pwm1_thre1 */ 57 #define PWM1_THRE2_OFFSET (0x48) /* pwm1_thre2 */ 58 #define PWM1_PERIOD_OFFSET (0x4C) /* pwm1_period */ 59 #define PWM1_CONFIG_OFFSET (0x50) /* pwm1_config */ 60 #define PWM1_INTERRUPT_OFFSET (0x54) /* pwm1_interrupt */ 61 #define PWM2_CLKDIV_OFFSET (0x60) /* pwm2_clkdiv */ 62 #define PWM2_THRE1_OFFSET (0x64) /* pwm2_thre1 */ 63 #define PWM2_THRE2_OFFSET (0x68) /* pwm2_thre2 */ 64 #define PWM2_PERIOD_OFFSET (0x6C) /* pwm2_period */ 65 #define PWM2_CONFIG_OFFSET (0x70) /* pwm2_config */ 66 #define PWM2_INTERRUPT_OFFSET (0x74) /* pwm2_interrupt */ 67 #define PWM3_CLKDIV_OFFSET (0x80) /* pwm3_clkdiv */ 68 #define PWM3_THRE1_OFFSET (0x84) /* pwm3_thre1 */ 69 #define PWM3_THRE2_OFFSET (0x88) /* pwm3_thre2 */ 70 #define PWM3_PERIOD_OFFSET (0x8C) /* pwm3_period */ 71 #define PWM3_CONFIG_OFFSET (0x90) /* pwm3_config */ 72 #define PWM3_INTERRUPT_OFFSET (0x94) /* pwm3_interrupt */ 73 #define PWM4_CLKDIV_OFFSET (0xA0) /* pwm4_clkdiv */ 74 #define PWM4_THRE1_OFFSET (0xA4) /* pwm4_thre1 */ 75 #define PWM4_THRE2_OFFSET (0xA8) /* pwm4_thre2 */ 76 #define PWM4_PERIOD_OFFSET (0xAC) /* pwm4_period */ 77 #define PWM4_CONFIG_OFFSET (0xB0) /* pwm4_config */ 78 #define PWM4_INTERRUPT_OFFSET (0xB4) /* pwm4_interrupt */ 79 80 /* Register Bitfield definitions *****************************************************/ 81 82 /* 0x0 : pwm_int_config */ 83 #define PWM_INTERRUPT_STS_SHIFT (0U) 84 #define PWM_INTERRUPT_STS_MASK (0x3f << PWM_INTERRUPT_STS_SHIFT) 85 #define PWM_INT_CLEAR_SHIFT (8U) 86 #define PWM_INT_CLEAR_MASK (0x3f << PWM_INT_CLEAR_SHIFT) 87 88 /* 0x20 : pwm0_clkdiv */ 89 #define PWM_CLK_DIV_SHIFT (0U) 90 #define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT) 91 92 /* 0x24 : pwm0_thre1 */ 93 #define PWM_THRE1_SHIFT (0U) 94 #define PWM_THRE1_MASK (0xffff << PWM_THRE1_SHIFT) 95 96 /* 0x28 : pwm0_thre2 */ 97 #define PWM_THRE2_SHIFT (0U) 98 #define PWM_THRE2_MASK (0xffff << PWM_THRE2_SHIFT) 99 100 /* 0x2C : pwm0_period */ 101 #define PWM_PERIOD_SHIFT (0U) 102 #define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT) 103 104 /* 0x30 : pwm0_config */ 105 #define PWM_REG_CLK_SEL_SHIFT (0U) 106 #define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT) 107 #define PWM_OUT_INV (1 << 2U) 108 #define PWM_STOP_MODE (1 << 3U) 109 #define PWM_SW_FORCE_VAL (1 << 4U) 110 #define PWM_SW_MODE (1 << 5U) 111 #define PWM_STOP_EN (1 << 6U) 112 #define PWM_STS_TOP (1 << 7U) 113 114 /* 0x34 : pwm0_interrupt */ 115 #define PWM_INT_PERIOD_CNT_SHIFT (0U) 116 #define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT) 117 #define PWM_INT_ENABLE (1 << 16U) 118 119 /* 0x40 : pwm1_clkdiv */ 120 #define PWM_CLK_DIV_SHIFT (0U) 121 #define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT) 122 123 /* 0x44 : pwm1_thre1 */ 124 #define PWM_THRE1_SHIFT (0U) 125 #define PWM_THRE1_MASK (0xffff << PWM_THRE1_SHIFT) 126 127 /* 0x48 : pwm1_thre2 */ 128 #define PWM_THRE2_SHIFT (0U) 129 #define PWM_THRE2_MASK (0xffff << PWM_THRE2_SHIFT) 130 131 /* 0x4C : pwm1_period */ 132 #define PWM_PERIOD_SHIFT (0U) 133 #define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT) 134 135 /* 0x50 : pwm1_config */ 136 #define PWM_REG_CLK_SEL_SHIFT (0U) 137 #define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT) 138 #define PWM_OUT_INV (1 << 2U) 139 #define PWM_STOP_MODE (1 << 3U) 140 #define PWM_SW_FORCE_VAL (1 << 4U) 141 #define PWM_SW_MODE (1 << 5U) 142 #define PWM_STOP_EN (1 << 6U) 143 #define PWM_STS_TOP (1 << 7U) 144 145 /* 0x54 : pwm1_interrupt */ 146 #define PWM_INT_PERIOD_CNT_SHIFT (0U) 147 #define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT) 148 #define PWM_INT_ENABLE (1 << 16U) 149 150 /* 0x60 : pwm2_clkdiv */ 151 #define PWM_CLK_DIV_SHIFT (0U) 152 #define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT) 153 154 /* 0x64 : pwm2_thre1 */ 155 #define PWM_THRE1_SHIFT (0U) 156 #define PWM_THRE1_MASK (0xffff << PWM_THRE1_SHIFT) 157 158 /* 0x68 : pwm2_thre2 */ 159 #define PWM_THRE2_SHIFT (0U) 160 #define PWM_THRE2_MASK (0xffff << PWM_THRE2_SHIFT) 161 162 /* 0x6C : pwm2_period */ 163 #define PWM_PERIOD_SHIFT (0U) 164 #define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT) 165 166 /* 0x70 : pwm2_config */ 167 #define PWM_REG_CLK_SEL_SHIFT (0U) 168 #define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT) 169 #define PWM_OUT_INV (1 << 2U) 170 #define PWM_STOP_MODE (1 << 3U) 171 #define PWM_SW_FORCE_VAL (1 << 4U) 172 #define PWM_SW_MODE (1 << 5U) 173 #define PWM_STOP_EN (1 << 6U) 174 #define PWM_STS_TOP (1 << 7U) 175 176 /* 0x74 : pwm2_interrupt */ 177 #define PWM_INT_PERIOD_CNT_SHIFT (0U) 178 #define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT) 179 #define PWM_INT_ENABLE (1 << 16U) 180 181 /* 0x80 : pwm3_clkdiv */ 182 #define PWM_CLK_DIV_SHIFT (0U) 183 #define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT) 184 185 /* 0x84 : pwm3_thre1 */ 186 #define PWM_THRE1_SHIFT (0U) 187 #define PWM_THRE1_MASK (0xffff << PWM_THRE1_SHIFT) 188 189 /* 0x88 : pwm3_thre2 */ 190 #define PWM_THRE2_SHIFT (0U) 191 #define PWM_THRE2_MASK (0xffff << PWM_THRE2_SHIFT) 192 193 /* 0x8C : pwm3_period */ 194 #define PWM_PERIOD_SHIFT (0U) 195 #define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT) 196 197 /* 0x90 : pwm3_config */ 198 #define PWM_REG_CLK_SEL_SHIFT (0U) 199 #define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT) 200 #define PWM_OUT_INV (1 << 2U) 201 #define PWM_STOP_MODE (1 << 3U) 202 #define PWM_SW_FORCE_VAL (1 << 4U) 203 #define PWM_SW_MODE (1 << 5U) 204 #define PWM_STOP_EN (1 << 6U) 205 #define PWM_STS_TOP (1 << 7U) 206 207 /* 0x94 : pwm3_interrupt */ 208 #define PWM_INT_PERIOD_CNT_SHIFT (0U) 209 #define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT) 210 #define PWM_INT_ENABLE (1 << 16U) 211 212 /* 0xA0 : pwm4_clkdiv */ 213 #define PWM_CLK_DIV_SHIFT (0U) 214 #define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT) 215 216 /* 0xA4 : pwm4_thre1 */ 217 #define PWM_THRE1_SHIFT (0U) 218 #define PWM_THRE1_MASK (0xffff << PWM_THRE1_SHIFT) 219 220 /* 0xA8 : pwm4_thre2 */ 221 #define PWM_THRE2_SHIFT (0U) 222 #define PWM_THRE2_MASK (0xffff << PWM_THRE2_SHIFT) 223 224 /* 0xAC : pwm4_period */ 225 #define PWM_PERIOD_SHIFT (0U) 226 #define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT) 227 228 /* 0xB0 : pwm4_config */ 229 #define PWM_REG_CLK_SEL_SHIFT (0U) 230 #define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT) 231 #define PWM_OUT_INV (1 << 2U) 232 #define PWM_STOP_MODE (1 << 3U) 233 #define PWM_SW_FORCE_VAL (1 << 4U) 234 #define PWM_SW_MODE (1 << 5U) 235 #define PWM_STOP_EN (1 << 6U) 236 #define PWM_STS_TOP (1 << 7U) 237 238 /* 0xB4 : pwm4_interrupt */ 239 #define PWM_INT_PERIOD_CNT_SHIFT (0U) 240 #define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT) 241 #define PWM_INT_ENABLE (1 << 16U) 242 243 #endif /* __PWM_REG_H__ */ 244