1 /** 2 ****************************************************************************** 3 * @file pwm_reg.h 4 * @version V1.0 5 * @date 2022-08-15 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_PWM_V2_H__ 37 #define __HARDWARE_PWM_V2_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define PWM_INT_CONFIG_OFFSET (0x0) /* pwm_int_config */ 46 #define PWM_MC0_CONFIG0_OFFSET (0x40) /* pwm_mc0_config0 */ 47 #define PWM_MC0_CONFIG1_OFFSET (0x44) /* pwm_mc0_config1 */ 48 #define PWM_MC0_PERIOD_OFFSET (0x48) /* pwm_mc0_period */ 49 #define PWM_MC0_DEAD_TIME_OFFSET (0x4C) /* pwm_mc0_dead_time */ 50 #define PWM_MC0_CH0_THRE_OFFSET (0x50) /* pwm_mc0_ch0_thre */ 51 #define PWM_MC0_CH1_THRE_OFFSET (0x54) /* pwm_mc0_ch1_thre */ 52 #define PWM_MC0_CH2_THRE_OFFSET (0x58) /* pwm_mc0_ch2_thre */ 53 #define PWM_MC0_CH3_THRE_OFFSET (0x5C) /* pwm_mc0_ch3_thre */ 54 #define PWM_MC0_INT_STS_OFFSET (0x60) /* pwm_mc0_int_sts */ 55 #define PWM_MC0_INT_MASK_OFFSET (0x64) /* pwm_mc0_int_mask */ 56 #define PWM_MC0_INT_CLEAR_OFFSET (0x68) /* pwm_mc0_int_clear */ 57 #define PWM_MC0_INT_EN_OFFSET (0x6C) /* pwm_mc0_int_en */ 58 59 /* Register Bitfield definitions *****************************************************/ 60 61 /* 0x0 : pwm_int_config */ 62 #define PWM0_INT_STS (1 << 0U) 63 #define PWM1_INT_STS (1 << 1U) 64 #define PWM0_INT_CLR (1 << 8U) 65 #define PWM1_INT_CLR (1 << 9U) 66 67 /* 0x40 : pwm_mc0_config0 */ 68 #define PWM_CLK_DIV_SHIFT (0U) 69 #define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT) 70 #define PWM_STOP_ON_REPT (1 << 19U) 71 #define PWM_ADC_TRG_SRC_SHIFT (20U) 72 #define PWM_ADC_TRG_SRC_MASK (0xf << PWM_ADC_TRG_SRC_SHIFT) 73 #define PWM_SW_BREAK_EN (1 << 24U) 74 #define PWM_EXT_BREAK_EN (1 << 25U) 75 #define PWM_EXT_BREAK_PL (1 << 26U) 76 #define PWM_STOP_EN (1 << 27U) 77 #define PWM_STOP_MODE (1 << 28U) 78 #define PWM_STS_STOP (1 << 29U) 79 #define PWM_REG_CLK_SEL_SHIFT (30U) 80 #define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT) 81 82 /* 0x44 : pwm_mc0_config1 */ 83 #define PWM_CH0_PEN (1 << 0U) 84 #define PWM_CH0_PSI (1 << 1U) 85 #define PWM_CH0_NEN (1 << 2U) 86 #define PWM_CH0_NSI (1 << 3U) 87 #define PWM_CH1_PEN (1 << 4U) 88 #define PWM_CH1_PSI (1 << 5U) 89 #define PWM_CH1_NEN (1 << 6U) 90 #define PWM_CH1_NSI (1 << 7U) 91 #define PWM_CH2_PEN (1 << 8U) 92 #define PWM_CH2_PSI (1 << 9U) 93 #define PWM_CH2_NEN (1 << 10U) 94 #define PWM_CH2_NSI (1 << 11U) 95 #define PWM_CH3_PEN (1 << 12U) 96 #define PWM_CH3_PSI (1 << 13U) 97 #define PWM_CH3_NEN (1 << 14U) 98 #define PWM_CH3_NSI (1 << 15U) 99 #define PWM_CH0_PPL (1 << 16U) 100 #define PWM_CH0_NPL (1 << 17U) 101 #define PWM_CH1_PPL (1 << 18U) 102 #define PWM_CH1_NPL (1 << 19U) 103 #define PWM_CH2_PPL (1 << 20U) 104 #define PWM_CH2_NPL (1 << 21U) 105 #define PWM_CH3_PPL (1 << 22U) 106 #define PWM_CH3_NPL (1 << 23U) 107 #define PWM_CH0_PBS (1 << 24U) 108 #define PWM_CH0_NBS (1 << 25U) 109 #define PWM_CH1_PBS (1 << 26U) 110 #define PWM_CH1_NBS (1 << 27U) 111 #define PWM_CH2_PBS (1 << 28U) 112 #define PWM_CH2_NBS (1 << 29U) 113 #define PWM_CH3_PBS (1 << 30U) 114 #define PWM_CH3_NBS (1 << 31U) 115 116 /* 0x48 : pwm_mc0_period */ 117 #define PWM_PERIOD_SHIFT (0U) 118 #define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT) 119 #define PWM_INT_PERIOD_CNT_SHIFT (16U) 120 #define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT) 121 122 /* 0x4C : pwm_mc0_dead_time */ 123 #define PWM_CH0_DTG_SHIFT (0U) 124 #define PWM_CH0_DTG_MASK (0xff << PWM_CH0_DTG_SHIFT) 125 #define PWM_CH1_DTG_SHIFT (8U) 126 #define PWM_CH1_DTG_MASK (0xff << PWM_CH1_DTG_SHIFT) 127 #define PWM_CH2_DTG_SHIFT (16U) 128 #define PWM_CH2_DTG_MASK (0xff << PWM_CH2_DTG_SHIFT) 129 #define PWM_CH3_DTG_SHIFT (24U) 130 #define PWM_CH3_DTG_MASK (0xff << PWM_CH3_DTG_SHIFT) 131 132 /* 0x50 : pwm_mc0_ch0_thre */ 133 #define PWM_CH0_THREL_SHIFT (0U) 134 #define PWM_CH0_THREL_MASK (0xffff << PWM_CH0_THREL_SHIFT) 135 #define PWM_CH0_THREH_SHIFT (16U) 136 #define PWM_CH0_THREH_MASK (0xffff << PWM_CH0_THREH_SHIFT) 137 138 /* 0x54 : pwm_mc0_ch1_thre */ 139 #define PWM_CH1_THREL_SHIFT (0U) 140 #define PWM_CH1_THREL_MASK (0xffff << PWM_CH1_THREL_SHIFT) 141 #define PWM_CH1_THREH_SHIFT (16U) 142 #define PWM_CH1_THREH_MASK (0xffff << PWM_CH1_THREH_SHIFT) 143 144 /* 0x58 : pwm_mc0_ch2_thre */ 145 #define PWM_CH2_THREL_SHIFT (0U) 146 #define PWM_CH2_THREL_MASK (0xffff << PWM_CH2_THREL_SHIFT) 147 #define PWM_CH2_THREH_SHIFT (16U) 148 #define PWM_CH2_THREH_MASK (0xffff << PWM_CH2_THREH_SHIFT) 149 150 /* 0x5C : pwm_mc0_ch3_thre */ 151 #define PWM_CH3_THREL_SHIFT (0U) 152 #define PWM_CH3_THREL_MASK (0xffff << PWM_CH3_THREL_SHIFT) 153 #define PWM_CH3_THREH_SHIFT (16U) 154 #define PWM_CH3_THREH_MASK (0xffff << PWM_CH3_THREH_SHIFT) 155 156 /* 0x60 : pwm_mc0_int_sts */ 157 #define PWM_CH0L_INT (1 << 0U) 158 #define PWM_CH0H_INT (1 << 1U) 159 #define PWM_CH1L_INT (1 << 2U) 160 #define PWM_CH1H_INT (1 << 3U) 161 #define PWM_CH2L_INT (1 << 4U) 162 #define PWM_CH2H_INT (1 << 5U) 163 #define PWM_CH3L_INT (1 << 6U) 164 #define PWM_CH3H_INT (1 << 7U) 165 #define PWM_PRDE_INT (1 << 8U) 166 #define PWM_BRK_INT (1 << 9U) 167 #define PWM_REPT_INT (1 << 10U) 168 169 /* 0x64 : pwm_mc0_int_mask */ 170 #define PWM_CR_PWM_CH0L_MASK (1 << 0U) 171 #define PWM_CR_PWM_CH0H_MASK (1 << 1U) 172 #define PWM_CR_PWM_CH1L_MASK (1 << 2U) 173 #define PWM_CR_PWM_CH1H_MASK (1 << 3U) 174 #define PWM_CR_PWM_CH2L_MASK (1 << 4U) 175 #define PWM_CR_PWM_CH2H_MASK (1 << 5U) 176 #define PWM_CR_PWM_CH3L_MASK (1 << 6U) 177 #define PWM_CR_PWM_CH3H_MASK (1 << 7U) 178 #define PWM_CR_PWM_PRDE_MASK (1 << 8U) 179 #define PWM_CR_PWM_BRK_MASK (1 << 9U) 180 #define PWM_CR_PWM_REPT_MASK (1 << 10U) 181 182 /* 0x68 : pwm_mc0_int_clear */ 183 #define PWM_CR_PWM_CH0L_CLR (1 << 0U) 184 #define PWM_CR_PWM_CH0H_CLR (1 << 1U) 185 #define PWM_CR_PWM_CH1L_CLR (1 << 2U) 186 #define PWM_CR_PWM_CH1H_CLR (1 << 3U) 187 #define PWM_CR_PWM_CH2L_CLR (1 << 4U) 188 #define PWM_CR_PWM_CH2H_CLR (1 << 5U) 189 #define PWM_CR_PWM_CH3L_CLR (1 << 6U) 190 #define PWM_CR_PWM_CH3H_CLR (1 << 7U) 191 #define PWM_CR_PWM_PRDE_CLR (1 << 8U) 192 #define PWM_CR_PWM_BRK_CLR (1 << 9U) 193 #define PWM_CR_PWM_REPT_CLR (1 << 10U) 194 195 /* 0x6C : pwm_mc0_int_en */ 196 #define PWM_CR_PWM_CH0L_EN (1 << 0U) 197 #define PWM_CR_PWM_CH0H_EN (1 << 1U) 198 #define PWM_CR_PWM_CH1L_EN (1 << 2U) 199 #define PWM_CR_PWM_CH1H_EN (1 << 3U) 200 #define PWM_CR_PWM_CH2L_EN (1 << 4U) 201 #define PWM_CR_PWM_CH2H_EN (1 << 5U) 202 #define PWM_CR_PWM_CH3L_EN (1 << 6U) 203 #define PWM_CR_PWM_CH3H_EN (1 << 7U) 204 #define PWM_CR_PWM_PRDE_EN (1 << 8U) 205 #define PWM_CR_PWM_BRK_EN (1 << 9U) 206 #define PWM_CR_PWM_REPT_EN (1 << 10U) 207 208 #endif /* __HARDWARE_PWM_V2_H__ */ 209