1 /** 2 ****************************************************************************** 3 * @file rtc_reg.h 4 * @version V1.0 5 * @date 2022-08-05 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_RTC_H__ 37 #define __HARDWARE_RTC_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define HBN_CTL_OFFSET (0x0) /* HBN_CTL */ 46 #define HBN_TIME_L_OFFSET (0x4) /* HBN_TIME_L */ 47 #define HBN_TIME_H_OFFSET (0x8) /* HBN_TIME_H */ 48 #define HBN_RTC_TIME_L_OFFSET (0xC) /* RTC_TIME_L */ 49 #define HBN_RTC_TIME_H_OFFSET (0x10) /* RTC_TIME_H */ 50 51 /* Register Bitfield definitions *****************************************************/ 52 53 /* 0x0 : HBN_CTL */ 54 #define HBN_RTC_ENABLE (1 << 0U) 55 #define HBN_RTC_CTL_SHIFT (1U) 56 #if defined(BL602) || defined(BL702) 57 #define HBN_RTC_CTL_MASK (0x3f << HBN_RTC_CTL_SHIFT) 58 #define HBN_RTC_DLY_OPTION (1 << 24U) 59 #elif defined(BL808) || defined(BL606P) || defined(BL616) || defined(BL702L) || defined(BL628) 60 #define HBN_RTC_CTL_MASK (0x7 << HBN_RTC_CTL_SHIFT) 61 #define HBN_RTC_DLY_OPTION (1 << 4U) 62 #endif 63 #define HBN_RTC_BIT39_0_COMPARE (1 << HBN_RTC_CTL_SHIFT) 64 #define HBN_MODE (1 << 7U) 65 #define HBN_TRAP_MODE (1 << 8U) 66 #define HBN_PWRDN_HBN_CORE (1 << 9U) 67 #define HBN_PWRDN_HBN_RTC (1 << 11U) 68 #define HBN_SW_RST (1 << 12U) 69 #define HBN_DIS_PWR_OFF_LDO11 (1 << 13U) 70 #define HBN_DIS_PWR_OFF_LDO11_RT (1 << 14U) 71 #define HBN_LDO11_RT_VOUT_SEL_SHIFT (15U) 72 #define HBN_LDO11_RT_VOUT_SEL_MASK (0xf << HBN_LDO11_RT_VOUT_SEL_SHIFT) 73 #define HBN_LDO11_AON_VOUT_SEL_SHIFT (19U) 74 #define HBN_LDO11_AON_VOUT_SEL_MASK (0xf << HBN_LDO11_AON_VOUT_SEL_SHIFT) 75 #define HBN_PU_DCDC18_AON (1 << 23U) 76 #define HBN_PWR_ON_OPTION (1 << 25U) 77 #define HBN_SRAM_SLP_OPTION (1 << 26U) 78 #define HBN_SRAM_SLP (1 << 27U) 79 #define HBN_STATE_SHIFT (28U) 80 #define HBN_STATE_MASK (0xf << HBN_STATE_SHIFT) 81 82 /* 0x4 : HBN_TIME_L */ 83 #define HBN_TIME_L_SHIFT (0U) 84 #define HBN_TIME_L_MASK (0xffffffff << HBN_TIME_L_SHIFT) 85 86 /* 0x8 : HBN_TIME_H */ 87 #define HBN_TIME_H_SHIFT (0U) 88 #define HBN_TIME_H_MASK (0xff << HBN_TIME_H_SHIFT) 89 90 /* 0xC : RTC_TIME_L */ 91 #define HBN_RTC_TIME_LATCH_L_SHIFT (0U) 92 #define HBN_RTC_TIME_LATCH_L_MASK (0xffffffff << HBN_RTC_TIME_LATCH_L_SHIFT) 93 94 /* 0x10 : RTC_TIME_H */ 95 #define HBN_RTC_TIME_LATCH_H_SHIFT (0U) 96 #define HBN_RTC_TIME_LATCH_H_MASK (0xff << HBN_RTC_TIME_LATCH_H_SHIFT) 97 #define HBN_RTC_TIME_LATCH (1 << 31U) 98 99 #endif /* __HARDWARE_RTC_H__ */ 100