1 /** 2 ****************************************************************************** 3 * @file spi_reg.h 4 * @version V1.0 5 * @date 2022-06-20 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_SPI_H__ 37 #define __HARDWARE_SPI_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define SPI_CONFIG_OFFSET (0x0) /* spi_config */ 46 #define SPI_INT_STS_OFFSET (0x4) /* spi_int_sts */ 47 #define SPI_BUS_BUSY_OFFSET (0x8) /* spi_bus_busy */ 48 #define SPI_PRD_0_OFFSET (0x10) /* spi_prd_0 */ 49 #define SPI_PRD_1_OFFSET (0x14) /* spi_prd_1 */ 50 #define SPI_RXD_IGNR_OFFSET (0x18) /* spi_rxd_ignr */ 51 #define SPI_STO_VALUE_OFFSET (0x1C) /* spi_sto_value */ 52 #define SPI_FIFO_CONFIG_0_OFFSET (0x80) /* spi_fifo_config_0 */ 53 #define SPI_FIFO_CONFIG_1_OFFSET (0x84) /* spi_fifo_config_1 */ 54 #define SPI_FIFO_WDATA_OFFSET (0x88) /* spi_fifo_wdata */ 55 #define SPI_FIFO_RDATA_OFFSET (0x8C) /* spi_fifo_rdata */ 56 #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 57 #define SPI_BACKUP_IO_EN_OFFSET (0xFC) /* backup_io_en */ 58 #endif 59 /* Register Bitfield definitions *****************************************************/ 60 61 /* 0x0 : spi_config */ 62 #define SPI_CR_SPI_M_EN (1 << 0U) 63 #define SPI_CR_SPI_S_EN (1 << 1U) 64 #define SPI_CR_SPI_FRAME_SIZE_SHIFT (2U) 65 #define SPI_CR_SPI_FRAME_SIZE_MASK (0x3 << SPI_CR_SPI_FRAME_SIZE_SHIFT) 66 #define SPI_CR_SPI_SCLK_POL (1 << 4U) 67 #define SPI_CR_SPI_SCLK_PH (1 << 5U) 68 #define SPI_CR_SPI_BIT_INV (1 << 6U) 69 #define SPI_CR_SPI_BYTE_INV (1 << 7U) 70 #define SPI_CR_SPI_RXD_IGNR_EN (1 << 8U) 71 #define SPI_CR_SPI_M_CONT_EN (1 << 9U) 72 #define SPI_CR_SPI_S_3PIN_MODE (1 << 10U) 73 #define SPI_CR_SPI_DEG_EN (1 << 11U) 74 #define SPI_CR_SPI_DEG_CNT_SHIFT (12U) 75 #define SPI_CR_SPI_DEG_CNT_MASK (0xf << SPI_CR_SPI_DEG_CNT_SHIFT) 76 77 /* 0x4 : spi_int_sts */ 78 #define SPI_END_INT (1 << 0U) 79 #define SPI_TXF_INT (1 << 1U) 80 #define SPI_RXF_INT (1 << 2U) 81 #define SPI_STO_INT (1 << 3U) 82 #define SPI_TXU_INT (1 << 4U) 83 #define SPI_FER_INT (1 << 5U) 84 #define SPI_CR_SPI_END_MASK (1 << 8U) 85 #define SPI_CR_SPI_TXF_MASK (1 << 9U) 86 #define SPI_CR_SPI_RXF_MASK (1 << 10U) 87 #define SPI_CR_SPI_STO_MASK (1 << 11U) 88 #define SPI_CR_SPI_TXU_MASK (1 << 12U) 89 #define SPI_CR_SPI_FER_MASK (1 << 13U) 90 #define SPI_CR_SPI_END_CLR (1 << 16U) 91 #define SPI_CR_SPI_STO_CLR (1 << 19U) 92 #define SPI_CR_SPI_TXU_CLR (1 << 20U) 93 #define SPI_CR_SPI_END_EN (1 << 24U) 94 #define SPI_CR_SPI_TXF_EN (1 << 25U) 95 #define SPI_CR_SPI_RXF_EN (1 << 26U) 96 #define SPI_CR_SPI_STO_EN (1 << 27U) 97 #define SPI_CR_SPI_TXU_EN (1 << 28U) 98 #define SPI_CR_SPI_FER_EN (1 << 29U) 99 100 /* 0x8 : spi_bus_busy */ 101 #define SPI_STS_SPI_BUS_BUSY (1 << 0U) 102 103 /* 0x10 : spi_prd_0 */ 104 #define SPI_CR_SPI_PRD_S_SHIFT (0U) 105 #define SPI_CR_SPI_PRD_S_MASK (0xff << SPI_CR_SPI_PRD_S_SHIFT) 106 #define SPI_CR_SPI_PRD_P_SHIFT (8U) 107 #define SPI_CR_SPI_PRD_P_MASK (0xff << SPI_CR_SPI_PRD_P_SHIFT) 108 #define SPI_CR_SPI_PRD_D_PH_0_SHIFT (16U) 109 #define SPI_CR_SPI_PRD_D_PH_0_MASK (0xff << SPI_CR_SPI_PRD_D_PH_0_SHIFT) 110 #define SPI_CR_SPI_PRD_D_PH_1_SHIFT (24U) 111 #define SPI_CR_SPI_PRD_D_PH_1_MASK (0xff << SPI_CR_SPI_PRD_D_PH_1_SHIFT) 112 113 /* 0x14 : spi_prd_1 */ 114 #define SPI_CR_SPI_PRD_I_SHIFT (0U) 115 #define SPI_CR_SPI_PRD_I_MASK (0xff << SPI_CR_SPI_PRD_I_SHIFT) 116 117 /* 0x18 : spi_rxd_ignr */ 118 #define SPI_CR_SPI_RXD_IGNR_P_SHIFT (0U) 119 #define SPI_CR_SPI_RXD_IGNR_P_MASK (0x1f << SPI_CR_SPI_RXD_IGNR_P_SHIFT) 120 #define SPI_CR_SPI_RXD_IGNR_S_SHIFT (16U) 121 #define SPI_CR_SPI_RXD_IGNR_S_MASK (0x1f << SPI_CR_SPI_RXD_IGNR_S_SHIFT) 122 123 /* 0x1C : spi_sto_value */ 124 #define SPI_CR_SPI_STO_VALUE_SHIFT (0U) 125 #define SPI_CR_SPI_STO_VALUE_MASK (0xfff << SPI_CR_SPI_STO_VALUE_SHIFT) 126 127 /* 0x80 : spi_fifo_config_0 */ 128 #define SPI_DMA_TX_EN (1 << 0U) 129 #define SPI_DMA_RX_EN (1 << 1U) 130 #define SPI_TX_FIFO_CLR (1 << 2U) 131 #define SPI_RX_FIFO_CLR (1 << 3U) 132 #define SPI_TX_FIFO_OVERFLOW (1 << 4U) 133 #define SPI_TX_FIFO_UNDERFLOW (1 << 5U) 134 #define SPI_RX_FIFO_OVERFLOW (1 << 6U) 135 #define SPI_RX_FIFO_UNDERFLOW (1 << 7U) 136 137 /* 0x84 : spi_fifo_config_1 */ 138 #define SPI_TX_FIFO_CNT_SHIFT (0U) 139 #if defined(BL702) || defined(BL602) 140 #define SPI_TX_FIFO_CNT_MASK (0x7 << SPI_TX_FIFO_CNT_SHIFT) 141 #elif defined(BL702L) 142 #define SPI_TX_FIFO_CNT_MASK (0x1f << SPI_TX_FIFO_CNT_SHIFT) 143 #elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 144 #define SPI_TX_FIFO_CNT_MASK (0x3f << SPI_TX_FIFO_CNT_SHIFT) 145 #endif 146 #define SPI_RX_FIFO_CNT_SHIFT (8U) 147 #if defined(BL702) || defined(BL602) 148 #define SPI_RX_FIFO_CNT_MASK (0x7 << SPI_RX_FIFO_CNT_SHIFT) 149 #elif defined(BL702L) 150 #define SPI_RX_FIFO_CNT_MASK (0x1f << SPI_RX_FIFO_CNT_SHIFT) 151 #elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 152 #define SPI_RX_FIFO_CNT_MASK (0x3f << SPI_RX_FIFO_CNT_SHIFT) 153 #endif 154 #define SPI_TX_FIFO_TH_SHIFT (16U) 155 #if defined(BL702) || defined(BL602) 156 #define SPI_TX_FIFO_TH_MASK (0x3 << SPI_TX_FIFO_TH_SHIFT) 157 #elif defined(BL702L) 158 #define SPI_TX_FIFO_TH_MASK (0xf << SPI_TX_FIFO_TH_SHIFT) 159 #elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 160 #define SPI_TX_FIFO_TH_MASK (0x1f << SPI_TX_FIFO_TH_SHIFT) 161 #endif 162 #define SPI_RX_FIFO_TH_SHIFT (24U) 163 #if defined(BL702) || defined(BL602) 164 #define SPI_RX_FIFO_TH_MASK (0x3 << SPI_RX_FIFO_TH_SHIFT) 165 #elif defined(BL702L) 166 #define SPI_RX_FIFO_TH_MASK (0xf << SPI_RX_FIFO_TH_SHIFT) 167 #elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 168 #define SPI_RX_FIFO_TH_MASK (0x1f << SPI_RX_FIFO_TH_SHIFT) 169 #endif 170 171 /* 0x88 : spi_fifo_wdata */ 172 #define SPI_FIFO_WDATA_SHIFT (0U) 173 #define SPI_FIFO_WDATA_MASK (0xffffffff << SPI_FIFO_WDATA_SHIFT) 174 175 /* 0x8C : spi_fifo_rdata */ 176 #define SPI_FIFO_RDATA_SHIFT (0U) 177 #define SPI_FIFO_RDATA_MASK (0xffffffff << SPI_FIFO_RDATA_SHIFT) 178 179 #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 180 /* 0xFC : backup_io_en */ 181 #define SPI_BACKUP_IO_EN (1 << 0U) 182 #endif 183 184 #endif /* __HARDWARE_SPI_H__ */ 185