1 /******************************************************************************* 2 * Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. 3 * 4 * This software is owned and published by: 5 * Huada Semiconductor Co.,Ltd ("HDSC"). 6 * 7 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 8 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. 9 * 10 * This software contains source code for use with HDSC 11 * components. This software is licensed by HDSC to be adapted only 12 * for use in systems utilizing HDSC components. HDSC shall not be 13 * responsible for misuse or illegal use of this software for devices not 14 * supported herein. HDSC is providing this software "AS IS" and will 15 * not be responsible for issues arising from incorrect user implementation 16 * of the software. 17 * 18 * Disclaimer: 19 * HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, 20 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 21 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 22 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 23 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 24 * WARRANTY OF NONINFRINGEMENT. 25 * HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 26 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 27 * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 28 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 29 * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 31 * SAVINGS OR PROFITS, 32 * EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 33 * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR 34 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 35 * FROM, THE SOFTWARE. 36 * 37 * This software may be replicated in part or whole for the licensed use, 38 * with the restriction that this Disclaimer and Copyright notice must be 39 * included with each copy of this software, whether used in part or whole, 40 * at all times. 41 */ 42 /******************************************************************************/ 43 /** \file sysctrl.h 44 ** 45 ** Headerfile for SYSCTRL functions 46 ** @link SYSCTRL Group Some description @endlink 47 ** 48 ** History: 49 ** - 2018-04-15 Lux First Version 50 ** 51 ******************************************************************************/ 52 53 #ifndef __SYSCTRL_H__ 54 #define __SYSCTRL_H__ 55 56 /******************************************************************************* 57 * Include files 58 ******************************************************************************/ 59 #include "hc32l196_ddl.h" 60 61 62 #ifdef __cplusplus 63 extern "C" 64 { 65 #endif 66 67 /** 68 ****************************************************************************** 69 ** \defgroup SysCtrlGroup (SYSCTRL) 70 ** 71 ******************************************************************************/ 72 //@{ 73 74 /** 75 ******************************************************************************* 76 ** function prototypes. 77 ******************************************************************************/ 78 79 /****************************************************************************** 80 * Global type definitions 81 ******************************************************************************/ 82 83 /** 84 ******************************************************************************* 85 ** \brief 系统时钟输入源类型定义 86 ** \note 87 ******************************************************************************/ 88 typedef enum en_sysctrl_clk_source 89 { 90 SysctrlClkRCH = 0u, ///< 内部高速时钟 91 SysctrlClkXTH = 1u, ///< 外部高速时钟 92 SysctrlClkRCL = 2u, ///< 内部低速时钟 93 SysctrlClkXTL = 3u, ///< 外部低速时钟 94 SysctrlClkPLL = 4u, ///< PLL时钟 95 }en_sysctrl_clk_source_t; 96 97 /** 98 ******************************************************************************* 99 ** \brief RCH频率值枚举类型定义 100 ******************************************************************************/ 101 typedef enum en_sysctrl_rch_freq 102 { 103 SysctrlRchFreq4MHz = 4u, ///< 4MHz 104 SysctrlRchFreq8MHz = 3u, ///< 8MHz 105 SysctrlRchFreq16MHz = 2u, ///< 16MHz 106 SysctrlRchFreq22_12MHz = 1u, ///< 22.12MHz 107 SysctrlRchFreq24MHz = 0u, ///< 24MHz 108 }en_sysctrl_rch_freq_t; 109 110 /** 111 ******************************************************************************* 112 ** \brief XTAL驱动能力类型定义 113 ******************************************************************************/ 114 typedef enum en_sysctrl_xtal_driver 115 { 116 SysctrlXtalDriver0 = 0u, ///< 最弱驱动能力 117 SysctrlXtalDriver1 = 1u, ///< 弱驱动能力 118 SysctrlXtalDriver2 = 2u, ///< 一般驱动能力 119 SysctrlXtalDriver3 = 3u, ///< 最强驱动能力 120 }en_sysctrl_xtal_driver_t; 121 122 /** 123 ******************************************************************************* 124 ** \brief XTH频率值范围选择类型定义 125 ******************************************************************************/ 126 typedef enum en_sysctrl_xth_freq 127 { 128 SysctrlXthFreq4_8MHz = 0u, ///< 4~8MHz 129 SysctrlXthFreq8_16MHz = 1u, ///< 8~16MHz 130 SysctrlXthFreq16_24MHz = 2u, ///< 16~24MHz 131 SysctrlXthFreq24_32MHz = 3u, ///< 24~32MHz 132 }en_sysctrl_xth_freq_t; 133 134 /** 135 ******************************************************************************* 136 ** \brief XTH时钟稳定周期数类型定义 137 ******************************************************************************/ 138 typedef enum en_sysctrl_xth_cycle 139 { 140 SysctrlXthStableCycle256 = 0u, ///< 256 个周期数 141 SysctrlXthStableCycle1024 = 1u, ///< 1024 个周期数 142 SysctrlXthStableCycle4096 = 2u, ///< 4096 个周期数 143 SysctrlXthStableCycle16384 = 3u, ///< 16384 个周期数 144 }en_sysctrl_xth_cycle_t; 145 146 /** 147 ******************************************************************************* 148 ** \brief RCL频率值枚举类型定义 149 ******************************************************************************/ 150 typedef enum en_sysctrl_rcl_freq 151 { 152 SysctrlRclFreq32768 = 0x11u, ///< 32.768KHz 153 SysctrlRclFreq38400 = 0x10u, ///< 38.4KHz 154 }en_sysctrl_rcl_freq_t; 155 156 /** 157 ******************************************************************************* 158 ** \brief RCL时钟稳定周期数类型定义 159 ******************************************************************************/ 160 typedef enum en_sysctrl_rcl_cycle 161 { 162 SysctrlRclStableCycle4 = 0u, ///< 4 个周期数 163 SysctrlRclStableCycle16 = 1u, ///< 16 个周期数 164 SysctrlRclStableCycle64 = 2u, ///< 64 个周期数 165 SysctrlRclStableCycle256 = 3u, ///< 256 个周期数 166 }en_sysctrl_rcl_cycle_t; 167 168 /** 169 ******************************************************************************* 170 ** \brief XTL时钟稳定周期数类型定义 171 ******************************************************************************/ 172 typedef enum en_sysctrl_xtl_cycle 173 { 174 SysctrlXtlStableCycle256 = 0u, ///< 256 个周期数 175 SysctrlXtlStableCycle1024 = 1u, ///< 1024 个周期数 176 SysctrlXtlStableCycle4096 = 2u, ///< 4096 个周期数 177 SysctrlXtlStableCycle16384 = 3u, ///< 16384 个周期数 178 }en_sysctrl_xtl_cycle_t; 179 180 /** 181 ******************************************************************************* 182 ** \brief XTL晶体振幅枚举类型定义 183 ******************************************************************************/ 184 typedef enum en_sysctrl_xtl_amp 185 { 186 SysctrlXtlAmp0 = 0u, ///< 最小振幅 187 SysctrlXtlAmp1 = 1u, ///< 小振幅 188 SysctrlXtlAmp2 = 2u, ///< 一般振幅 189 SysctrlXtlAmp3 = 3u, ///< 最大振幅 190 }en_sysctrl_xtl_amp_t; 191 192 /** 193 ******************************************************************************* 194 ** \brief PLL时钟稳定周期数类型定义 195 ******************************************************************************/ 196 typedef enum en_sysctrl_pll_cycle 197 { 198 SysctrlPllStableCycle128 = 0u, ///< 128个周期数 199 SysctrlPllStableCycle256 = 1u, ///< 256个周期数 200 SysctrlPllStableCycle512 = 2u, ///< 512个周期数 201 SysctrlPllStableCycle1024 = 3u, ///< 1024个周期数 202 SysctrlPllStableCycle2048 = 4u, ///< 2048个周期数 203 SysctrlPllStableCycle4096 = 5u, ///< 4096个周期数 204 SysctrlPllStableCycle8192 = 6u, ///< 8192个周期数 205 SysctrlPllStableCycle16384 = 7u, ///< 16384个周期数 206 }en_sysctrl_pll_cycle_t; 207 208 /** 209 ******************************************************************************* 210 ** \brief PLL输入频率范围类型定义 211 ******************************************************************************/ 212 typedef enum en_sysctrl_pll_infreq 213 { 214 SysctrlPllInFreq4_6MHz = 0u, ///< 4~16MHz 215 SysctrlPllInFreq6_12MHz = 1u, ///< 6~12MHz 216 SysctrlPllInFreq12_20MHz = 2u, ///< 12~20MHz 217 SysctrlPllInFreq20_24MHz = 3u, ///< 20~24MHz 218 }en_sysctrl_pll_infreq_t; 219 220 /** 221 ******************************************************************************* 222 ** \brief PLL输出频率范围类型定义 223 ******************************************************************************/ 224 typedef enum en_sysctrl_pll_outfreq 225 { 226 SysctrlPllOutFreq8_12MHz = 0u, ///< 8~12MHz 227 SysctrlPllOutFreq12_18MHz = 1u, ///< 12~18MHz 228 SysctrlPllOutFreq18_24MHz = 2u, ///< 18~24MHz 229 SysctrlPllOutFreq24_36MHz = 3u, ///< 24~36MHz 230 SysctrlPllOutFreq36_48MHz = 4u, ///< 36~48MHz 231 }en_sysctrl_pll_outfreq_t; 232 233 /** 234 ******************************************************************************* 235 ** \brief PLL输入时钟源类型定义 236 ******************************************************************************/ 237 typedef enum en_sysctrl_pll_clksource 238 { 239 SysctrlPllXthXtal = 0u, ///< XTH晶振输入的时钟 240 SysctrlPllXthIn = 2u, ///< XTH从端口输入的时钟 241 SysctrlPllRch = 3u, ///< RCH时钟 242 }en_sysctrl_pll_clksource_t; 243 244 /** 245 ******************************************************************************* 246 ** \brief PLL输入时钟源类型定义 247 ******************************************************************************/ 248 typedef enum en_sysctrl_pll_mul 249 { 250 SysctrlPllMul2 = 2u, ///< 2倍频 251 SysctrlPllMul3 = 3u, ///< 3倍频 252 SysctrlPllMul4 = 4u, ///< 4倍频 253 SysctrlPllMul5 = 5u, ///< 5倍频 254 SysctrlPllMul6 = 6u, ///< 6倍频 255 SysctrlPllMul7 = 7u, ///< 7倍频 256 SysctrlPllMul8 = 8u, ///< 8倍频 257 SysctrlPllMul9 = 9u, ///< 9倍频 258 SysctrlPllMul10 = 10u, ///< 10倍频 259 SysctrlPllMul11 = 11u, ///< 11倍频 260 SysctrlPllMul12 = 12u, ///< 12倍频 261 }en_sysctrl_pll_mul_t; 262 263 /** 264 ******************************************************************************* 265 ** \brief HCLK时钟分频系数类型定义 266 ******************************************************************************/ 267 typedef enum en_sysctrl_hclk_div 268 { 269 SysctrlHclkDiv1 = 0u, ///< SystemClk 270 SysctrlHclkDiv2 = 1u, ///< SystemClk/2 271 SysctrlHclkDiv4 = 2u, ///< SystemClk/4 272 SysctrlHclkDiv8 = 3u, ///< SystemClk/8 273 SysctrlHclkDiv16 = 4u, ///< SystemClk/16 274 SysctrlHclkDiv32 = 5u, ///< SystemClk/32 275 SysctrlHclkDiv64 = 6u, ///< SystemClk/64 276 SysctrlHclkDiv128 = 7u, ///< SystemClk/128 277 }en_sysctrl_hclk_div_t; 278 279 /** 280 ******************************************************************************* 281 ** \brief PCLK分频系数 282 ******************************************************************************/ 283 typedef enum en_sysctrl_pclk_div 284 { 285 SysctrlPclkDiv1 = 0u, ///< HCLK 286 SysctrlPclkDiv2 = 1u, ///< HCLK/2 287 SysctrlPclkDiv4 = 2u, ///< HCLK/4 288 SysctrlPclkDiv8 = 3u, ///< HCLK/8 289 }en_sysctrl_pclk_div_t; 290 291 /** 292 ******************************************************************************* 293 ** \brief RTC高速时钟补偿时钟频率数据类型定义 294 ******************************************************************************/ 295 typedef enum en_sysctrl_rtc_adjust 296 { 297 SysctrlRTC4MHz = 0u, ///< 4MHz 298 SysctrlRTC6MHz = 1u, ///< 6MHz 299 SysctrlRTC8MHz = 2u, ///< 8MHz 300 SysctrlRTC12MHz = 3u, ///< 12MHz 301 SysctrlRTC16MHz = 4u, ///< 16MHz 302 SysctrlRTC20MHz = 5u, ///< 20MHz 303 SysctrlRTC24MHz = 6u, ///< 24MHz 304 SysctrlRTC32MHz = 7u, ///< 32MHz 305 }en_sysctrl_rtc_adjust_t; 306 307 /** 308 ******************************************************************************* 309 ** \brief 系统控制模块其他功能数据类型定义 310 ******************************************************************************/ 311 typedef enum en_sysctrl_func 312 { 313 SysctrlEXTHEn = 1u, ///< 使能外部高速时钟从输入引脚输入 314 SysctrlEXTLEn = 2u, ///< 使能外部低速速时钟从输入引脚输入 315 SysctrlXTLAlwaysOnEn = 3u, ///< 使能后XTL_EN只可置位 316 SysctrlClkFuncRTCLpmEn = 5u, ///< 使能RTC低功耗模式 317 SysctrlCMLockUpEn = 6u, ///< 使能后CPU执行无效指令会复位MCU 318 SysctrlSWDUseIOEn = 8u, ///< SWD端口设为IO功能 319 }en_sysctrl_func_t; 320 321 /** 322 ******************************************************************************* 323 ** \brief 外设时钟门控开关类型枚举 324 ******************************************************************************/ 325 typedef enum en_sysctrl_peripheral_gate 326 { 327 SysctrlPeripheralUart0 = 0u, ///< 串口0 328 SysctrlPeripheralUart1 = 1u, ///< 串口1 329 SysctrlPeripheralLpUart0 = 2u, ///< 低功耗串口0 330 SysctrlPeripheralLpUart1 = 3u, ///< 低功耗串口1 331 SysctrlPeripheralI2c0 = 4u, ///< I2C0 332 SysctrlPeripheralI2c1 = 5u, ///< I2C1 333 SysctrlPeripheralSpi0 = 6u, ///< SPI0 334 SysctrlPeripheralSpi1 = 7u, ///< SPI1 335 SysctrlPeripheralBaseTim = 8u, ///< 基础定时器TIM0/1/2 336 SysctrlPeripheralLpTim0 = 9u, ///< 低功耗定时器0 337 SysctrlPeripheralAdvTim = 10u, ///< 高级定时器TIM4/5/6 338 SysctrlPeripheralTim3 = 11u, ///< 定时器3 339 SysctrlPeripheralOpa = 13u, ///< OPA 340 SysctrlPeripheralPca = 14u, ///< 可编程计数阵列 341 SysctrlPeripheralWdt = 15u, ///< 看门狗 342 SysctrlPeripheralAdcBgr = 16u, ///< ADC&BGR 343 SysctrlPeripheralVcLvd = 17u, ///< VC和LVD 344 SysctrlPeripheralRng = 18u, ///< RNG 345 SysctrlPeripheralPcnt = 19u, ///< PCNT 346 SysctrlPeripheralRtc = 20u, ///< RTC 347 SysctrlPeripheralTrim = 21u, ///< 时钟校准 348 SysctrlPeripheralLcd = 22u, ///< LCD 349 SysctrlPeripheralTick = 24u, ///< 系统定时器 350 SysctrlPeripheralSwd = 25u, ///< SWD 351 SysctrlPeripheralCrc = 26u, ///< CRC 352 SysctrlPeripheralAes = 27u, ///< AES 353 SysctrlPeripheralGpio = 28u, ///< GPIO 354 SysctrlPeripheralDma = 29u, ///< DMA 355 SysctrlPeripheralFlash = 31u, ///< Flash 356 SysctrlPeripheralDac = 35u, ///< DAC 357 SysctrlPeripheralLpTim1 = 36u, ///< 低功耗定时器1 358 SysctrlPeripheralUart2 = 40u, ///< UART2 359 SysctrlPeripheralUart3 = 41u, ///< UART3 360 }en_sysctrl_peripheral_gate_t; 361 362 /** 363 ******************************************************************************* 364 ** \brief 时钟初始化配置结构体定义 365 ******************************************************************************/ 366 typedef struct 367 { 368 en_sysctrl_clk_source_t enClkSrc; ///< 时钟源选择 369 en_sysctrl_hclk_div_t enHClkDiv; ///< HCLK分频系数 370 en_sysctrl_pclk_div_t enPClkDiv; ///< PCLK分频系数 371 }stc_sysctrl_clk_cfg_t; 372 373 /** 374 ******************************************************************************* 375 ** \brief 时钟初始化配置结构体定义 376 ******************************************************************************/ 377 typedef struct 378 { 379 en_sysctrl_pll_infreq_t enInFreq; ///< PLL输入时钟频率范围选择 380 en_sysctrl_pll_outfreq_t enOutFreq; ///< PLL输出时钟频率范围选择 381 en_sysctrl_pll_clksource_t enPllClkSrc; ///< PLL输入时钟源选择 382 en_sysctrl_pll_mul_t enPllMul; ///< PLL倍频系数选择 383 }stc_sysctrl_pll_cfg_t; 384 385 /****************************************************************************** 386 * Global variable declarations ('extern', definition in C source) 387 ******************************************************************************/ 388 389 /****************************************************************************** 390 * Global function prototypes (definition in C source) 391 ******************************************************************************/ 392 ///< 系统时钟初始化API:用于上电后，系统工作之前对主频及外设时钟进行初始化； 393 ///< 注意1：使用该初始化函数前需要根据系统，必须优先设置目标内部时钟源的TRIM值或外部时钟源的频率范围， 394 ///< 注意2：XTH、XTL的频率范围设定，需要根据外部晶振决定， 395 ///< 注意3：本驱动默认宏定义：SYSTEM_XTH=32MHz,SYSTEM_XTL=32768Hz,如使用其它外部晶振，必须修改这两个宏定义的值。 396 en_result_t Sysctrl_ClkInit(stc_sysctrl_clk_cfg_t *pstcCfg); 397 398 ///< 系统时钟去初始化API:恢复为上电默认状态->PCLK=HCLK=SystemClk=RCH4MHz 399 en_result_t Sysctrl_ClkDeInit(void); 400 401 ///< 系统时钟模块的基本功能设置 402 ///< 注意：使能需要使用的时钟源之前，必须优先设置目标内部时钟源的TRIM值或外部时钟源的频率范围 403 en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag); 404 405 ///<外部晶振驱动配置：系统初始化Sysctrl_ClkInit()之后，可根据需要配置外部晶振的驱动能力，时钟初始化Sysctrl_ClkInit()默认为最大值; 406 en_result_t Sysctrl_XTHDriverCfg(en_sysctrl_xtal_driver_t enDriver); 407 en_result_t Sysctrl_XTLDriverCfg(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver); 408 409 ///<时钟稳定周期设置:系统初始化Sysctrl_ClkInit()之后，可根据需要配置时钟开启后的稳定之间，默认为最大值; 410 en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle); 411 en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle); 412 en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle); 413 en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle); 414 415 ///<系统时钟源切换并更新系统时钟：如果需要在系统时钟初始化Sysctrl_ClkInit()之后切换主频时钟源，则使用该函数； 416 ///< 时钟切换前后，必须根据目标频率值设置Flash读等待周期，可配置插入周期为0、1、2， 417 ///< 注意!!!：当HCLK大于24MHz时，FLASH等待周期插入必须至少为1,否则程序运行可能产生未知错误 418 en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource); 419 420 ///< 时钟源频率设定：根据系统情况，单独设置不同时钟源的频率值; 421 ///< 时钟频率设置前，必须根据目标频率值设置Flash读等待周期，可配置插入周期为0、1、2， 422 ///< 其中XTL的时钟由外部晶振决定，无需设置。 423 en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq); 424 en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq); 425 en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq); 426 en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_cfg_t *pstcPLLCfg); 427 428 ///< 时钟分频设置:根据系统情况，单独设置HCLK、PCLK的分配值; 429 en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv); 430 en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv); 431 432 ///< 时钟频率获取：根据系统需要，获取当前HCLK及PCLK的频率值 433 uint32_t Sysctrl_GetHClkFreq(void); 434 uint32_t Sysctrl_GetPClkFreq(void); 435 436 ///< 外设门控开关/状态获取：用于控制外设模块的使能，使用该模块的功能之前，必须使能该模块的门控时钟； 437 en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag); 438 boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral); 439 440 ///< 系统功能配置：用于设置其他系统相关特殊功能； 441 en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag); 442 443 ///< RTC高速时钟补偿:用于设置RTC高速时钟下的频率补偿 444 en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj); 445 446 //@} // Sysctrl Group 447 448 #ifdef __cplusplus 449 #endif 450 451 #endif /* __SYSCTRL_H__ */ 452 /******************************************************************************* 453 * EOF (not truncated) 454 ******************************************************************************/ 455 456 457