1 /** 2 ****************************************************************************** 3 * @file hk32f0xx_spi.h 4 * @version V1.0.1 5 * @date 2019-08-15 6 ****************************************************************************** 7 */ 8 9 /* Define to prevent recursive inclusion -------------------------------------*/ 10 #ifndef __HK32F0XX_SPI_H 11 #define __HK32F0XX_SPI_H 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /* Includes ------------------------------------------------------------------*/ 18 #include "hk32f0xx.h" 19 20 /** @addtogroup HK32F0xx_StdPeriph_Driver 21 * @{ 22 */ 23 24 /** @addtogroup SPI 25 * @{ 26 */ 27 28 /* Exported types ------------------------------------------------------------*/ 29 30 /** 31 * @brief SPI Init structure definition 32 */ 33 34 typedef struct 35 { 36 uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. 37 This parameter can be a value of @ref SPI_data_direction */ 38 39 uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). 40 This parameter can be a value of @ref SPI_mode */ 41 42 uint16_t SPI_DataSize; /*!< Specifies the SPI data size. 43 This parameter can be a value of @ref SPI_data_size */ 44 45 uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. 46 This parameter can be a value of @ref SPI_Clock_Polarity */ 47 48 uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. 49 This parameter can be a value of @ref SPI_Clock_Phase */ 50 51 uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by 52 hardware (NSS pin) or by software using the SSI bit. 53 This parameter can be a value of @ref SPI_Slave_Select_management */ 54 55 uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 56 used to configure the transmit and receive SCK clock. 57 This parameter can be a value of @ref SPI_BaudRate_Prescaler 58 @note The communication clock is derived from the master 59 clock. The slave clock does not need to be set. */ 60 61 uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 62 This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 63 64 uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ 65 }SPI_InitTypeDef; 66 67 68 /** 69 * @brief I2S Init structure definition 70 * @note These parameters are not available for HK32F030 devices. 71 */ 72 73 typedef struct 74 { 75 uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. 76 This parameter can be a value of @ref SPI_I2S_Mode */ 77 78 uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. 79 This parameter can be a value of @ref SPI_I2S_Standard */ 80 81 uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. 82 This parameter can be a value of @ref SPI_I2S_Data_Format */ 83 84 uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 85 This parameter can be a value of @ref SPI_I2S_MCLK_Output */ 86 87 uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. 88 This parameter can be a value of @ref SPI_I2S_Audio_Frequency */ 89 90 uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. 91 This parameter can be a value of @ref SPI_I2S_Clock_Polarity */ 92 }I2S_InitTypeDef; 93 94 /* Exported constants --------------------------------------------------------*/ 95 96 /** @defgroup SPI_Exported_Constants 97 * @{ 98 */ 99 100 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ 101 ((PERIPH) == SPI2)) 102 103 #define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1)) 104 105 /** @defgroup SPI_data_direction 106 * @{ 107 */ 108 109 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) 110 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) 111 #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) 112 #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) 113 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ 114 ((MODE) == SPI_Direction_2Lines_RxOnly) || \ 115 ((MODE) == SPI_Direction_1Line_Rx) || \ 116 ((MODE) == SPI_Direction_1Line_Tx)) 117 /** 118 * @} 119 */ 120 121 /** @defgroup SPI_mode 122 * @{ 123 */ 124 125 #define SPI_Mode_Master ((uint16_t)0x0104) 126 #define SPI_Mode_Slave ((uint16_t)0x0000) 127 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ 128 ((MODE) == SPI_Mode_Slave)) 129 /** 130 * @} 131 */ 132 133 /** @defgroup SPI_data_size 134 * @{ 135 */ 136 137 #define SPI_DataSize_4b ((uint16_t)0x0300) 138 #define SPI_DataSize_5b ((uint16_t)0x0400) 139 #define SPI_DataSize_6b ((uint16_t)0x0500) 140 #define SPI_DataSize_7b ((uint16_t)0x0600) 141 #define SPI_DataSize_8b ((uint16_t)0x0700) 142 #define SPI_DataSize_9b ((uint16_t)0x0800) 143 #define SPI_DataSize_10b ((uint16_t)0x0900) 144 #define SPI_DataSize_11b ((uint16_t)0x0A00) 145 #define SPI_DataSize_12b ((uint16_t)0x0B00) 146 #define SPI_DataSize_13b ((uint16_t)0x0C00) 147 #define SPI_DataSize_14b ((uint16_t)0x0D00) 148 #define SPI_DataSize_15b ((uint16_t)0x0E00) 149 #define SPI_DataSize_16b ((uint16_t)0x0F00) 150 #define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \ 151 ((SIZE) == SPI_DataSize_5b) || \ 152 ((SIZE) == SPI_DataSize_6b) || \ 153 ((SIZE) == SPI_DataSize_7b) || \ 154 ((SIZE) == SPI_DataSize_8b) || \ 155 ((SIZE) == SPI_DataSize_9b) || \ 156 ((SIZE) == SPI_DataSize_10b) || \ 157 ((SIZE) == SPI_DataSize_11b) || \ 158 ((SIZE) == SPI_DataSize_12b) || \ 159 ((SIZE) == SPI_DataSize_13b) || \ 160 ((SIZE) == SPI_DataSize_14b) || \ 161 ((SIZE) == SPI_DataSize_15b) || \ 162 ((SIZE) == SPI_DataSize_16b)) 163 /** 164 * @} 165 */ 166 167 /** @defgroup SPI_CRC_length 168 * @{ 169 */ 170 171 #define SPI_CRCLength_8b ((uint16_t)0x0000) 172 #define SPI_CRCLength_16b SPI_CR1_CRCL 173 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \ 174 ((LENGTH) == SPI_CRCLength_16b)) 175 /** 176 * @} 177 */ 178 179 /** @defgroup SPI_Clock_Polarity 180 * @{ 181 */ 182 183 #define SPI_CPOL_Low ((uint16_t)0x0000) 184 #define SPI_CPOL_High SPI_CR1_CPOL 185 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ 186 ((CPOL) == SPI_CPOL_High)) 187 /** 188 * @} 189 */ 190 191 /** @defgroup SPI_Clock_Phase 192 * @{ 193 */ 194 195 #define SPI_CPHA_1Edge ((uint16_t)0x0000) 196 #define SPI_CPHA_2Edge SPI_CR1_CPHA 197 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ 198 ((CPHA) == SPI_CPHA_2Edge)) 199 /** 200 * @} 201 */ 202 203 /** @defgroup SPI_Slave_Select_management 204 * @{ 205 */ 206 207 #define SPI_NSS_Soft SPI_CR1_SSM 208 #define SPI_NSS_Hard ((uint16_t)0x0000) 209 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ 210 ((NSS) == SPI_NSS_Hard)) 211 /** 212 * @} 213 */ 214 215 /** @defgroup SPI_BaudRate_Prescaler 216 * @{ 217 */ 218 219 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) 220 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) 221 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) 222 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) 223 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 224 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) 225 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) 226 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) 227 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ 228 ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ 229 ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ 230 ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ 231 ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ 232 ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ 233 ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ 234 ((PRESCALER) == SPI_BaudRatePrescaler_256)) 235 /** 236 * @} 237 */ 238 239 /** @defgroup SPI_MSB_LSB_transmission 240 * @{ 241 */ 242 243 #define SPI_FirstBit_MSB ((uint16_t)0x0000) 244 #define SPI_FirstBit_LSB SPI_CR1_LSBFIRST 245 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ 246 ((BIT) == SPI_FirstBit_LSB)) 247 /** 248 * @} 249 */ 250 251 /** @defgroup SPI_I2S_Mode 252 * @{ 253 */ 254 255 #define I2S_Mode_SlaveTx ((uint16_t)0x0000) 256 #define I2S_Mode_SlaveRx ((uint16_t)0x0100) 257 #define I2S_Mode_MasterTx ((uint16_t)0x0200) 258 #define I2S_Mode_MasterRx ((uint16_t)0x0300) 259 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ 260 ((MODE) == I2S_Mode_SlaveRx) || \ 261 ((MODE) == I2S_Mode_MasterTx)|| \ 262 ((MODE) == I2S_Mode_MasterRx)) 263 /** 264 * @} 265 */ 266 267 /** @defgroup SPI_I2S_Standard 268 * @{ 269 */ 270 271 #define I2S_Standard_Phillips ((uint16_t)0x0000) 272 #define I2S_Standard_MSB ((uint16_t)0x0010) 273 #define I2S_Standard_LSB ((uint16_t)0x0020) 274 #define I2S_Standard_PCMShort ((uint16_t)0x0030) 275 #define I2S_Standard_PCMLong ((uint16_t)0x00B0) 276 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ 277 ((STANDARD) == I2S_Standard_MSB) || \ 278 ((STANDARD) == I2S_Standard_LSB) || \ 279 ((STANDARD) == I2S_Standard_PCMShort) || \ 280 ((STANDARD) == I2S_Standard_PCMLong)) 281 /** 282 * @} 283 */ 284 285 /** @defgroup SPI_I2S_Data_Format 286 * @{ 287 */ 288 289 #define I2S_DataFormat_16b ((uint16_t)0x0000) 290 #define I2S_DataFormat_16bextended ((uint16_t)0x0001) 291 #define I2S_DataFormat_24b ((uint16_t)0x0003) 292 #define I2S_DataFormat_32b ((uint16_t)0x0005) 293 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ 294 ((FORMAT) == I2S_DataFormat_16bextended) || \ 295 ((FORMAT) == I2S_DataFormat_24b) || \ 296 ((FORMAT) == I2S_DataFormat_32b)) 297 /** 298 * @} 299 */ 300 301 /** @defgroup SPI_I2S_MCLK_Output 302 * @{ 303 */ 304 305 #define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE 306 #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) 307 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ 308 ((OUTPUT) == I2S_MCLKOutput_Disable)) 309 /** 310 * @} 311 */ 312 313 /** @defgroup SPI_I2S_Audio_Frequency 314 * @{ 315 */ 316 317 #define I2S_AudioFreq_192k ((uint32_t)192000) 318 #define I2S_AudioFreq_96k ((uint32_t)96000) 319 #define I2S_AudioFreq_48k ((uint32_t)48000) 320 #define I2S_AudioFreq_44k ((uint32_t)44100) 321 #define I2S_AudioFreq_32k ((uint32_t)32000) 322 #define I2S_AudioFreq_22k ((uint32_t)22050) 323 #define I2S_AudioFreq_16k ((uint32_t)16000) 324 #define I2S_AudioFreq_11k ((uint32_t)11025) 325 #define I2S_AudioFreq_8k ((uint32_t)8000) 326 #define I2S_AudioFreq_Default ((uint32_t)2) 327 328 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ 329 ((FREQ) <= I2S_AudioFreq_192k)) || \ 330 ((FREQ) == I2S_AudioFreq_Default)) 331 /** 332 * @} 333 */ 334 335 /** @defgroup SPI_I2S_Clock_Polarity 336 * @{ 337 */ 338 339 #define I2S_CPOL_Low ((uint16_t)0x0000) 340 #define I2S_CPOL_High SPI_I2SCFGR_CKPOL 341 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ 342 ((CPOL) == I2S_CPOL_High)) 343 /** 344 * @} 345 */ 346 347 /** @defgroup SPI_FIFO_reception_threshold 348 * @{ 349 */ 350 351 #define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000) 352 #define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH 353 #define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \ 354 ((THRESHOLD) == SPI_RxFIFOThreshold_QF)) 355 /** 356 * @} 357 */ 358 359 /** @defgroup SPI_I2S_DMA_transfer_requests 360 * @{ 361 */ 362 363 #define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN 364 #define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN 365 #define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00)) 366 /** 367 * @} 368 */ 369 370 /** @defgroup SPI_last_DMA_transfers 371 * @{ 372 */ 373 374 #define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000) 375 #define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000) 376 #define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000) 377 #define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000) 378 #define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \ 379 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \ 380 ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \ 381 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd)) 382 /** 383 * @} 384 */ 385 /** @defgroup SPI_NSS_internal_software_management 386 * @{ 387 */ 388 389 #define SPI_NSSInternalSoft_Set SPI_CR1_SSI 390 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) 391 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ 392 ((INTERNAL) == SPI_NSSInternalSoft_Reset)) 393 /** 394 * @} 395 */ 396 397 /** @defgroup SPI_CRC_Transmit_Receive 398 * @{ 399 */ 400 401 #define SPI_CRC_Tx ((uint8_t)0x00) 402 #define SPI_CRC_Rx ((uint8_t)0x01) 403 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) 404 /** 405 * @} 406 */ 407 408 /** @defgroup SPI_direction_transmit_receive 409 * @{ 410 */ 411 412 #define SPI_Direction_Rx ((uint16_t)0xBFFF) 413 #define SPI_Direction_Tx ((uint16_t)0x4000) 414 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ 415 ((DIRECTION) == SPI_Direction_Tx)) 416 /** 417 * @} 418 */ 419 420 /** @defgroup SPI_I2S_interrupts_definition 421 * @{ 422 */ 423 424 #define SPI_I2S_IT_TXE ((uint8_t)0x71) 425 #define SPI_I2S_IT_RXNE ((uint8_t)0x60) 426 #define SPI_I2S_IT_ERR ((uint8_t)0x50) 427 428 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ 429 ((IT) == SPI_I2S_IT_RXNE) || \ 430 ((IT) == SPI_I2S_IT_ERR)) 431 432 #define I2S_IT_UDR ((uint8_t)0x53) 433 #define SPI_IT_MODF ((uint8_t)0x55) 434 #define SPI_I2S_IT_OVR ((uint8_t)0x56) 435 #define SPI_I2S_IT_FRE ((uint8_t)0x58) 436 437 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ 438 ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \ 439 ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR)) 440 /** 441 * @} 442 */ 443 444 445 /** @defgroup SPI_transmission_fifo_status_level 446 * @{ 447 */ 448 449 #define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000) 450 #define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) 451 #define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) 452 #define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800) 453 454 /** 455 * @} 456 */ 457 458 /** @defgroup SPI_reception_fifo_status_level 459 * @{ 460 */ 461 #define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000) 462 #define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) 463 #define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) 464 #define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600) 465 466 /** 467 * @} 468 */ 469 470 471 /** @defgroup SPI_I2S_flags_definition 472 * @{ 473 */ 474 475 #define SPI_I2S_FLAG_RXNE SPI_SR_RXNE 476 #define SPI_I2S_FLAG_TXE SPI_SR_TXE 477 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE 478 #define I2S_FLAG_UDR SPI_SR_UDR 479 #define SPI_FLAG_CRCERR SPI_SR_CRCERR 480 #define SPI_FLAG_MODF SPI_SR_MODF 481 #define SPI_I2S_FLAG_OVR SPI_SR_OVR 482 #define SPI_I2S_FLAG_BSY SPI_SR_BSY 483 #define SPI_I2S_FLAG_FRE SPI_SR_FRE 484 485 486 487 #define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) 488 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ 489 ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ 490 ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ 491 ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \ 492 ((FLAG) == I2S_FLAG_UDR)) 493 /** 494 * @} 495 */ 496 497 /** @defgroup SPI_CRC_polynomial 498 * @{ 499 */ 500 501 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) 502 /** 503 * @} 504 */ 505 506 /** 507 * @} 508 */ 509 510 /* Exported macro ------------------------------------------------------------*/ 511 /* Exported functions ------------------------------------------------------- */ 512 513 /* Initialization and Configuration functions *********************************/ 514 void SPI_I2S_DeInit(SPI_TypeDef* SPIx); 515 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); 516 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for HK32F030 devices */ 517 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); 518 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for HK32F030 devices */ 519 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 520 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 521 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 522 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); /*!< Not applicable for HK32F030 devices */ 523 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); 524 void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold); 525 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); 526 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); 527 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 528 529 /* Data transfers functions ***************************************************/ 530 void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data); 531 void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data); 532 uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx); 533 uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx); 534 535 /* Hardware CRC Calculation functions *****************************************/ 536 void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength); 537 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); 538 void SPI_TransmitCRC(SPI_TypeDef* SPIx); 539 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); 540 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); 541 542 /* DMA transfers management functions *****************************************/ 543 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 544 void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer); 545 546 /* Interrupts and flags management functions **********************************/ 547 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 548 uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx); 549 uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx); 550 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 551 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 552 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 553 554 #ifdef __cplusplus 555 } 556 #endif 557 558 #endif /*__HK32F0XX_SPI_H */ 559 560 /** 561 * @} 562 */ 563 564 /** 565 * @} 566 */ 567 568