1 /** 2 ****************************************************************************** 3 * @file hk32f0xx_syscfg.h 4 * @version V1.0.1 5 * @date 2019-08-15 6 ****************************************************************************** 7 */ 8 9 /*!< Define to prevent recursive inclusion -------------------------------------*/ 10 #ifndef __HK32F0XX_SYSCFG_H 11 #define __HK32F0XX_SYSCFG_H 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /*!< Includes ------------------------------------------------------------------*/ 18 #include "hk32f0xx.h" 19 20 /** @addtogroup HK32F0xx_StdPeriph_Driver 21 * @{ 22 */ 23 24 /** @addtogroup SYSCFG 25 * @{ 26 */ 27 /* Exported types ------------------------------------------------------------*/ 28 /* Exported constants --------------------------------------------------------*/ 29 30 /** @defgroup SYSCFG_Exported_Constants 31 * @{ 32 */ 33 34 /** @defgroup SYSCFG_EXTI_Port_Sources 35 * @{ 36 */ 37 #define EXTI_PortSourceGPIOA ((uint8_t)0x00) 38 #define EXTI_PortSourceGPIOB ((uint8_t)0x01) 39 #define EXTI_PortSourceGPIOC ((uint8_t)0x02) 40 #define EXTI_PortSourceGPIOD ((uint8_t)0x03) /*!< not available for HK32F031 devices */ 41 #define EXTI_PortSourceGPIOF ((uint8_t)0x05) 42 43 #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ 44 ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ 45 ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ 46 ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ 47 ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ 48 ((PORTSOURCE) == EXTI_PortSourceGPIOF)) 49 /** 50 * @} 51 */ 52 53 /** @defgroup SYSCFG_EXTI_Pin_sources 54 * @{ 55 */ 56 #define EXTI_PinSource0 ((uint8_t)0x00) 57 #define EXTI_PinSource1 ((uint8_t)0x01) 58 #define EXTI_PinSource2 ((uint8_t)0x02) 59 #define EXTI_PinSource3 ((uint8_t)0x03) 60 #define EXTI_PinSource4 ((uint8_t)0x04) 61 #define EXTI_PinSource5 ((uint8_t)0x05) 62 #define EXTI_PinSource6 ((uint8_t)0x06) 63 #define EXTI_PinSource7 ((uint8_t)0x07) 64 #define EXTI_PinSource8 ((uint8_t)0x08) 65 #define EXTI_PinSource9 ((uint8_t)0x09) 66 #define EXTI_PinSource10 ((uint8_t)0x0A) 67 #define EXTI_PinSource11 ((uint8_t)0x0B) 68 #define EXTI_PinSource12 ((uint8_t)0x0C) 69 #define EXTI_PinSource13 ((uint8_t)0x0D) 70 #define EXTI_PinSource14 ((uint8_t)0x0E) 71 #define EXTI_PinSource15 ((uint8_t)0x0F) 72 73 #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ 74 ((PINSOURCE) == EXTI_PinSource1) || \ 75 ((PINSOURCE) == EXTI_PinSource2) || \ 76 ((PINSOURCE) == EXTI_PinSource3) || \ 77 ((PINSOURCE) == EXTI_PinSource4) || \ 78 ((PINSOURCE) == EXTI_PinSource5) || \ 79 ((PINSOURCE) == EXTI_PinSource6) || \ 80 ((PINSOURCE) == EXTI_PinSource7) || \ 81 ((PINSOURCE) == EXTI_PinSource8) || \ 82 ((PINSOURCE) == EXTI_PinSource9) || \ 83 ((PINSOURCE) == EXTI_PinSource10) || \ 84 ((PINSOURCE) == EXTI_PinSource11) || \ 85 ((PINSOURCE) == EXTI_PinSource12) || \ 86 ((PINSOURCE) == EXTI_PinSource13) || \ 87 ((PINSOURCE) == EXTI_PinSource14) || \ 88 ((PINSOURCE) == EXTI_PinSource15)) 89 /** 90 * @} 91 */ 92 93 /** @defgroup SYSCFG_Memory_Remap_Config 94 * @{ 95 */ 96 #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) 97 #define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01) 98 #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) 99 100 101 #define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ 102 ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \ 103 ((REMAP) == SYSCFG_MemoryRemap_SRAM)) 104 105 /** 106 * @} 107 */ 108 109 /** @defgroup SYSCFG_DMA_Remap_Config 110 * @{ 111 */ 112 113 #define SYSCFG_DMARemap_USART3 SYSCFG_CFGR1_USART3_DMA_RMP /* Remap USART3 DMA requests from channel6/7 to channel3/2 */ 114 115 #define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */ 116 #define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */ 117 #define SYSCFG_DMARemap_USART1Rx SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */ 118 #define SYSCFG_DMARemap_USART1Tx SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */ 119 #define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */ 120 121 #define IS_SYSCFG_DMA_REMAP(REMAP) ( ((REMAP) == SYSCFG_DMARemap_USART3) || \ 122 ((REMAP) == SYSCFG_DMARemap_TIM17) || \ 123 ((REMAP) == SYSCFG_DMARemap_TIM16) || \ 124 ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \ 125 ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \ 126 ((REMAP) == SYSCFG_DMARemap_ADC1)) 127 128 /** 129 * @} 130 */ 131 132 /** @defgroup SYSCFG_I2C_FastModePlus_Config 133 * @{ 134 */ 135 #define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */ 136 #define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */ 137 #define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */ 138 #define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */ 139 #define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /* Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for HK32F0031 and HK32F030 devices) */ 140 #define SYSCFG_I2CFastModePlus_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /* Enable Fast Mode Plus on PA9 (only for HK32F031 and HK32F030 devices) */ 141 #define SYSCFG_I2CFastModePlus_PA10 SYSCFG_CFGR1_I2C_FMP_PA10/* Enable Fast Mode Plus on PA10(only for HK32F031 and HK32F030 devices) */ 142 143 #define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \ 144 ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \ 145 ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \ 146 ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \ 147 ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \ 148 ((PIN) == SYSCFG_I2CFastModePlus_PA9) || \ 149 ((PIN) == SYSCFG_I2CFastModePlus_PA10)) 150 151 152 /** 153 * @} 154 */ 155 156 /** @defgroup SYSCFG_Lock_Config 157 * @{ 158 */ 159 #define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1 */ 160 #define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */ 161 #define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */ 162 163 #define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \ 164 ((CONFIG) == SYSCFG_Break_SRAMParity) || \ 165 ((CONFIG) == SYSCFG_Break_Lockup)) 166 167 /** 168 * @} 169 */ 170 171 /** @defgroup SYSCFG_flags_definition 172 * @{ 173 */ 174 175 #define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE 176 177 #define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE)) 178 179 /** 180 * @} 181 */ 182 183 /** @defgroup SYSCFG_ISR_WRAPPER 184 * @{ 185 */ 186 #define SYSCFG_ITLINE0 ((uint32_t) 0x00000000) 187 #define SYSCFG_ITLINE1 ((uint32_t) 0x00000001) 188 #define SYSCFG_ITLINE2 ((uint32_t) 0x00000002) 189 #define SYSCFG_ITLINE3 ((uint32_t) 0x00000003) 190 #define SYSCFG_ITLINE4 ((uint32_t) 0x00000004) 191 #define SYSCFG_ITLINE5 ((uint32_t) 0x00000005) 192 #define SYSCFG_ITLINE6 ((uint32_t) 0x00000006) 193 #define SYSCFG_ITLINE7 ((uint32_t) 0x00000007) 194 #define SYSCFG_ITLINE8 ((uint32_t) 0x00000008) 195 #define SYSCFG_ITLINE9 ((uint32_t) 0x00000009) 196 #define SYSCFG_ITLINE10 ((uint32_t) 0x0000000A) 197 #define SYSCFG_ITLINE11 ((uint32_t) 0x0000000B) 198 #define SYSCFG_ITLINE12 ((uint32_t) 0x0000000C) 199 #define SYSCFG_ITLINE13 ((uint32_t) 0x0000000D) 200 #define SYSCFG_ITLINE14 ((uint32_t) 0x0000000E) 201 #define SYSCFG_ITLINE15 ((uint32_t) 0x0000000F) 202 #define SYSCFG_ITLINE16 ((uint32_t) 0x00000010) 203 #define SYSCFG_ITLINE17 ((uint32_t) 0x00000011) 204 #define SYSCFG_ITLINE18 ((uint32_t) 0x00000012) 205 #define SYSCFG_ITLINE19 ((uint32_t) 0x00000013) 206 #define SYSCFG_ITLINE20 ((uint32_t) 0x00000014) 207 #define SYSCFG_ITLINE21 ((uint32_t) 0x00000015) 208 #define SYSCFG_ITLINE22 ((uint32_t) 0x00000016) 209 #define SYSCFG_ITLINE23 ((uint32_t) 0x00000017) 210 #define SYSCFG_ITLINE24 ((uint32_t) 0x00000018) 211 #define SYSCFG_ITLINE25 ((uint32_t) 0x00000019) 212 #define SYSCFG_ITLINE26 ((uint32_t) 0x0000001A) 213 #define SYSCFG_ITLINE27 ((uint32_t) 0x0000001B) 214 #define SYSCFG_ITLINE28 ((uint32_t) 0x0000001C) 215 #define SYSCFG_ITLINE29 ((uint32_t) 0x0000001D) 216 #define SYSCFG_ITLINE30 ((uint32_t) 0x0000001E) 217 #define SYSCFG_ITLINE31 ((uint32_t) 0x0000001F) 218 219 #define ITLINE_EWDG ((uint32_t) ((SYSCFG_ITLINE0 << 0x18) | SYSCFG_ITLINE0_SR_EWDG)) /* EWDG Interrupt */ 220 #define ITLINE_PVDOUT ((uint32_t) ((SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_PVDOUT)) /* Power voltage detection Interrupt */ 221 #define ITLINE_VDDIO2 ((uint32_t) ((SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_VDDIO2)) /* VDDIO2 Interrupt */ 222 #define ITLINE_RTC_WAKEUP ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /* RTC WAKEUP -> exti[20] Interrupt */ 223 #define ITLINE_RTC_TSTAMP ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /* RTC Time Stamp -> exti[19] interrupt */ 224 #define ITLINE_RTC_ALRA ((uint32_t) ((SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /* RTC Alarm -> exti[17] interrupt */ 225 #define ITLINE_FLASH_ITF ((uint32_t) ((SYSCFG_ITLINE3 << 0x18) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /* Flash ITF Interrupt */ 226 #define ITLINE_CRS ((uint32_t) ((SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CRS)) /* CRS Interrupt */ 227 #define ITLINE_CLK_CTRL ((uint32_t) ((SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /* CLK Control Interrupt */ 228 #define ITLINE_EXTI0 ((uint32_t) ((SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI0)) /* External Interrupt 0 */ 229 #define ITLINE_EXTI1 ((uint32_t) ((SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI1)) /* External Interrupt 1 */ 230 #define ITLINE_EXTI2 ((uint32_t) ((SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI2)) /* External Interrupt 2 */ 231 #define ITLINE_EXTI3 ((uint32_t) ((SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI3)) /* External Interrupt 3 */ 232 #define ITLINE_EXTI4 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI4)) /* EXTI4 Interrupt */ 233 #define ITLINE_EXTI5 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI5)) /* EXTI5 Interrupt */ 234 #define ITLINE_EXTI6 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI6)) /* EXTI6 Interrupt */ 235 #define ITLINE_EXTI7 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI7)) /* EXTI7 Interrupt */ 236 #define ITLINE_EXTI8 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI8)) /* EXTI8 Interrupt */ 237 #define ITLINE_EXTI9 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI9)) /* EXTI9 Interrupt */ 238 #define ITLINE_EXTI10 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI10)) /* EXTI10 Interrupt */ 239 #define ITLINE_EXTI11 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI11)) /* EXTI11 Interrupt */ 240 #define ITLINE_EXTI12 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI12)) /* EXTI12 Interrupt */ 241 #define ITLINE_EXTI13 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI13)) /* EXTI13 Interrupt */ 242 #define ITLINE_EXTI14 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI14)) /* EXTI14 Interrupt */ 243 #define ITLINE_EXTI15 ((uint32_t) ((SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI15)) /* EXTI15 Interrupt */ 244 #define ITLINE_TSC_EOA ((uint32_t) ((SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_EOA)) /* Touch control EOA Interrupt */ 245 #define ITLINE_TSC_MCE ((uint32_t) ((SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_MCE)) /* Touch control MCE Interrupt */ 246 #define ITLINE_DMA1_CH1 ((uint32_t) ((SYSCFG_ITLINE9 << 0x18) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /* DMA1 Channel 1 Interrupt */ 247 #define ITLINE_DMA1_CH2 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /* DMA1 Channel 2 Interrupt */ 248 #define ITLINE_DMA1_CH3 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /* DMA1 Channel 3 Interrupt */ 249 #define ITLINE_DMA2_CH1 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /* DMA2 Channel 1 Interrupt */ 250 #define ITLINE_DMA2_CH2 ((uint32_t) ((SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /* DMA2 Channel 2 Interrupt */ 251 #define ITLINE_DMA1_CH4 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /* DMA1 Channel 4 Interrupt */ 252 #define ITLINE_DMA1_CH5 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /* DMA1 Channel 5 Interrupt */ 253 #define ITLINE_DMA1_CH6 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /* DMA1 Channel 6 Interrupt */ 254 #define ITLINE_DMA1_CH7 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /* DMA1 Channel 7 Interrupt */ 255 #define ITLINE_DMA2_CH3 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /* DMA2 Channel 3 Interrupt */ 256 #define ITLINE_DMA2_CH4 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /* DMA2 Channel 4 Interrupt */ 257 #define ITLINE_DMA2_CH5 ((uint32_t) ((SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /* DMA2 Channel 5 Interrupt */ 258 #define ITLINE_ADC ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_ADC)) /* ADC Interrupt */ 259 #define ITLINE_COMP1 ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP1)) /* COMP1 Interrupt -> exti[21] */ 260 #define ITLINE_COMP2 ((uint32_t) ((SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP2)) /* COMP2 Interrupt -> exti[21] */ 261 #define ITLINE_TIM1_BRK ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /* TIM1 BRK Interrupt */ 262 #define ITLINE_TIM1_UPD ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /* TIM1 UPD Interrupt */ 263 #define ITLINE_TIM1_TRG ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /* TIM1 TRG Interrupt */ 264 #define ITLINE_TIM1_CCU ((uint32_t) ((SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /* TIM1 CCU Interrupt */ 265 #define ITLINE_TIM1_CC ((uint32_t) ((SYSCFG_ITLINE14 << 0x18) | SYSCFG_ITLINE14_SR_TIM1_CC)) /* TIM1 CC Interrupt */ 266 #define ITLINE_TIM2 ((uint32_t) ((SYSCFG_ITLINE15 << 0x18) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /* TIM2 Interrupt */ 267 #define ITLINE_TIM3 ((uint32_t) ((SYSCFG_ITLINE16 << 0x18) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /* TIM3 Interrupt */ 268 #define ITLINE_DAC ((uint32_t) ((SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_DAC)) /* DAC Interrupt */ 269 #define ITLINE_TIM6 ((uint32_t) ((SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /* TIM6 Interrupt */ 270 #define ITLINE_TIM7 ((uint32_t) ((SYSCFG_ITLINE18 << 0x18) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /* TIM7 Interrupt */ 271 #define ITLINE_TIM14 ((uint32_t) ((SYSCFG_ITLINE19 << 0x18) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /* TIM14 Interrupt */ 272 #define ITLINE_TIM15 ((uint32_t) ((SYSCFG_ITLINE20 << 0x18) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /* TIM15 Interrupt */ 273 #define ITLINE_TIM16 ((uint32_t) ((SYSCFG_ITLINE21 << 0x18) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /* TIM16 Interrupt */ 274 #define ITLINE_TIM17 ((uint32_t) ((SYSCFG_ITLINE22 << 0x18) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /* TIM17 Interrupt */ 275 #define ITLINE_I2C1 ((uint32_t) ((SYSCFG_ITLINE23 << 0x18) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /* I2C1 Interrupt -> exti[23] */ 276 #define ITLINE_I2C2 ((uint32_t) ((SYSCFG_ITLINE24 << 0x18) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /* I2C2 Interrupt */ 277 #define ITLINE_SPI1 ((uint32_t) ((SYSCFG_ITLINE25 << 0x18) | SYSCFG_ITLINE25_SR_SPI1)) /* I2C1 Interrupt -> exti[23] */ 278 #define ITLINE_SPI2 ((uint32_t) ((SYSCFG_ITLINE26 << 0x18) | SYSCFG_ITLINE26_SR_SPI2)) /* SPI1 Interrupt */ 279 #define ITLINE_USART1 ((uint32_t) ((SYSCFG_ITLINE27 << 0x18) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */ 280 #define ITLINE_USART2 ((uint32_t) ((SYSCFG_ITLINE28 << 0x18) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */ 281 #define ITLINE_USART3 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART3_GLB)) /* USART3 Interrupt */ 282 #define ITLINE_USART4 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART4_GLB)) /* USART4 Interrupt */ 283 #define ITLINE_USART5 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART5_GLB)) /* USART5 Interrupt */ 284 #define ITLINE_USART6 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART6_GLB)) /* USART6 Interrupt */ 285 #define ITLINE_USART7 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART7_GLB)) /* USART7 Interrupt */ 286 #define ITLINE_USART8 ((uint32_t) ((SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART8_GLB)) /* USART8 Interrupt */ 287 #define ITLINE_CAN ((uint32_t) ((SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CAN)) /* CAN Interrupt */ 288 #define ITLINE_CEC ((uint32_t) ((SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CEC)) /* CEC Interrupt -> exti[27] */ 289 290 #define IS_SYSCFG_ITLINE(LINE) (((LINE) == ITLINE_EWDG) || \ 291 ((LINE) == ITLINE_PVDOUT) || \ 292 ((LINE) == ITLINE_VDDIO2) || \ 293 ((LINE) == ITLINE_RTC_WAKEUP) || \ 294 ((LINE) == ITLINE_RTC_TSTAMP) || \ 295 ((LINE) == ITLINE_RTC_ALRA) || \ 296 ((LINE) == ITLINE_FLASH_ITF) || \ 297 ((LINE) == ITLINE_CRS) || \ 298 ((LINE) == ITLINE_CLK_CTRL) || \ 299 ((LINE) == ITLINE_EXTI0) || \ 300 ((LINE) == ITLINE_EXTI1) || \ 301 ((LINE) == ITLINE_EXTI2) || \ 302 ((LINE) == ITLINE_EXTI3) || \ 303 ((LINE) == ITLINE_EXTI4) || \ 304 ((LINE) == ITLINE_EXTI5) || \ 305 ((LINE) == ITLINE_EXTI6) || \ 306 ((LINE) == ITLINE_EXTI7) || \ 307 ((LINE) == ITLINE_EXTI8) || \ 308 ((LINE) == ITLINE_EXTI9) || \ 309 ((LINE) == ITLINE_EXTI10) || \ 310 ((LINE) == ITLINE_EXTI11) || \ 311 ((LINE) == ITLINE_EXTI12) || \ 312 ((LINE) == ITLINE_EXTI13) || \ 313 ((LINE) == ITLINE_EXTI14) || \ 314 ((LINE) == ITLINE_EXTI15) || \ 315 ((LINE) == ITLINE_TSC_EOA) || \ 316 ((LINE) == ITLINE_TSC_MCE) || \ 317 ((LINE) == ITLINE_DMA1_CH1) || \ 318 ((LINE) == ITLINE_DMA1_CH2) || \ 319 ((LINE) == ITLINE_DMA1_CH3) || \ 320 ((LINE) == ITLINE_DMA1_CH4) || \ 321 ((LINE) == ITLINE_DMA1_CH5) || \ 322 ((LINE) == ITLINE_DMA1_CH6) || \ 323 ((LINE) == ITLINE_DMA1_CH7) || \ 324 ((LINE) == ITLINE_DMA2_CH1) || \ 325 ((LINE) == ITLINE_DMA2_CH2) || \ 326 ((LINE) == ITLINE_DMA2_CH3) || \ 327 ((LINE) == ITLINE_DMA2_CH4) || \ 328 ((LINE) == ITLINE_DMA2_CH5) || \ 329 ((LINE) == ITLINE_ADC) || \ 330 ((LINE) == ITLINE_COMP1) || \ 331 ((LINE) == ITLINE_COMP2) || \ 332 ((LINE) == ITLINE_TIM1_BRK) || \ 333 ((LINE) == ITLINE_TIM1_UPD) || \ 334 ((LINE) == ITLINE_TIM1_TRG) || \ 335 ((LINE) == ITLINE_TIM1_CCU) || \ 336 ((LINE) == ITLINE_TIM1_CC) || \ 337 ((LINE) == ITLINE_TIM2) || \ 338 ((LINE) == ITLINE_TIM3) || \ 339 ((LINE) == ITLINE_DAC) || \ 340 ((LINE) == ITLINE_TIM6) || \ 341 ((LINE) == ITLINE_TIM7) || \ 342 ((LINE) == ITLINE_TIM14) || \ 343 ((LINE) == ITLINE_TIM15) || \ 344 ((LINE) == ITLINE_TIM16) || \ 345 ((LINE) == ITLINE_TIM17) || \ 346 ((LINE) == ITLINE_I2C1) || \ 347 ((LINE) == ITLINE_I2C2) || \ 348 ((LINE) == ITLINE_SPI1) || \ 349 ((LINE) == ITLINE_SPI2) || \ 350 ((LINE) == ITLINE_USART1) || \ 351 ((LINE) == ITLINE_USART2) || \ 352 ((LINE) == ITLINE_USART3) || \ 353 ((LINE) == ITLINE_USART4) || \ 354 ((LINE) == ITLINE_USART5) || \ 355 ((LINE) == ITLINE_USART6) || \ 356 ((LINE) == ITLINE_USART7) || \ 357 ((LINE) == ITLINE_USART8) || \ 358 ((LINE) == ITLINE_CAN) || \ 359 ((LINE) == ITLINE_CEC)) 360 361 /** 362 * @} 363 */ 364 /** @defgroup IRDA_ENV_SEL 365 * @{ 366 */ 367 #define SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0&SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* Timer16 is selected as IRDA Modulation envelope source */ 368 #define SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* USART1 is selected as IRDA Modulation envelope source.*/ 369 #define SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* USART4 is selected as IRDA Modulation envelope source.*/ 370 371 #define IS_SYSCFG_IRDA_ENV(ENV) (((ENV) == SYSCFG_IRDA_ENV_SEL_TIM16) || \ 372 ((ENV) == SYSCFG_IRDA_ENV_SEL_USART1) || \ 373 ((ENV) == SYSCFG_IRDA_ENV_SEL_USART4)) 374 /** 375 * @} 376 */ 377 378 /** 379 * @} 380 */ 381 382 /* Exported macro ------------------------------------------------------------*/ 383 /* Exported functions ------------------------------------------------------- */ 384 385 /* Function used to set the SYSCFG configuration to the default reset state **/ 386 void SYSCFG_DeInit(void); 387 388 /* SYSCFG configuration functions *********************************************/ 389 void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap); 390 void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState); 391 void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState); 392 void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv); 393 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); 394 uint32_t SYSCFG_GetPendingIT(uint32_t ITSourceLine); 395 void SYSCFG_BreakConfig(uint32_t SYSCFG_Break); 396 FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag); 397 void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag); 398 399 #ifdef __cplusplus 400 } 401 #endif 402 403 #endif /*__HK32F0XX_SYSCFG_H */ 404 405 /** 406 * @} 407 */ 408 409 /** 410 * @} 411 */ 412