1 /* 2 * Copyright (c) 2022-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef HPM_DMA_MGR_H 9 #define HPM_DMA_MGR_H 10 11 #include "hpm_common.h" 12 #include "hpm_dmamux_drv.h" 13 #include "hpm_dmamux_src.h" 14 #ifdef HPMSOC_HAS_HPMSDK_DMAV2 15 #include "hpm_dmav2_drv.h" 16 #else 17 #include "hpm_dma_drv.h" 18 #endif 19 #include "hpm_soc_feature.h" 20 21 #ifdef HPMSOC_HAS_HPMSDK_DMAV2 22 #define DMA_MGR_HAS_INFINITE_LOOP (1U) 23 #define DMA_MGR_HAS_HALF_TC_INT (1U) 24 #define DMA_MGR_HAS_HANDSHAKE_OPT (1U) 25 #define DMA_MGR_HAS_BURST_OPT (1U) 26 #if defined(HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS) && (HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS == 1) 27 #define DMA_MGR_HAS_BURST_IN_FIXED_TRANS HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS 28 #else 29 #define DMA_MGR_HAS_BURST_IN_FIXED_TRANS 0 30 #endif 31 #if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1) 32 #define DMA_MGR_HAS_BYTE_ORDER_SWAP HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP 33 #else 34 #define DMA_MGR_HAS_BYTE_ORDER_SWAP 0 35 #endif 36 #endif 37 38 #define DMA_MGR_CHANNEL_PRIORITY_LOW DMA_CHANNEL_PRIORITY_LOW 39 #define DMA_MGR_CHANNEL_PRIORITY_HIGH DMA_CHANNEL_PRIORITY_HIGH 40 41 #define DMA_MGR_NUM_TRANSFER_PER_BURST_1T DMA_NUM_TRANSFER_PER_BURST_1T 42 #define DMA_MGR_NUM_TRANSFER_PER_BURST_2T DMA_NUM_TRANSFER_PER_BURST_2T 43 #define DMA_MGR_NUM_TRANSFER_PER_BURST_4T DMA_NUM_TRANSFER_PER_BURST_4T 44 #define DMA_MGR_NUM_TRANSFER_PER_BURST_8T DMA_NUM_TRANSFER_PER_BURST_8T 45 #define DMA_MGR_NUM_TRANSFER_PER_BURST_16T DMA_NUM_TRANSFER_PER_BURST_16T 46 #define DMA_MGR_NUM_TRANSFER_PER_BURST_32T DMA_NUM_TRANSFER_PER_BURST_32T 47 #define DMA_MGR_NUM_TRANSFER_PER_BURST_64T DMA_NUM_TRANSFER_PER_BURST_64T 48 #define DMA_MGR_NUM_TRANSFER_PER_BURST_128T DMA_NUM_TRANSFER_PER_BURST_128T 49 #define DMA_MGR_NUM_TRANSFER_PER_BURST_256T DMA_NUM_TRANSFER_PER_BURST_256T 50 #define DMA_MGR_NUM_TRANSFER_PER_BURST_512T DMA_NUM_TRANSFER_PER_BURST_512T 51 #define DMA_MGR_NUM_TRANSFER_PER_BURST_1024T DMA_NUM_TRANSFER_PER_BURST_1024T 52 53 #define DMA_MGR_TRANSFER_WIDTH_BYTE DMA_TRANSFER_WIDTH_BYTE 54 #define DMA_MGR_TRANSFER_WIDTH_HALF_WORD DMA_TRANSFER_WIDTH_HALF_WORD 55 #define DMA_MGR_TRANSFER_WIDTH_WORD DMA_TRANSFER_WIDTH_WORD 56 #define DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD DMA_TRANSFER_WIDTH_DOUBLE_WORD 57 58 #define DMA_MGR_HANDSHAKE_MODE_NORMAL DMA_HANDSHAKE_MODE_NORMAL 59 #define DMA_MGR_HANDSHAKE_MODE_HANDSHAKE DMA_HANDSHAKE_MODE_HANDSHAKE 60 61 #define DMA_MGR_ADDRESS_CONTROL_INCREMENT DMA_ADDRESS_CONTROL_INCREMENT 62 #define DMA_MGR_ADDRESS_CONTROL_DECREMENT DMA_ADDRESS_CONTROL_DECREMENT 63 #define DMA_MGR_ADDRESS_CONTROL_FIXED DMA_ADDRESS_CONTROL_FIXED 64 65 #if defined(DMA_MGR_HAS_BURST_OPT) && DMA_MGR_HAS_BURST_OPT 66 #define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE DMA_SRC_BURST_OPT_STANDAND_SIZE 67 #define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE DMA_SRC_BURST_OPT_CUSTOM_SIZE 68 #else 69 #define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE 0 70 #define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE 0 71 #endif 72 73 #if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT 74 #define DMA_MGR_HANDSHAKE_OPT_ONE_BURST DMA_HANDSHAKE_OPT_ONE_BURST 75 #define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE DMA_HANDSHAKE_OPT_ALL_TRANSIZE 76 #else 77 #define DMA_MGR_HANDSHAKE_OPT_ONE_BURST 0 78 #define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE 0 79 #endif 80 81 #define DMA_MGR_CHANNEL_STATUS_ONGOING DMA_CHANNEL_STATUS_ONGOING 82 #define DMA_MGR_CHANNEL_STATUS_ERROR DMA_CHANNEL_STATUS_ERROR 83 #define DMA_MGR_CHANNEL_STATUS_ABORT DMA_CHANNEL_STATUS_ABORT 84 #define DMA_MGR_CHANNEL_STATUS_TC DMA_CHANNEL_STATUS_TC 85 #if defined(DMA_MGR_HAS_HALF_TC_INT) && DMA_MGR_HAS_HALF_TC_INT 86 #define DMA_MGR_CHANNEL_STATUS_HALF_TC DMA_CHANNEL_STATUS_HALF_TC 87 #else 88 #define DMA_MGR_CHANNEL_STATUS_HALF_TC 0 89 #endif 90 #define DMA_MGR_INTERRUPT_MASK_NONE DMA_INTERRUPT_MASK_NONE 91 #define DMA_MGR_INTERRUPT_MASK_ERROR DMA_INTERRUPT_MASK_ERROR 92 #define DMA_MGR_INTERRUPT_MASK_ABORT DMA_INTERRUPT_MASK_ABORT 93 #define DMA_MGR_INTERRUPT_MASK_TC DMA_INTERRUPT_MASK_TERMINAL_COUNT 94 #if defined(DMA_MGR_HAS_HALF_TC_INT) && DMA_MGR_HAS_HALF_TC_INT 95 #define DMA_MGR_INTERRUPT_MASK_HALF_TC DMA_INTERRUPT_MASK_HALF_TC 96 #else 97 #define DMA_MGR_INTERRUPT_MASK_HALF_TC 0 98 #endif 99 #define DMA_MGR_INTERRUPT_MASK_ALL DMA_INTERRUPT_MASK_ALL 100 101 #if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP 102 #define DMA_MGR_SWAP_MODE_TABLE DMA_SWAP_MODE_TABLE 103 #define DMA_MGR_SWAP_MODE_BYTE DMA_SWAP_MODE_BYTE 104 #define DMA_MGR_SWAP_MODE_HALF_WORD DMA_SWAP_MODE_HALF_WORD 105 #define DMA_MGR_SWAP_MODE_WORD DMA_SWAP_MODE_WORD 106 #else 107 #define DMA_MGR_SWAP_MODE_TABLE 0 108 #define DMA_MGR_SWAP_MODE_BYTE 0 109 #define DMA_MGR_SWAP_MODE_HALF_WORD 0 110 #define DMA_MGR_SWAP_MODE_WORD 0 111 #endif 112 113 #ifdef __cplusplus 114 115 extern "C" { 116 #endif 117 118 /** 119 * @brief DMA Manager status codes 120 */ 121 enum { 122 status_dma_mgr_no_resource = MAKE_STATUS(status_group_dma_manager, 0), /**< No DMA resource available */ 123 }; 124 125 /** 126 * @brief DMA Channel Interrupt callback 127 * 128 * @param [in] DMA base address 129 * @param [in] channel DMA channel index 130 * @param [in/out] cb_data_ptr callback Data pointer 131 */ 132 typedef void (*dma_mgr_chn_cb_t)(DMA_Type *base, uint32_t channel, void *cb_data_ptr); 133 134 /** 135 * @brief DMA Resource Structure 136 */ 137 typedef struct _dma_resource { 138 DMA_Type *base; /**< The DMA intance that the allocated channel belongs to */ 139 uint32_t channel; /**< Channel index */ 140 int32_t irq_num; /**< DMA IRQ number */ 141 } dma_resource_t; 142 143 typedef struct hpm_dma_mgr_chn_conf { 144 bool en_dmamux; /**< DMAMUX enable */ 145 uint8_t dmamux_src; /**< DMAMUX source */ 146 uint8_t priority; /**< Channel priority */ 147 uint8_t src_burst_size; /**< Source burst size */ 148 uint8_t src_mode; /**< Source work mode: 0-Normal, 1-Handshake */ 149 uint8_t dst_mode; /**< Destination work mode: 0-Normal, 1-Handshake */ 150 uint8_t src_width; /**< Source width */ 151 uint8_t dst_width; /**< Destination width */ 152 uint8_t src_addr_ctrl; /**< Source address control: 0-inc, 1-dec, 2-fix */ 153 uint8_t dst_addr_ctrl; /**< Destination address control: 0-inc, 1-dec, 2-fix */ 154 uint16_t interrupt_mask; /**< Interrupt mask */ 155 uint32_t src_addr; /**< Source address */ 156 uint32_t dst_addr; /**< Destination address */ 157 uint32_t linked_ptr; /**< Next linked descriptor */ 158 uint32_t size_in_byte; /**< Total size to be transferred in byte */ 159 bool en_infiniteloop; /**< Infinite loop transfer enable. Attention: only DMAV2 support */ 160 uint8_t handshake_opt; /**< Handshake transfer option. Attention: only DMAV2 support */ 161 uint8_t burst_opt; /**< Burst size option. Attention: only DMAV2 support */ 162 bool en_src_burst_in_fixed_trans; /**< Source address burst in fix transfer size enable, discard src_addr_ctrl setting. Attention: only DMAV2 support */ 163 bool en_dst_burst_in_fixed_trans; /**< Destination address burst in fix transfer size enable, discard dst_addr_ctrl setting. Attention: only DMAV2 support */ 164 uint8_t swap_mode; /**< Swap Mode. Attention: only DMAV2 support */ 165 uint32_t swap_table; /**< Swap Table. Attention: only DMAV2 support */ 166 } dma_mgr_chn_conf_t; 167 168 typedef struct hpm_dma_mgr_linked_descriptor { 169 uint32_t descriptor[8]; 170 } dma_mgr_linked_descriptor_t; 171 172 /** 173 * @brief DMA Manager ISR handler 174 */ 175 void dma_mgr_isr_handler(DMA_Type *ptr, uint32_t instance); 176 177 /** 178 * @brief Initialize DMA Manager Context 179 */ 180 void dma_mgr_init(void); 181 182 /** 183 * @brief Request DMA resource from DMA Manager 184 * 185 * @param [out] resource DMA resource 186 * @retval status_success if no error occurred 187 * @retval status_invalid_argument if the parameter is invalid 188 * @retval status_dma_mgr_no_resource if all DMA channels are occupied; 189 */ 190 hpm_stat_t dma_mgr_request_resource(dma_resource_t *resource); 191 192 /** 193 * @brief Release DMA resource 194 * 195 * @param [in] resource DMA resource 196 * 197 * @retval status_success if no error occurred 198 * @retval status_invalid_argument if the parameter is invalid 199 */ 200 hpm_stat_t dma_mgr_release_resource(const dma_resource_t *resource); 201 202 /** 203 * @brief Enable DMA interrupt with priority 204 * @param [in] resource DMA resource 205 * @param [in] priority Interrupt Priority 206 * 207 * @retval status_success if no error occurred 208 * @retval status_invalid_argument if any parameters are invalid 209 */ 210 hpm_stat_t dma_mgr_enable_dma_irq_with_priority(const dma_resource_t *resource, uint32_t priority); 211 212 /** 213 * @brief Disable DMA interrupt 214 * NOTE: Each DMA instance consists of several DMA channels, disabling the DMA interrupt 215 * will disable the global DMA interrupt for all DMA channels. Please be aware of the 216 * impact 217 * @param [in] resource DMA resource 218 * 219 * @retval status_success if no error occurred 220 * @retval status_invalid_argument if any parameters are invalid 221 */ 222 hpm_stat_t dma_mgr_disable_dma_irq(const dma_resource_t *resource); 223 224 /** 225 * @brief Install Interrupt Callback for DMA channel transfer complete 226 * 227 * @param [in] resource DMA resource 228 * @param [in] callback Interrupt callback for DMA resource 229 * @param [in] user_data User data used in the callback 230 * 231 * @retval status_success if no error occurred 232 * @retval status_invalid_argument if any parameters are invalid 233 */ 234 hpm_stat_t dma_mgr_install_chn_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); 235 236 /** 237 * @brief Install Interrupt Callback for DMA channel half transfer complete 238 * 239 * @param [in] resource DMA resource 240 * @param [in] callback Interrupt callback for DMA resource 241 * @param [in] user_data User data used in the callback 242 * 243 * @retval status_success if no error occurred 244 * @retval status_invalid_argument if any parameters are invalid 245 */ 246 hpm_stat_t dma_mgr_install_chn_half_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); 247 248 /** 249 * @brief Install Interrupt Callback for DMA channel transfer error 250 * 251 * @param [in] resource DMA resource 252 * @param [in] callback Interrupt callback for DMA resource 253 * @param [in] user_data User data used in the callback 254 * 255 * @retval status_success if no error occurred 256 * @retval status_invalid_argument if any parameters are invalid 257 */ 258 hpm_stat_t dma_mgr_install_chn_error_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); 259 260 /** 261 * @brief Install Interrupt Callback for DMA channel transfer abort 262 * 263 * @param [in] resource DMA resource 264 * @param [in] callback Interrupt callback for DMA resource 265 * @param [in] user_data User data used in the callback 266 * 267 * @retval status_success if no error occurred 268 * @retval status_invalid_argument if any parameters are invalid 269 */ 270 hpm_stat_t dma_mgr_install_chn_abort_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); 271 272 /** 273 * @brief Get DMA channel default config 274 * 275 * @param [out] config config data pointer 276 */ 277 void dma_mgr_get_default_chn_config(dma_mgr_chn_conf_t *config); 278 279 /** 280 * @brief Setup channel config 281 * 282 * @param [in] resource DMA resource 283 * @param [in] config DMA channel config 284 * 285 * @retval status_success if no error occurred 286 * @retval status_invalid_argument if any parameters are invalid 287 */ 288 hpm_stat_t dma_mgr_setup_channel(const dma_resource_t *resource, dma_mgr_chn_conf_t *config); 289 290 /** 291 * @brief Setup chain linked descriptor config 292 * 293 * @param [in] resource DMA resource 294 * @param [in] config DMA channel config 295 * @param [out] descriptor linked descriptor config data pointer 296 * 297 * @retval status_success if no error occurred 298 * @retval status_invalid_argument if any parameters are invalid 299 */ 300 hpm_stat_t dma_mgr_config_linked_descriptor(const dma_resource_t *resource, dma_mgr_chn_conf_t *config, dma_mgr_linked_descriptor_t *descriptor); 301 302 /** 303 * @brief Enable DMA channel, start transfer 304 * 305 * @param [in] resource DMA resource 306 * 307 * @retval status_success if no error occurred 308 * @retval status_invalid_argument if any parameters are invalid 309 */ 310 hpm_stat_t dma_mgr_enable_channel(const dma_resource_t *resource); 311 312 /** 313 * @brief Disable DMA channel 314 * 315 * @param [in] resource DMA resource 316 * 317 * @retval status_success if no error occurred 318 * @retval status_invalid_argument if any parameters are invalid 319 */ 320 hpm_stat_t dma_mgr_disable_channel(const dma_resource_t *resource); 321 322 /** 323 * @brief Check DMA channel enable status 324 * 325 * @param [in] resource DMA resource 326 * @param [out] enable enable status 327 * 328 * @retval status_success if no error occurred 329 * @retval status_invalid_argument if any parameters are invalid 330 */ 331 hpm_stat_t dma_mgr_check_chn_enable(const dma_resource_t *resource, bool *enable); 332 333 /** 334 * @brief Enable DMA channel interrupt 335 * @param [in] resource DMA resource 336 * 337 * @retval status_success if no error occurred 338 * @retval status_invalid_argument if any parameters are invalid 339 */ 340 hpm_stat_t dma_mgr_enable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask); 341 342 /** 343 * @brief Disable DMA channel interrupt 344 * @param [in] resource DMA resource 345 * 346 * @retval status_success if no error occurred 347 * @retval status_invalid_argument if any parameters are invalid 348 */ 349 hpm_stat_t dma_mgr_disable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask); 350 351 /** 352 * @brief Set DMA channel priority 353 * 354 * @param [in] resource DMA resource 355 * @param [in] priority DMA channel priority 356 * @arg @ref DMA_MGR_PRIORITY_LOW 357 * @arg @ref DMA_MGR_PRIORITY_HIGH 358 * 359 * @retval status_success if no error occurred 360 * @retval status_invalid_argument if any parameters are invalid 361 */ 362 hpm_stat_t dma_mgr_set_chn_priority(const dma_resource_t *resource, uint8_t priority); 363 364 /** 365 * @brief Set DMA channel source work mode 366 * 367 * @param [in] resource DMA resource 368 * @param [in] mode DMA source work mode 369 * @arg @ref DMA_MGR_HANDSHAKE_MODE_NORMAL 370 * @arg @ref DMA_MGR_HANDSHAKE_MODE_HANDSHAKE 371 * 372 * @retval status_success if no error occurred 373 * @retval status_invalid_argument if any parameters are invalid 374 */ 375 hpm_stat_t dma_mgr_set_chn_src_work_mode(const dma_resource_t *resource, uint8_t mode); 376 377 /** 378 * @brief Set DMA channel destination work mode 379 * 380 * @param [in] resource DMA resource 381 * @param [in] mode DMA destination work mode 382 * @arg @ref DMA_MGR_HANDSHAKE_MODE_NORMAL 383 * @arg @ref DMA_MGR_HANDSHAKE_MODE_HANDSHAKE 384 * 385 * @retval status_success if no error occurred 386 * @retval status_invalid_argument if any parameters are invalid 387 */ 388 hpm_stat_t dma_mgr_set_chn_dst_work_mode(const dma_resource_t *resource, uint8_t mode); 389 390 /** 391 * @brief Set DMA channel source burst size 392 * 393 * @param [in] resource DMA resource 394 * @param [in] burstsize DMA source burst size 395 * when BURSTOPT is 0, please reference follows: 396 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_1T 397 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_2T 398 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_4T 399 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_8T 400 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_16T 401 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_32T 402 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_64T 403 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_128T 404 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_256T 405 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_512T 406 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_1024T 407 * when BURSTOPT is 1, burst size is (burstsize + 1). Attention: only DMAV2 support 408 * 409 * @retval status_success if no error occurred 410 * @retval status_invalid_argument if any parameters are invalid 411 */ 412 hpm_stat_t dma_mgr_set_chn_src_burst_size(const dma_resource_t *resource, uint8_t burstsize); 413 414 /** 415 * @brief Get DMA channel remaining transfer size 416 * 417 * @param [in] resource DMA resource 418 * @param [out] size remaining transfer size of the channel. 419 * 420 * @retval status_success if no error occurred 421 * @retval status_invalid_argument if any parameters are invalid 422 */ 423 hpm_stat_t dma_mgr_get_chn_remaining_transize(const dma_resource_t *resource, uint32_t *size); 424 425 /** 426 * @brief Set DMA channel transfer size 427 * 428 * @param [in] resource DMA resource 429 * @param [in] size transfer size of the channel. 430 * 431 * @retval status_success if no error occurred 432 * @retval status_invalid_argument if any parameters are invalid 433 */ 434 hpm_stat_t dma_mgr_set_chn_transize(const dma_resource_t *resource, uint32_t size); 435 436 /** 437 * @brief Set DMA channel source width 438 * 439 * @param [in] resource DMA resource 440 * @param [in] width transfer source width of the channel 441 * @arg @ref DMA_MGR_TRANSFER_WIDTH_BYTE 442 * @arg @ref DMA_MGR_TRANSFER_WIDTH_HALF_WORD 443 * @arg @ref DMA_MGR_TRANSFER_WIDTH_WORD 444 * @arg @ref DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD 445 * 446 * @retval status_success if no error occurred 447 * @retval status_invalid_argument if any parameters are invalid 448 */ 449 hpm_stat_t dma_mgr_set_chn_src_width(const dma_resource_t *resource, uint8_t width); 450 451 /** 452 * @brief Set DMA channel destination width 453 * 454 * @param [in] resource DMA resource 455 * @param [in] width transfer destination width of the channel 456 * @arg @ref DMA_MGR_TRANSFER_WIDTH_BYTE 457 * @arg @ref DMA_MGR_TRANSFER_WIDTH_HALF_WORD 458 * @arg @ref DMA_MGR_TRANSFER_WIDTH_WORD 459 * @arg @ref DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD 460 * 461 * @retval status_success if no error occurred 462 * @retval status_invalid_argument if any parameters are invalid 463 */ 464 hpm_stat_t dma_mgr_set_chn_dst_width(const dma_resource_t *resource, uint8_t width); 465 466 /** 467 * @brief Set DMA channel source address 468 * 469 * @param [in] resource DMA resource 470 * @param [in] addr source address 471 * 472 * @retval status_success if no error occurred 473 * @retval status_invalid_argument if any parameters are invalid 474 */ 475 hpm_stat_t dma_mgr_set_chn_src_addr(const dma_resource_t *resource, uint32_t addr); 476 477 /** 478 * @brief Set DMA channel destination address 479 * 480 * @param [in] resource DMA resource 481 * @param [in] addr destination address 482 * 483 * @retval status_success if no error occurred 484 * @retval status_invalid_argument if any parameters are invalid 485 */ 486 hpm_stat_t dma_mgr_set_chn_dst_addr(const dma_resource_t *resource, uint32_t addr); 487 488 /** 489 * @brief Set DMA channel source address control mode 490 * 491 * @param [in] resource DMA resource 492 * @param [in] addr_ctrl source address control mode 493 * @arg @ref DMA_MGR_ADDRESS_CONTROL_INCREMENT 494 * @arg @ref DMA_MGR_ADDRESS_CONTROL_DECREMENT 495 * @arg @ref DMA_MGR_ADDRESS_CONTROL_FIXED 496 * 497 * @retval status_success if no error occurred 498 * @retval status_invalid_argument if any parameters are invalid 499 */ 500 hpm_stat_t dma_mgr_set_chn_src_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl); 501 502 /** 503 * @brief Set DMA channel destination address control mode 504 * 505 * @param [in] resource DMA resource 506 * @param [in] addr_ctrl destination address control mode 507 * @arg @ref DMA_MGR_ADDRESS_CONTROL_INCREMENT 508 * @arg @ref DMA_MGR_ADDRESS_CONTROL_DECREMENT 509 * @arg @ref DMA_MGR_ADDRESS_CONTROL_FIXED 510 * 511 * @retval status_success if no error occurred 512 * @retval status_invalid_argument if any parameters are invalid 513 */ 514 hpm_stat_t dma_mgr_set_chn_dst_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl); 515 516 /** 517 * @brief Set DMA channel infinite loop mode. Attention: only DMAV2 support 518 * 519 * @param [in] resource DMA resource 520 * @param [in] infinite_loop false - normal mode(single times mode); true - infinite loop mode(cycle mode) 521 * 522 * @retval status_success if no error occurred 523 * @retval status_invalid_argument if any parameters are invalid 524 */ 525 hpm_stat_t dma_mgr_set_chn_infinite_loop_mode(const dma_resource_t *resource, bool infinite_loop); 526 527 /** 528 * @brief Set DMA channel source burst option. Attention: only DMAV2 support 529 * 530 * @param [in] resource DMA resource 531 * @param [in] burst_opt burst option 532 * @arg @ref DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE 533 * @arg @ref DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE 534 * 535 * @retval status_success if no error occurred 536 * @retval status_invalid_argument if any parameters are invalid 537 */ 538 hpm_stat_t dma_mgr_set_chn_src_busrt_option(const dma_resource_t *resource, uint8_t burst_opt); 539 540 /** 541 * @brief Set DMA channel handshake option. Attention: only DMAV2 support 542 * 543 * @param [in] resource DMA resource 544 * @param [in] handshake_opt handshake option 545 * @arg @ref DMA_HANDSHAKE_OPT_ONE_BURST 546 * @arg @ref DMA_HANDSHAKE_OPT_ALL_TRANSIZE 547 * 548 * @retval status_success if no error occurred 549 * @retval status_invalid_argument if any parameters are invalid 550 */ 551 hpm_stat_t dma_mgr_set_chn_handshake_option(const dma_resource_t *resource, uint8_t handshake_opt); 552 553 /** 554 * @brief Abort DMA channel transfer 555 * 556 * @param [in] resource DMA resource 557 * 558 * @retval status_success if no error occurred 559 * @retval status_invalid_argument if any parameters are invalid 560 */ 561 hpm_stat_t dma_mgr_abort_chn_transfer(const dma_resource_t *resource); 562 563 /** 564 * @brief Check DMA channel transfer status 565 * 566 * @param [in] resource DMA resource 567 * @param [out] sts transfer status 568 * DMA_MGR_CHANNEL_STATUS_ONGOING if transfer is still ongoing 569 * DMA_MGR_CHANNEL_STATUS_ERROR if any error occurred during transferring 570 * DMA_MGR_CHANNEL_STATUS_ABORT if transfer is aborted 571 * DMA_MGR_CHANNEL_STATUS_TC if transfer is finished without error 572 * DMA_MGR_CHANNEL_STATUS_HALF_TC if half transfer complete without error. Attention: only DMAV2 support 573 * 574 * @retval status_success if no error occurred 575 * @retval status_invalid_argument if any parameters are invalid 576 */ 577 hpm_stat_t dma_mgr_check_chn_transfer_status(const dma_resource_t *resource, uint32_t *status); 578 579 /** 580 * @brief Set DMA channel source burst in fixed transfer size enable or disable 581 * 582 * @param [in] resource DMA resource 583 * @param[in] enable false - disable; true - enable 584 * 585 */ 586 hpm_stat_t dma_mgr_set_source_burst_in_fixed_transize_enable(const dma_resource_t *resource, bool enable); 587 588 /** 589 * @brief Set DMA channel destination burst in fixed transfer size enable or disable 590 * 591 * @param [in] resource DMA resource 592 * @param[in] enable false - disable; true - enable 593 * 594 */ 595 hpm_stat_t dma_mgr_set_destination_burst_in_fix_transize_enable(const dma_resource_t *resource, bool enable); 596 597 /** 598 * @brief Set DMA channel swap mode 599 * 600 * @param [in] resource DMA resource 601 * @param[in] swap_mode swap mode 602 * @arg @ref DMA_MGR_SWAP_MODE_TABLE 603 * @arg @ref DMA_MGR_SWAP_MODE_BYTE 604 * @arg @ref DMA_MGR_SWAP_MODE_HALF_WORD 605 * @arg @ref DMA_MGR_SWAP_MODE_WORD 606 * 607 */ 608 hpm_stat_t dma_mgr_set_swap_mode(const dma_resource_t *resource, uint8_t swap_mode); 609 610 /** 611 * @brief Set DMA channel swap table 612 * 613 * @param [in] resource DMA resource 614 * @param[in] swap_table swap table 615 * 616 */ 617 hpm_stat_t dma_mgr_set_swap_table(const dma_resource_t *resource, uint32_t swap_table); 618 619 #ifdef __cplusplus 620 } 621 #endif 622 623 #endif /* HPM_DMA_MGR_H */ 624